JP2900686B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device related to a CMOS type LSI and a method of manufacturing the same.

[0002]

BACKGROUND ART will be described with reference to FIG. 4 for a conventional CMOS-type LSI (especially the LDD structure MOS transistors). Figure 4 is a cross-sectional view illustrating an n-channel transistor of a conventional LDD structure, which is an element isolation region formed in the channel stop region 6 and the field oxide film 8, the low-concentration n-type diffusion layer (n ^- diffusion Layer 13) and high concentration n
-Type diffusion layer are composed of (n ⁺ diffusion layer 16), and said isolation region and (6,8) lightly doped n-type diffusion layer ^- is formed so as to (n diffusion layer 13) are in contact with .
In FIG. 4 , 1 is a p-type silicon substrate (Si substrate), 9 is a gate oxide film, 10 is a gate electrode, 14 is a side wall, and W _{1 in} FIG. ₂ indicates the distance between the low concentration n-type diffusion layers (n ⁻ diffusion layers) 13.

Next, conventional CMOS LSIs (particularly LDs)
N-channel D structure, the process for producing the p-channel two transistors) will be described with reference to FIG. 5, this conventional type p, a process sequence sectional views showing a manufacturing method of n both channel transistor, first, as shown in FIG. 5 Step A, p-type silicon substrate 1 having an n-well 2 ( Less than,
It is called Si substrate 1. ), A pad oxide film 3 composed of a silicon oxide film (hereinafter simply referred to as an oxide film) having a thickness of 200 to 600 Å and a silicon nitride film 4 (hereinafter simply referred to as a nitride film 4) having a thickness of about 1000 Å. ) Is deposited.

[0004] Then, the nitride film 4 is selectively left in the element formation region by photolithography and dry etching techniques, and is masked with a photoresist 5 to form a channel stop region 6 (see 6 in the next step B). Perform boron ion implantation. The ion implantation conditions in this case are as follows: energy 100 to 200 keV, dose 1 × 10 ¹² to 10 ¹³ / cm ²
It is about.

[0005] Next, as shown in FIG. 5 step B, the photoresist is removed 5, the Si substrate 1 was heated and oxidized at about 1000 ° C., to form a field oxide film 8 to the channel stop region 6. During this thermal oxidation, the portion of the Si substrate 1 covered with the nitride film 4 is not oxidized, and only a thin oxide film 7 is formed on the surface of the nitride film 4. The steps so far are element isolation steps called LOCOS.

[0006] Next, as shown in FIG. 5 step C, the nitride film 4
After removing the thin oxide film 7 and the pad oxide film 3 on the surface thereof, the Si substrate 1 is oxidized to form a gate oxide film 9, and then polysilicon (not shown) is formed by CVD.
Is deposited, and a gate electrode 10 is formed through a photolithography and dry etching process. Thereafter, a photoresist (not shown) is formed by opening only on the n-well 2, boron ions are implanted in a self-aligned manner, and a low-concentration p-type diffusion layer ( hereinafter referred to as a p ^- diffusion layer 11) is n. Well 2
Then, a photoresist 1 is formed on the n-well 2.
2 and implant phosphorus ions to form a low concentration n-type diffusion layer.
( Hereinafter, referred to as n ⁻ diffusion layer 13) is formed in a self-aligned manner.

[0007] Next, as shown in FIG. 5 step D, the photoresist is removed 12, after depositing an oxide film (not shown) by a CVD method, forming the side wall 14 of the oxide film is etched I do. Thereafter, the p ^- diffusion layer 11,
By the same means as in the step C in which the n ^- diffusion layer 13 is formed,
Boron ion implantation is performed in a photoresist pattern (not shown) that opens on the n-well 2 and arsenic ion implantation is performed in a self-aligned manner using a pattern (not shown) that covers the n-well 2. Then, a heat treatment for activating these two dopants is performed to form a high-concentration p-type diffusion layer ( hereinafter referred to as p ⁺ diffusion layer 15) and a high-concentration n-type diffusion layer ( hereinafter referred to as n ⁺ diffusion layer 16). A p-channel and n-channel transistor is manufactured.

[0008]

Problems in the above-mentioned conventional CMOS LSI and its manufacturing method will be described with reference to FIGS. 4 and 5 taking an n-channel transistor as an example. In order to achieve high integration, it is necessary to reduce also the element isolation width, the fact that reducing the element isolation width, in other words, that Hasameru the opening space of the nitride film 4 in step A of FIG. 5 According to this,
There is a problem that the field oxide film 8 becomes thin.

Further, the n-channel transistor of the LDD structure shown in FIG. 4, n which form the source and drain regions
^{In general,} arsenic is introduced into the ⁺ diffusion layer 16 and phosphorus is introduced into the n ⁻ diffusion layer 13 as impurities.
Phosphorus has a large thermal diffusion coefficient in silicon, so that a deep diffusion layer is formed on both sides of the field oxide film 8. The element isolation region formed by the channel stop region 6 and the field oxide film 8 and the n ⁻ diffusion layer 13 are formed. Are formed so as to contact with.

[0010] As a result, the element isolation width, i.e., W ₁ in FIG. 4
In order to reduce the size, the distance W ₂ between the n ⁻ diffusion layers 13 is reduced, and the reduction in W _{2 and} the reduction in the thickness of the field oxide film 8 combine to reduce the distance between adjacent transistors. However, there is a problem that the breakdown voltage between the high-concentration n-type diffusion layers ( between the n ⁺ diffusion layers 16) is deteriorated. As described above, the n-channel transistor has been described, but it goes without saying that the p-channel transistor also has the same problem. (Monthly SemiconductorWorld March 1991 p1
12-117).

Accordingly, an object of the present invention is to provide a semiconductor device which solves the above-mentioned conventional problems and a method of manufacturing the same. In particular, the present invention relates to an LDD structure MOS having an element isolation region, a low concentration diffusion layer region and a high concentration diffusion layer region.
It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can prevent deterioration of the breakdown voltage between diffusion layers (the high-concentration diffusion layers) serving as a source and a drain of an adjacent transistor even if the element isolation region is reduced in the transistor. Aim.

[0012]

According to the present invention, there is provided a semiconductor device formed such that a channel stop region, an element isolation region formed of a field oxide film, and a low concentration diffusion layer region are not in contact with each other, and a method of manufacturing the same. This achieves the object of the present invention of preventing the deterioration of the breakdown voltage between the diffusion layers of the adjacent transistors (high-concentration diffusion layers) even if the dimensions of the element isolation regions are reduced. is there.

That is, a semiconductor device according to the present invention comprises an element isolation region, a low-concentration diffusion layer region, and a high-concentration diffusion layer region.
In the MOS transistor having the DD structure, the low concentration diffusion layer region having the LDD structure may be disposed under the high concentration diffusion layer region.
Diffusion layer with low concentration by compensating and diffusing impurities of opposite conductivity type
In the presence of a region, by this, the said device isolation region are allowed to be present without contacting the low-concentration diffusion layer region and the low concentrations present in proximity to the device isolation region and
A semiconductor device comprising: a transistor in which the changed diffusion layer region functions as a low-concentration carrier layer. It is the gist.

Further, the method of manufacturing a semiconductor device according to the present invention includes: (1) a step of depositing a pad oxide film and a silicon nitride film on the surface of a p-type silicon substrate having an n-well formed therein; and (2) photolithography and dry etching. A step of forming a channel stop region by selectively leaving a nitride film in an element formation region by a technique and masking with a photoresist, and (3) removing the photoresist and heating and oxidizing the p-type silicon substrate to form a channel stop region. (4) removing the nitride film and pad oxide film, oxidizing the p-type silicon substrate to form a gate oxide film, and then forming a gate electrode; (5) self-aligned manner by ion implantation, forming a low concentration first conductivity type <br/> diffusion layer in a self-aligned manner, after depositing an oxide film by (6) CVD method, etching the oxide film Forming a sidewall and grayed, (7) a self-aligned manner by ion implantation, a high concentration by thermal treatment
Forming a first conductivity type diffusion layer, comprising: an element isolation region, a low concentration first conductivity type diffusion layer region and a high concentration first conductivity type diffusion layer region;
In the method for manufacturing an S transistor, following the step (7), (8) an oxide film is deposited by a CVD method, and then the oxide film is etched back to form a second sidewall. drain and the step of performing a self-aligned ion-implanted the opposite conductivity type impurities by thermal treatment (9), a low concentration first proximate the isolation region
One conductivity type carrier layer and said low concentration first conductivity type carrier layer
Forming a lightly doped opposite-conductivity-type impurity layer of the bottom,
The gist of the present invention is a method of manufacturing a semiconductor device, characterized by including:

Hereinafter, the present invention will be described in detail. The semiconductor device (CMOS LSI) of the present invention will be described in detail with reference to FIG. FIG. 1 shows the structure of a semiconductor device according to the present invention.
FIG. 7 is a view for explaining an example of the structure, and shows an n-type LDD structure.
FIG. 3 is a cross-sectional view illustrating a channel transistor.

The CMOS LSI of the present invention has an element isolation region formed by a channel stop region 6 and a field oxide film 8, a low concentration n-type diffusion layer (n ^- diffusion layer 13 ) and a high concentration n-type diffusion layer (n ⁺ Diffusion layer 16 ) . Soshi
Thus, below the high concentration n-type diffusion layer (n ⁺ diffusion layer 16),
Another low-concentration n-type diffusion layer (n ^- diffusion layer 13)
Close the diffusion layer region (low-concentration carrier layer 18) to the device isolation region.
The low-concentration diffusion layer area (low-concentration carrier)
Layer 18), a reverse-concentration low-concentration diffusion layer region (low
It consists configured to present the concentration p-type impurity layer 19), this
As a result, the element isolation region and the low concentration diffusion layer region (the n ⁻ diffusion layer
13 ) is formed so as to be present without contact. In addition, low-concentration diffusion existing close to the element isolation region
The layer region functions as a “low concentration carrier layer 18”.
Is formed.

[0017] In FIG. 1, 1 is a Si substrate, a gate oxide film 9, 10 denotes a gate electrode, 14 is a side wall, also, W ₁ in FIG. 1 shows an isolation width,
W ₂ indicates the distance between the n ⁻ diffusion layers 13. That is, C of the present invention
MOS type LSI without also be reduced in size of the element isolation width W ₁ shorten W ₂ dimension between the low-concentration diffusion layer region, LDD type n structure separating the desired distance, the two transistors of the p-channel Have.

The operation of the CMOS LSI of the present invention will be described.
LDD structure n-channel transistor shown in FIG.
To explain, W₁Field oxide film 8 with reduction in size
Becomes thinner,⁺Diffusion layer 16(High concentration n-type diffusion layer)
Can be separated by the field oxide film 8 and n^-Expansion
Layer 13(Low concentration n-type diffusion layer)Distance W between_TwoRelease enough
The n of the adjacent transistor⁺-N⁺Diffusion layer1
6No action can be taken to ensure sufficient pressure resistance between
You.

On the other hand, the method of manufacturing a semiconductor device of the present invention
This is a method for manufacturing both n-channel and p-channel transistors having the above structure (structure in which the element isolation region and the low-concentration diffusion layer region are present without being in contact with each other). This method will be described in detail with reference to the following examples. In the following examples, description will be made mainly on the manufacturing method. However, the obtained n-channel and p-channel transistors (in the following examples, n-channel transistors will be described as examples) will be described. This also corresponds to the embodiment of the structure of the semiconductor device .

[0020]

【Example】

( Example ) FIG. 2 shows an example (embodiment) of a method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a view for explaining Example ), and is a cross-sectional view in the order of manufacturing steps of an n-channel transistor. The manufacturing method of this n-channel transistor is based on the side wall (first side wall ).
Lumpur 14a) is formed, the source performs arsenic ion implantation for drain formation, up to the step of by the heat treatment for dopant activation a high concentration n-type diffusion layer (n ⁺ diffusion layer 16), It is the same as the conventional manufacturing method. That is, up to step A in FIG. 2 is the same as step A to step D in FIG. 6 of the above-described conventional method, and therefore, the description is omitted, including the reference numerals, up to step A in FIG.

In the first embodiment, an oxide film (not shown) is formed by a CVD method, as shown in FIG. 2 step B, following the step A in FIG. 2 (corresponding to step D in FIG. 6 of the conventional method). After this is deposited, the oxide film is etched back to form a second sidewall 17, and then, boron ions are implanted in a self-aligned manner. The boron ion implantation conditions in this case were an acceleration energy of 10 keV and a dose of 1.5 × 10 ¹³ / cm ² .

After boron ion implantation, the dopant is activated in a nitrogen atmosphere at 900 ° C. to manufacture an n-channel transistor having a cross-sectional structure shown in step C of FIG. Here, the dose of boron ion implantation is two orders of magnitude lower than the dose of arsenic ion implantation for source / drain formation.
The n ⁺ diffusion layer 16 is formed without being affected by the boron ion implantation.

On the other hand, n ⁻ diffusion layer 13 formed so as to cover n ⁺ diffusion layer 16 (see step B in FIG. 2).
After the boron ion implantation, a low-concentration carrier layer 18 in which boron and phosphorus are present at substantially the same concentration between the field oxide film 8 and the second
^- can be formed separately in the diffusion layer 13, further, the low-concentration p-type impurity layer 19 immediately below the low-concentration carrier layer 18 is formed.
By this method, the low-concentration carrier layer 18 and the low-concentration p
Type impurity layer 19 is divided into an element isolation region and a low concentration diffusion layer region (n
^- can be interposed between both the diffusion layer 13) is prepared as is present without contacting the both.

[0024] In the above embodiment has been described for n-channel transistors, can also be carried out in the same manner for the p-channel transistors, thereby not in contact and the element isolation region and the low concentration diffusion layer regions n, p both A channel transistor can be manufactured.

[0025]

It will be described with reference occurs in the present invention the effect according to the present invention in FIG. FIG. 3 is a diagram showing the relationship between the element isolation width and the diffusion interlayer breakdown voltage. As is clear from FIG. 3 , in the conventional semiconductor device, the practical diffusion interlayer breakdown voltage is 1, and the element isolation width at this time is 1. Assuming that 1 is, in the present invention, this is
It can be understood that it can be reduced to

As described in detail above, in the CMOS LSI of the present invention, even if the element isolation width is reduced by selective oxidation, the distance between the low-concentration diffusion layers serving as the source and drain of the adjacent LDD transistor is sufficiently separated. As a result, a remarkable effect that the breakdown voltage between the diffusion layers can be ensured occurs.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of the structure of a semiconductor device according to the present invention, and is a cross-sectional view illustrating an n-channel transistor having an LDD structure.

FIG. 2 shows an example (embodiment) of a method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a view for explaining Example ), and is a cross-sectional view in a process order for manufacturing an n-channel transistor.

FIG. 3 is a diagram for explaining an effect of the present invention, and is a diagram showing a relationship between an element isolation width and a withstand voltage between diffusion layers.

FIG. 4 is a sectional view showing a conventional n-channel transistor having an LDD structure.

FIG. 5 is a cross-sectional view illustrating a process of manufacturing a conventional p-channel and n-channel transistor having an LDD structure.

[Explanation of symbols]

Reference Signs List 1 Si substrate 2 n-well 3 pad oxide film 4 nitride film 5 photoresist 6 channel stop region 7 thin oxide film 8 field oxide film 9 gate oxide film 10 gate electrode 11 p ^- diffusion layer 12 photoresist 13 n ^- diffusion layer 14 side Wall 14 a First sidewall 15 p ⁺ diffusion layer 16 n ⁺ diffusion layer 17 second sidewall 18 low-concentration carrier layer 19 low-concentration p-type impurity layer

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/8234 H01L 21/336 H01L 27/088 H01L 29/78

Claims (2)

(57) [Claims] 1. A device isolation region, in the LDD structure MOS transistor having a low concentration diffusion layer region and the high concentration diffusion layer regions, the lower part of the high concentration diffusion layer regions, the low dark LDD structure
Low-concentration by compensating and diffusing impurities of the opposite conductivity type into the diffusion layer region
The presence of the diffusion layer region became, by this, are allowed to be present without contact with said and said isolation region low-concentration diffusion layer region and a said low concentration present in proximity to the isolation region
A transistor in which the diffusion layer region functions as a low-concentration carrier layer. (2) a step of depositing a pad oxide film and a silicon nitride film on the surface of a p-type silicon substrate having an n-well formed therein; and (2) selective nitriding in an element formation region by photolithography and dry etching. (3) removing the photoresist, heating and oxidizing the p-type silicon substrate to form a field oxide film in the channel stop region, 4) nitride film, after removing the pad oxide film, by oxidizing the p-type silicon substrate to form a gate oxide film, then forming a gate electrode, subjected to (5) self-aligned ion implantation, low A step of forming a first conductivity type diffusion layer in a self-aligned manner; (6) a step of depositing an oxide film by a CVD method and then etching the oxide film to form a sidewall; 7) Self-aligned ion implantation and heat treatment
Forming a first conductivity type diffusion layer, comprising: an element isolation region, a low concentration first conductivity type diffusion layer region and a high concentration first conductivity type diffusion layer region;
In the method for manufacturing an S transistor, following the step (7), further, (8) after depositing an oxide film by the CVD method, etching back the oxide film to form a second sidewall, drain and the step of performing a self-aligned ion-implanted the opposite conductivity type impurities by thermal treatment (9), a low concentration first proximate the isolation region
One conductivity type carrier layer and said low concentration first conductivity type carrier layer
The method of manufacturing a semiconductor device that between the lower portion of the low concentration opposite conductivity type impurity layer, and a step, of forming a.