JPH05226593A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To sufficiently diffuse both N-type impurities and P-type impurities which have been introduced into gate electrodes by a method wherein an N-type gate electrode is annealed longer than a P-type gate electrode. CONSTITUTION:Arsenic to be used as N-type impurities is ion-implanted into a polycrystalline silicon film 17 on the side of an N-type MOSFET; after that, an annealing operation is performed at 1000 deg.C for about 20 second. Then, polycrystalline silicon films 17a, 17b are patterned; gate electrodes for the FET are formed. Ton seeds whose type is the same as that of a channel for the MOSFET are ion-implanted, in a self-aligned manner, into the gate electrodes as well as a P-type well layer and an N-type well layer on bothe sides of them; they are diffused; N-type diffusion layers 18a, 18b and P-type diffusion layers 19a, 19b which are to be used as source regions and drain regions are formed. As ion implantation conditions, arsenic is used for an N-type region and boron is used for a P-type region. After that, the gate electrodes 17a, 17b and the diffusion layers 18a, 18b, 19a, 19b are annealed at 1000 deg.C for 20 seconds. Thereby, it is possible to complete the FET in which the impurities the have been diffused sufficiently into the N-type and P-type gate electrodes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This technology relates to a method of manufacturing a semiconductor device, particularly a fine and high-performance CMOS.

[0002]

2. Description of the Related Art In recent years, with the development of semiconductor technology, miniaturization and high integration of elements have been promoted. It is well known that with the progress of miniaturization of elements, the threshold voltage is drastically lowered with the shortening of the channel of a transistor. Particularly, in the buried conductivity type MIS transistor, since the channel is formed slightly inside the surface of the semiconductor device, the controllability of the drain current by the gate bias is poor, and the short channel effect becomes remarkable. On the other hand, in the surface conductivity type, since the channel is formed close to the interface between the gate insulating film and the semiconductor, the controllability of the drain current by the gate bias is improved as compared with the buried conductivity type. CMOS of N-channel element and P-channel element
A method of using an N-type polycrystalline silicon gate for an N-channel element and a P-type polycrystalline silicon gate for a P-channel element in order to obtain a surface conduction type normally-off transistor having a structure Is often used. An example of a method of forming a gate electrode in such a semiconductor device is shown in FIGS. First, for example, silicon substrate 1
After forming the P-type and N-type well regions 2 and 3, the element isolation insulating film 4 is formed by a commonly used selective oxidation method, for example, to form regions where transistors are to be formed. Then, the gate insulating film 5 is formed on the P-type and N-type well regions 2 and 3. Then, the gate electrodes 6a and 6b of the transistor are formed on the gate insulating film 5 (FIG. 7). Next, ion species of the same type as the channel are ion-implanted into the gate electrode and the P-type or N-type well region on both sides of the gate electrode in a self-aligned manner to cause thermal diffusion to form diffusion layers 7a to be source and drain regions. 7b and 8a,
8b is formed (FIG. 8). After that, the surface-conduction type semiconductor device is completed by the N-channel element and the P-channel element of the CMOS structure through the process of the FET which is usually used.

[0003]

Normally, in order to prevent the short channel effect and the reduction of punch-through resistance, it is necessary to make the depth of the diffusion layer shallow. However, in the above-mentioned forming method, the process of FIG. In the above, since boron ion-implanted into the gate electrode of the P-channel device has a large diffusion coefficient, it is diffused to the surface of the semiconductor substrate and the device characteristics are greatly changed. In order to prevent this, diffusion after ion implantation should be suppressed as much as possible. However, since arsenic or phosphorus that is ion-implanted into the gate electrode of the N-channel element has a smaller diffusion coefficient than boron, it is not sufficiently diffused and the gate electrode The internal resistance increases, which causes deterioration of the driving force of the N-type element.

The present invention has been made in view of the above circumstances, and an object thereof is a method of manufacturing a semiconductor device capable of sufficiently diffusing impurities in each gate electrode and improving the driving force of a transistor. To provide.

[0005]

In order to solve the above-mentioned problems, according to the present invention, the annealing time of the gate electrode introduced with N-type impurities is made longer than the annealing time of the gate electrode introduced with P-type impurities. It is characterized by having done.

[0006]

As described above, by annealing the N-type gate electrode longer than that of the P-type, the difference in diffusion coefficient between the N-type and P-type ions is compensated, and the introduction of impurities into the gate electrode is performed. , P type can be sufficiently performed.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings. 1 to 4 are process drawings showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

First, a P type and an N type are formed on the silicon substrate 11.
After forming the well regions 12 and 13, the element isolation insulating film 14 is formed at 70 ° C. by a selective oxidation method, for example.
It is formed to a thickness of 0 nm. After that, the surface is treated with HCl and O ₂
After thermal oxidation at about 750 ° C. in the atmosphere described above to form a silicon oxide film 15 to be a gate insulating film to a thickness of 10 nm, a gate electrode is formed on the entire surface by, for example, a low pressure CVD method in a SiH ₄ atmosphere. The polycrystalline silicon film 17 is replaced with 20
It is deposited to a thickness of 0 nm. Next, apply resist,
Exposure and development are performed to form a resist pattern 16 in a region other than the N-type MOSFET formation planned region (FIG. 1). Next, for example, arsenic, which is an N-type impurity, is ion-implanted into the polycrystalline silicon film 17 on the N-type MOSFET side under the conditions of an implantation energy of 30 KeV and an implantation dose of 5 × 10 ¹⁵ cm ⁻² using the resist pattern 16 as a mask. After injection
For example, using rapid thermal annealing technology, irradiate for a short time with a lamp using a tungsten filament,
Annealing is performed at 1000 ° C. for about 20 seconds. The temperature of 1000 ° C. at this time is a temperature sufficient to activate the impurities in a short time, and the annealing time is as short as about 20 seconds, so that the diffusion of the impurities in the depth direction can be prevented.

Phosphorus diffusion can be considered as a method of introducing N-type impurities into the region where the N-type MOSFET is to be formed. In this case, instead of the resist layer 16 in FIG. 1, a nitride film having a strong resistance to POCl ₃ which is an introduction gas at the time of phosphorus diffusion is used. The nitride film is SiH ₂ Cl ₂ and NH ₃
In a mixed gas with a mixing ratio of 1: 1 of 0.6 Torr, 7
It is formed to a thickness of 10 nm under the condition of 00 ° C. By patterning, after the nitride film is formed so as to leave only the P-type MOSFET formation region in POCl ₃ atmosphere, 8
Phosphorus diffusion is performed by heating to 50 ° C.

Through these steps, the N-type gate electrode is
The impurity concentration near the interface with the gate insulating film is 2 × 10
It is formed to have a ^{thickness of} about ²⁰ cm ^-3 . Next, the resist film or the nitride film is removed by CDE (chemical dry etching) to remove the polycrystalline silicon layers 17a and 17b.
Is patterned to form the gate electrode of each FET (FIG. 2).

Next, ion species of the same type as the channel of the MOSFET are ion-implanted and diffused into the gate electrode and the P-type and N-type well layers on both sides of the gate electrode in a self-aligned manner to form a source region and a drain region. N-type diffusion layer 1
8a, 18b and P type diffusion layers 19a, 19b are formed (FIG. 3). As the ion implantation conditions, for example, arsenic is used in the N-type region, the implantation energy is 30 KeV, and the implantation amount is 5 × 10 ^15.
cm ⁻² , boron is used in the P-type region, and the implantation energy is 1
The dose was 5 KeV and the implantation amount was 2 × 10 ¹⁵ cm ^-2 .

Thereafter, as in the case where the N-type MOSFET formation-scheduled region is initially formed, the rapid thermal annealing method is used, and the gate electrode 17a, 1000.degree.
17b and diffusion layers 18a, 18b, 19a and 19b were annealed.

Although not shown here, FIG. 2 and FIG.
In between, a resist layer is formed on the P-type MOSFET formation region, an N-type element such as arsenic is injected into the N-type MOSFET formation region, and then the resist layer on the P-type MOSFET formation region is removed by CDE. After that, a resist layer is formed on the N-type MOSFET formation region, a P-type element such as boron is injected into the P-type MOSFET formation region, and then impurities are injected into the entire region by using a rapid thermal annealing method. Annealing is performed at 1000 ° C. for 20 seconds.

Through the above steps, the impurity concentrations near the interface between the N-type gate electrode and the P-type gate electrode and the gate insulating film are 2-3 × 10 ²⁰ cm ⁻³ and 1 × 10 ²⁰ cm, respectively.
It will be about ^-3 . Further, if the impurity concentration of the channel layer under the gate insulating film is higher than 1 × 10 ¹⁷ cm ⁻³ , a current flows through the channel layer without applying a voltage to the gate electrode, which makes it difficult to control the drain current. However, by using this method, diffusion of boron having a large diffusion coefficient into the gate insulating film under the gate electrode can be prevented, and P
-Type and N-type have a channel layer impurity concentration of 1 × 10 ¹⁷ cm
^-Can be kept below ^-3 . The depth of each of the N-type and P-type diffusion layers can be formed to be as shallow as about 0.1 μm, and the impurity concentration of the N-type diffusion layer is 2 × 10 ²⁰ cm ⁻³ , P
The impurity concentration of the mold diffusion layer is about 5 × 10 ²⁰ cm ⁻³ .

After that, an interlayer insulating film 20 such as a silicon oxide film is deposited and formed on the entire surface by a CVD method, contact holes reaching the diffusion layer and the gate electrode are opened in this interlayer insulating film, and an electrode wiring 21 is formed (FIG. 4). ). by this,
For both N-type and P-type, FETs in which impurities are sufficiently diffused into the gate electrode are completed.

As described above, in the CMOS structure, the impurity diffusion to the N-type gate electrode is performed longer than that to the P-type to compensate for the difference in the diffusion coefficient of both N-type and P-type ions. It is possible to sufficiently introduce the impurities described above, and it is possible to avoid deterioration of device performance. (Embodiment 2) Similar to Embodiment 1, another embodiment will be described below in which extra impurity diffusion is performed on the gate electrode in the N-type region.

In this method, it is not necessary to first form a resist layer in a region other than the N-type region, and the formation of the resist pattern 16 is omitted in the step of FIG. That is, as in the first embodiment, the P-type and N-type well layers 12 and 13 are formed on the silicon substrate.
After forming the element isolation insulating film 14, the oxide film 15 and the polycrystalline silicon film 17 are formed, P is formed by patterning.
Type and N type gate electrodes 17a and 17b are formed (FIG. 2).

Here, in the second embodiment, a P-type MOSFET is used.
With the resist layer 51 formed on the formation region (FIG. 5), the N-type MO film is formed using the resist pattern 51 as a mask.
After implanting N-type impurities and arsenic into the gate electrode of the SFET formation region with an implantation energy of 30 KeV and an implantation amount of about 5 × 10 ¹⁵ cm ⁻² , a rapid thermal annealing method is used.
The gate electrode in the N-type MOSFET formation region is annealed at 11000 ° C. for 20 seconds. Then, again, the N-type MOS
Arsenic is implanted in the FET formation region at an energy of 30 KeV,
After implanting with a dose of 5 × 10 ¹⁵ cm ⁻² and removing the resist layer 51 on the P-type MOSFET formation region by CDE,
A resist layer 61 is formed on the N-type MOSFET formation region, and using this as a mask, a P-type impurity such as boron is implanted into the gate electrode, source and drain of the P-type MOSFET formation region with an implantation energy of 15 KeV and an implantation amount of 2 × 10 ¹⁵ c.
Inject to about m ^-2 (Fig. 6). After this, N-type MOSFE
The resist layer 61 on the T formation region is removed by CDE,
1000 ° C, 2 using rapid thermal annealing
Annealing is performed for 0 seconds to diffuse impurities, and
Get the structure of.

In this method, the step of forming the resist pattern 16 shown in FIG. 1 is omitted as compared with the first embodiment, so the number of steps is reduced, but the first time in the state where the N-type gate electrode pattern is formed. Since the impurities are diffused into the P-type well layer, the impurities are diffused into the P-type well layer. As a result, the N-type diffusion layer may be slightly deeper after the second impurity diffusion although it is not so remarkable as boron. .. However, if the concentration of the first N-type impurity to be implanted is reduced or the annealing time is shortened if desired, the depth of the N-type diffusion layer is sufficiently shallow while the impurities are sufficiently diffused in the N-type gate electrode. can do. The subsequent steps (FIG. 4) are performed in the same manner as in Example 1.

[0020]

As described above, according to the present invention, N
By annealing the p-type gate electrode longer than that of the p-type gate electrode, the difference in diffusion coefficient between the p-channel element and the n-channel element is compensated, and impurities in the gate electrode are sufficiently introduced for both n-type and p-type. Therefore, the resistance in the gate electrode can be reduced, and the performance deterioration of the device can be suppressed.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating a first embodiment of the present invention.

FIG. 3 is a sectional view illustrating a first embodiment of the present invention.

FIG. 4 is a sectional view illustrating a first embodiment of the present invention.

FIG. 5 is a sectional view illustrating a second embodiment of the present invention.

FIG. 6 is a sectional view illustrating a second embodiment of the present invention.

FIG. 7 is a sectional view illustrating a conventional example.

FIG. 8 is a sectional view illustrating a conventional example.

[Explanation of symbols]

 1, 11 ... Silicon substrate, 2, 12 ... P-type well region, 3, 13 ... N-type well region, 4, 14 ... Element isolation insulating film, 5, 15 ... Gate insulating film, 16, 51, 61 ... Resist Pattern, 6a, 6b, 17a, 17b ... Gate electrode, 7a, 7b, 18a, 18b, 8a, 8b, 19a, 19b ... Diffusion layer, 9, 20 ... Interlayer insulating film, 10, 21 ... Electrode wiring.

Claims (5)

[Claims] 1. A CMO on a semiconductor substrate via an insulating film.
In a method of manufacturing a semiconductor device in which a gate electrode of an S element is provided and P-type and N-type impurities are introduced into the gate electrodes of the P-channel element and the N-channel element, respectively, which form the CMOS element, A method of manufacturing a semiconductor device, wherein the heat treatment time of the gate electrode of the N-channel element after the introduction of the type impurities is longer than the heat treatment time of the gate electrode of the P-channel element after the introduction of the P-type impurities. 2. The impurity is introduced only into the gate electrode of the N-channel element to carry out the first heat treatment, and then the impurity is introduced into the gate electrode of the P-channel element to carry out the second heat treatment. The method for manufacturing a semiconductor device according to claim 1. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the impurity is introduced into the gate electrodes of the N-channel element and the P-channel element by ion implantation. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the impurity introduction into the gate electrode of the N-channel element and the first heat treatment are performed by thermal diffusion of N-type impurities. 5. A mask layer is formed on the P-channel element region, impurities are introduced only into the N-channel element region, rapid thermal annealing is performed, and then impurities are introduced into the P-channel element region as well to form an N-channel. 3. The method for manufacturing a semiconductor device according to claim 1, wherein rapid thermal annealing is performed on both the element region and the P channel element region.