JP3714757B2 - Manufacturing method of MIS type semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a MIS type semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a miniaturized MIS transistor.
[0002]
MIS is originally an abbreviation for metal (M) -insulator (I) -semiconductor (S), but M is used including not only metals but also conductors (semiconductors and the like) used for insulated gate electrodes. I is typically an oxide (O), but is not limited to an oxide. When an oxide is used, it becomes a MOS.
[0003]
[Prior art]
Electronic devices are widely used in the information and telecommunications industry, and high-integrated semiconductor devices (LSIs) are used in large quantities as component parts. In order to further improve the degree of integration of LSI, further improve high-speed performance, and further reduce power consumption, miniaturization of MOS transistors, which are constituent elements of LSI, is required.
[0004]
FIG. 9 schematically shows a conventional MOS transistor manufacturing method.
A gate oxide film 2 is formed on the surface of the p-type silicon substrate 1 by thermal oxidation, and a polycrystalline silicon layer 3 is grown thereon by CVD, for example, to a thickness of about 200 nm. Note that the periphery of the active region of the silicon substrate 1 is surrounded by a field oxide film (not shown) formed by LOCOS.
[0005]
In order to give conductivity to the polycrystalline silicon layer 3, ion implantation is performed. For example, P ⁺ Ion acceleration energy 20 keV, dose 1 × 10 ¹⁵ cm ^-2 Then, ions are implanted into the polycrystalline silicon layer 3. After the ion implantation, for example, heat treatment is performed at about 1000 ° C. for 10 seconds to activate the ion-implanted impurity (P) and to diffuse the polycrystalline silicon layer 3 evenly. Note that this heat treatment can be replaced by a heat treatment performed later.
[0006]
As shown in FIG. 9B, an upper gate electrode layer 4 having good conductivity made of, for example, tungsten silicide (WSi) is formed on the entire surface of the polycrystalline silicon layer 3 by sputtering or the like with a thickness of about 50 to 200 nm. .
[0007]
A resist pattern is formed on upper gate electrode layer 4, and upper gate electrode layer 4 and polycrystalline silicon layer 3 disposed therebelow are etched using this resist pattern as a mask to form a gate electrode. Thereafter, the resist pattern is removed.
[0008]
As shown in FIG. 9C, P is set using the gate electrode as a mask. ⁺ Ion acceleration energy 20 keV, dose 1 × 10 ¹³ cm ^-2 Ions are implanted to form a low concentration source / drain (LDD) region 9.
[0009]
As shown in FIG. 9D, an insulating film such as silicon oxide is formed over the entire surface of the substrate, and anisotropic etching such as reactive ion etching is performed to leave the sidewall 10 only on the side wall of the gate electrode.
[0010]
Using the gate electrode and the sidewall on the sidewall as a mask, P ⁺ Ion acceleration energy 20 keV, dose 1 × 10 ¹⁵ cm ^-2 Then, high concentration source / drain regions 9a are formed.
[0011]
Thereafter, for example, heat treatment is performed at 1100 ° C. for 10 seconds to activate the implanted impurities and recover crystal defects in the semiconductor substrate caused by the ion implantation.
[0012]
Thereafter, an insulating film is formed on the entire surface of the substrate, openings for forming contacts to the source / drain regions and the gate electrode are formed, and electrodes for making electrical contact with these regions through the openings are formed. .
[0013]
The n channel MOS transistor has been described above as an example. However, in the case of a p channel MOS transistor, all conductivity types are reversed. Boron (B) or the like is used as the p-type impurity. In the case of a CMOS device, a silicon substrate having a p-type region (well) and an n-type region (well) is used, and an n-channel MOS transistor and a p-channel MOS transistor are separately formed.
[0014]
The gate electrode is for controlling the potential of the channel region under the gate insulating film. When the gate electrode is made of metal, the metal diffuses in the gate insulating film and further penetrates into the channel region below it. Therefore, a metal gate electrode is not directly formed on the gate insulating film, but a semiconductor layer such as silicon is interposed. As the semiconductor layer, a silicon layer doped with impurities is usually used.
[0015]
In order to reduce power consumption, a CMOS type circuit is used. In a CMOS LSI, in order to make the characteristics of a p-channel MOS transistor and an n-channel MOS transistor uniform, polycrystalline silicon doped with an n-type impurity is used as the gate electrode of the n-channel MOS transistor, and the gate electrode of the p-channel MOS transistor is used. Uses polycrystalline silicon doped with p-type impurities. With such a structure, a transistor called a surface channel type is formed, so that an integrated circuit resistant to a short channel effect can be formed.
[0016]
It is also possible to use polycrystalline silicon doped with p-type impurities for the gate electrode of the n-channel MOS transistor and polycrystalline silicon doped with n-type impurities for the gate electrode of the p-channel MOS transistor. In this case, a buried channel transistor is formed, and a transistor structure that can increase the speed and improve the current driving capability and can reduce the characteristic variation due to hot carrier injection is provided.
[0017]
As described above, when the gate electrodes of the p-channel MOS transistor and the n-channel MOS transistor are doped with impurities of different conductivity types, the introduction of impurities into the polycrystalline silicon layer to be the gate electrode must be performed in different steps.
[0018]
That is, ion implantation as shown in FIG. 9A is performed by covering the p-channel MOS transistor region with a resist mask and ion-implanting n-type impurities, and covering the n-channel MOS transistor region with a resist mask. The process is performed separately from the step of implanting impurities.
[0019]
With the miniaturization of transistors, the thicknesses of the gate oxide film and the gate semiconductor layer are also reduced. In the ion implantation of the gate semiconductor layer, there has been a problem that the implanted ions do not stay in the semiconductor layer 3 but reach the gate insulating film 2 below and further to the semiconductor substrate below.
[0020]
When impurities enter the gate insulating film, the breakdown voltage of the gate insulating film deteriorates. When impurities are introduced into the surface of the semiconductor substrate, the threshold value of the formed MOS transistor is changed. Therefore, it is desirable to prevent impurities from entering the gate insulating film and the semiconductor substrate thereunder as much as possible.
[0021]
In ion implantation, the depth of penetration of an implanted atom is limited by its size. The smaller the atomic radius and the lighter the atom, the deeper the ion implantation. In particular, p-type impurity B has a long range and easily penetrates the polycrystalline silicon gate electrode layer.
[0022]
In order to prevent deep ion implantation of impurity atoms, it is conceivable to reduce the acceleration energy of ion implantation. However, when the ion implantation apparatus decreases the acceleration energy, the ion current decreases exponentially accordingly. A decrease in acceleration energy leads to a decrease in throughput and is not a practical method in a mass production process.
[0023]
In order to reduce the penetration depth of the implanted impurity atoms, a method of increasing the impurity species can be considered. Instead of implanting B ions, BF ₂ A method of implanting ions has been proposed. Since the mass of the impurity ions is remarkably increased, the penetration depth in ion implantation becomes shallow. However, BF ₂ When ions are used, F is implanted together with B. The presence of F causes phenomena such as enhanced diffusion in the B gate oxide film. That is, even if impurity ions are implanted shallowly in the ion implantation, the impurities easily penetrate the gate insulating film by the subsequent heat treatment.
[0024]
As shown in FIG. 9A, instead of implanting ions immediately after forming the semiconductor gate electrode layer, as shown in FIG. 9B, there is also a method of performing ion implantation after forming the upper gate electrode layer. Conceivable. When ion implantation reaching the semiconductor gate electrode layer is performed, penetration into the gate insulating film occurs, so that ions are implanted into the upper gate electrode layer and then diffused into the semiconductor gate electrode layer.
[0025]
By the way, the upper gate electrode layer 4 is formed of silicide or metal. When the upper gate electrode layer 4 is silicide, the diffusion coefficient of impurities is one to two digits or more higher than that of polycrystalline silicon, which is convenient for introducing impurities to the semiconductor gate electrode layer by diffusion. Instead, since the segregation coefficient is also one or two digits higher, the impurities reaching the interface diffuse into the polycrystalline silicon so that the impurities in the silicide are balanced by one digit to two digits higher. For this reason, the impurity concentration in the polycrystal cannot be increased, and the resistance of this portion is increased. For this reason, when ions are implanted into the upper gate electrode layer 4 and diffused from there to the semiconductor gate electrode layer 3, a sufficient amount of ions are required unless an impurity larger by one or two digits than the necessary impurity amount is implanted. It is impossible to reduce the resistance of crystalline silicon, which is not appropriate when considering mass production.
[0026]
When the upper gate electrode layer 4 is made of metal, impurities are not diffused even if ions are implanted therein and diffused into the semiconductor gate electrode layer.
[0027]
As described above, it is an essential process to perform ion implantation after the semiconductor gate electrode layer is formed.
[0028]
[Problems to be solved by the invention]
As described above, in the miniaturized MIS transistor, when ions are implanted into the semiconductor gate electrode layer, there arises a problem that the implanted impurity atoms penetrate into the gate insulating film and the semiconductor substrate surface therebelow.
[0029]
An object of the present invention is to provide a MIS type semiconductor device capable of introducing a sufficient amount of impurities into a semiconductor gate electrode layer in a miniaturized MIS type transistor without causing impurity atoms to penetrate into the gate insulating film and the semiconductor surface therebelow. It is to provide a manufacturing method.
[0031]
[Means for Solving the Problems]
According to one aspect of the present invention, a step of forming a gate insulating film on a surface of a semiconductor substrate, and then forming a first gate electrode film that can be made into a conductor by doping impurities on the gate insulating film. Forming a second gate electrode film formed of a conductor on the first gate electrode film, and then selectively etching the second gate electrode film, A first etching step of leaving a second gate electrode pattern on the one gate electrode film; and an ion implantation step of implanting impurities into the exposed first gate electrode film using the second gate electrode pattern as a mask; Next, a heat treatment process is performed for performing heat treatment on the first gate electrode film and diffusing impurities implanted into the first gate electrode film to a region under the second gate electrode pattern, Etching the first gate electrode film using the second gate electrode pattern as a mask to form a gate electrode, and the ion implantation step includes the first gate electrode film and the underlying gate electrode film. Impurity ion implantation is performed on a semiconductor substrate, and the ion implantation step includes a step of ion implantation of impurities with two or more acceleration energies, and the ions are mainly implanted into the semiconductor substrate by high acceleration energy ion implantation. There is provided a method of manufacturing a MIS type semiconductor device in which implantation is performed and ion implantation is mainly performed on the first gate electrode film by ion implantation with low acceleration energy.
[0032]
According to another aspect of the present invention, a step of forming a gate insulating film on a surface of a semiconductor substrate, and then a first gate electrode film that can be converted into a conductor by doping impurities on the gate insulating film. Forming a second gate electrode film made of a conductor on the first gate electrode film, and then selectively etching the second gate electrode film, A first etching step of leaving a second gate electrode pattern on the first gate electrode film; and then an ion implantation step of implanting impurities into the exposed first gate electrode film using the second gate electrode pattern as a mask Next, a heat treatment step is performed for performing heat treatment on the first gate electrode film, and diffusing impurities implanted into the first gate electrode film to a region under the second gate electrode pattern, and Etching the first gate electrode film using the second gate electrode pattern as a mask to form a gate electrode, and the ion implantation step includes the first gate electrode film and the underlying layer. Impurity ion implantation is performed on the semiconductor substrate, and the ion implantation step includes a step of implanting two or more ion species having different average ranges with respect to the same acceleration energy, and an ion species having a long average range. Thus, there is provided a method for manufacturing a MIS type semiconductor device in which ion implantation is mainly performed on the semiconductor substrate and ion implantation is mainly performed on the first gate electrode film with an ion species having a short average range.
[0033]
After the second gate electrode film is formed on the first gate electrode film, only the second gate electrode film is patterned, and the second gate electrode pattern is formed on the first gate electrode film. In this state, ion implantation is performed. To do. Since the first gate electrode film under the second gate electrode pattern is protected by the second gate electrode pattern or the resist pattern on the second gate electrode pattern, ions are implanted into the underlying gate insulating film and the semiconductor substrate surface. Can be prevented. A sufficient amount of impurity ions is implanted into the first gate electrode film on both sides of the second gate electrode pattern.
[0034]
The subsequent heat treatment causes thermal diffusion from the region doped with impurities on both sides of the second gate electrode pattern to the region under the second gate electrode pattern in the first gate electrode film, and the region under the second gate electrode pattern also Can be sufficiently doped.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0036]
FIG. 1 schematically shows a method of manufacturing a semiconductor device according to an embodiment of the present invention.
As shown in FIG. 1A, a gate insulating film 2 is formed on the surface of a semiconductor substrate 1, and a semiconductor gate electrode layer 3 and an upper gate electrode layer 4 are stacked thereon. The gate insulating film 2 has a thickness of about 10 nm or less, for example. The semiconductor gate electrode layer 3 is formed of, for example, polycrystalline or amorphous silicon. The upper gate electrode layer 4 is made of silicide or metal.
[0037]
A resist pattern is formed on the upper gate electrode layer 4 and selectively etched to pattern the upper gate electrode layer 4 in the shape of the gate electrode. Etching is completed with the semiconductor gate electrode layer 3 left. The length of the gate electrode in the current direction (gate length) is 0.3 μm or less, typically 0.2 μm or less. As a method for selectively removing only the upper gate electrode layer 4 while leaving the semiconductor gate electrode layer 3, an etching stopper layer made of a thin conductor film is inserted between the semiconductor gate electrode layer 3 and the upper gate electrode layer. May be.
[0038]
In this state, impurity ions 5 are ion-implanted into the semiconductor gate electrode layer 3. Since the upper gate electrode layer 4 and the resist pattern on the gate electrode layer 4 serve as a mask for ion implantation, the semiconductor gate electrode layer 3 includes an undoped region 3b below the upper gate electrode layer 4 and doped regions 3a on both sides thereof. Divided into The resist pattern is removed by this stage after etching.
[0039]
As shown in FIG. 1B, for example, the semiconductor substrate is heated by heat 7 from a heating source 6 to activate and diffuse the impurities in the semiconductor gate electrode layer 3. Since the gate length is short and the impurity diffusion rate in the polycrystalline or amorphous semiconductor is remarkably high, the impurity diffusion from the doped region 3a to the non-doped region 3b occurs quickly, and the entire semiconductor gate electrode layer 3 is substantially uniformly doped. Doped with.
[0040]
As shown in FIG. 1C, the semiconductor gate electrode layer 3 is patterned using the upper gate electrode layer 4 as an etching mask. In this way, the gate electrode G is formed by stacking the semiconductor gate electrode layer 3 and the upper gate electrode layer 4.
[0041]
In this state, impurity ions 8 are further implanted to form impurity doped source / drain regions 9 in the semiconductor substrate 1.
[0042]
FIG. 1D schematically shows a plan view of the semiconductor substrate in a state where the ion implantation shown in FIG. 1C is performed. A gate electrode G is disposed across the active region at the center of the active region defined by the field insulating film OX, and the upper end of the gate electrode G extends over the field insulating film OX to form a contact region having an increased width. Yes. The active region on both sides of the gate electrode G is doped with impurities to form a source region S and a drain region D.
[0043]
Consider the semiconductor gate electrode layer of the gate electrode G. A portion on the active region is doped with a sufficient amount of impurities by the thermal diffusion process shown in FIG. However, in the contact region shown in the upper part of the figure, the width of the gate electrode layer is widened, so that the peripheral portion is sufficiently doped with impurities, but the central portion is not doped with sufficient impurities. May remain. This depends on the width (width) of the contact region, and cannot be generally described. However, when the heat treatment for the lateral diffusion is minimized, an NG region is formed. The impurity concentration of the non-doped region NG has a concentration of ½ or less of the impurity concentration of the semiconductor gate electrode layer on the peripheral portion and the active region. More typically, the impurity concentration in the center of the contact region is one digit or more lower than the impurity concentration in the peripheral portion.
[0044]
Although the description has been made without specifying the conductivity type of the impurity, when producing an n-channel MOS transistor, the impurity ions 5 and 8 are n-type impurities, and when producing a p-channel MOS transistor, Impurity ions 5 and 8 are p-type impurities. Or, in some cases, this may be reversed.
[0045]
In the step of FIG. 1A, the regions into which the impurity ions 5 are implanted are regions on both sides of the patterned upper gate electrode layer 4. This region is a region in which impurity ions 8 are ion-implanted into the surface of the semiconductor substrate 1 in the ion implantation of FIG. 1C, and even if some impurity ions 5 penetrate the gate insulating film 2, no problem occurs. .
[0046]
The region below the upper gate electrode layer 4 is a region on the channel region. When impurity ions enter through the gate insulating film 2, the threshold voltage (V _Th ) Will cause problems. In the process of FIG. 1A, since this region is protected by the upper gate electrode layer 4, the impurity ions 5 are not substantially implanted. There is no penetration of the implanted impurity ions.
[0047]
In FIG. 1A, the semiconductor gate electrode layer 3b on the channel region is non-doped, but in the step of FIG. 1B, impurities are diffused from both regions.
[0048]
2 and 3 are graphs for explaining how much impurity diffusion occurs in the semiconductor gate electrode layer due to thermal diffusion. The horizontal axis represents the distance x from the boundary between the doped region and the non-doped region to the non-doped region in the unit μm, and the vertical axis represents the impurity concentration in the unit cm. ^-3 It shows with. FIG. 2 shows a case where P ions are used as impurity ions, and FIG. 3 shows a case where B ions are used as impurity ions.
[0049]
In FIG. 2, 5 × 10 5 P ions are applied to a limited region of the polycrystalline silicon layer. ²⁰ cm ^-3 And then thermal diffusion. Impurity distribution after thermal diffusion is shown by each curve. The heat treatment conditions are a temperature of 750 ° C. to 900 ° C., a time of 30 minutes, and a time of 60 minutes.
[0050]
In FIG. 3, B is 1 × 10 6 in a limited region of the polycrystalline silicon layer. ^{twenty one} cm ^-3 Then, a heat treatment is performed to cause diffusion. The heat treatment conditions are a temperature of 750 ° C. to 900 ° C., a time of 30 minutes, and a time of 60 minutes.
[0051]
As shown in FIG. 1B, impurity diffusion occurs from both sides of the gate electrode. Therefore, half of the gate length may be doped by thermal diffusion from one side. That is, when the gate length is 0.3 μm, it is sufficient that 0.15 μm is doped almost uniformly by thermal diffusion.
[0052]
In the case of FIG. 2, a substantially uniform impurity distribution of about 0.15 μm is generated by heat treatment at 900 ° C. for 30 minutes. When the gate length is 0.2 μm, the diffusion distance is 0.1 μm, and the heat treatment for causing thermal diffusion can be performed at 850 ° C. for 60 minutes. Further, when the gate length is 0.1 μm, the diffusion distance is 0.05 μm, and the heat treatment for causing thermal diffusion is performed at 850 ° C. for 30 minutes. If the gate length is further shortened, sufficient thermal diffusion occurs at a lower temperature or in a shorter time.
[0053]
In the case of B doping shown in FIG. 3, the impurity concentration in the doped region is lower than in the case of FIG. 2, but the diffusion length is somewhat shorter. When the gate length is 0.3 μm, the heat treatment may be performed for about 40 minutes at 900 ° C. When the gate length is 0.2 μm, a heat treatment at 900 ° C. for 30 minutes is sufficient, and the time may be shortened to about 20 minutes.
[0054]
In the case of a CMOS semiconductor device, ion implantation corresponding to FIG. 1A is performed separately for an n-channel MOS transistor and a p-channel MOS transistor. The thermal diffusion process shown in FIG. 1B can be a process common to the n-channel MOS transistor and the p-channel MOS transistor. When the gate length is 0.3 μm, for example, heat treatment at 900 ° C. for 40 minutes may be performed. In the case of a gate length of 0.2 μm, for example, heat treatment is performed at 900 ° C. for 20 minutes.
[0055]
FIG. 1E shows a modification of the ion implantation process shown in FIGS. After patterning upper gate electrode layer 4, semiconductor gate electrode layer 3 is ion-implanted with short-range ions 5, and impurity-doped region 9 on the surface of the semiconductor substrate is ion-implanted with long-range ions 8. The ion implantation of ions having different ranges may be performed by changing the acceleration energy of the same ion species, or ions having different masses may be implanted with the same acceleration energy. For example, if As and P are ion-implanted with the same acceleration energy, the range of As is short and the range of P is long. When different types of ions are implanted, it is also possible to implant ions simultaneously in the same process.
[0056]
A method for manufacturing a CMOS type semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.
[0057]
As shown in FIG. 4A, an n-type well 12 is formed in a predetermined region of a p-type silicon substrate 11, and a field oxide layer 13 is formed on the surface. Either the well or the field oxide layer may be formed first. Further, although the case where the p-type silicon substrate 11 is exposed on the surface is shown, a p-type well is further formed in the p-type silicon substrate so that the n-type well and the p-type well are exposed on the surface. Also good.
[0058]
As shown in FIG. 4B, a gate oxide film 14 having a thickness of about 10 nm or less is grown on the surface of the active region surrounded by the field oxide layer 13 by thermal oxidation, and on the gate oxide film and the field oxide layer surface. The polycrystalline silicon layer 15 and the silicide layer 16 are stacked. An oxide film 17 is further deposited on the silicide layer 16.
[0059]
Polycrystalline silicon layer 15 has a thickness of about 50 nm, for example. The silicide layer 16 is a WSi layer having a thickness of about 150 nm, for example. The oxide film 17 is a silicon oxide film having a thickness of about 50 nm, for example. The polycrystalline silicon layer 15 and the oxide film 17 can be formed by CVD. The silicide layer 16 can be formed by sputtering, for example.
[0060]
As shown in FIG. 4C, a resist mask M1 matching the shape of the gate electrode is formed on the oxide film 17. Using the resist mask M1 as an etching mask, the underlying oxide film 17 and silicide layer 16 are etched. Etching is terminated with the surface of the polycrystalline silicon layer 15 exposed.
[0061]
As shown in FIG. 4D, a resist mask M2 covering the p-channel transistor region is formed, and P channel is formed in the n-channel MOS transistor region. ⁺ Ion implantation is performed. This ion implantation is for doping the exposed polycrystalline silicon layer 15 into n-type. The polycrystalline silicon layer 15 in the n-channel MOS transistor region is doped with P to become an n-type polycrystalline silicon layer 15n. Note that ions are not implanted into the regions under the pattern of the oxide film 17 and the silicide layer 16, and the polycrystalline silicon layer 15 is in a non-doped state. After the ion implantation, the resist mask M2 is removed.
[0062]
As shown in FIG. 5E, the n-channel MOS transistor region is covered with a resist mask M3, and the p-channel MOS transistor region is covered with B. ⁺ Ion implantation is performed. In this ion implantation, the polycrystalline silicon layer 15 in the p-channel MOS transistor region is doped with a p-type impurity to form a p-type polycrystalline silicon layer 15p. It should be noted that ions are not implanted into the region below the pattern of the oxide film 17 and the silicide layer 16 and remain undoped.
[0063]
B ⁺ The ion implantation is performed, for example, with an acceleration energy of 10 keV and a dose region of 1 × 10. ¹⁵ cm ^-2 To do. Thereafter, the resist mask M3 is removed.
[0064]
As shown in FIG. 5F, at least the surface of the semiconductor substrate is heated by heat 18 to heat-treat the polycrystalline silicon layer 15. By this heat treatment, impurities doped on both sides of the region below the silicide layer 16 are also thermally diffused. As described above, the heat treatment conditions are selected so that a sufficient amount of impurities are diffused in the region below the center of the silicide layer. For example, when the gate length is 0.15 μm, heat treatment is performed at a temperature of 800 to 850 ° C. for about 30 minutes. The diffusion rate of impurities in the polycrystalline silicon is high, and even if the polycrystalline silicon layer under the center of the silicide layer 16 is sufficiently doped with impurities, the impurities diffuse into the gate oxide film 14 therebelow. Can be prevented.
[0065]
In the regions on both sides of the silicide layer 16, impurities are already slightly doped into the gate oxide film 14 at the time of ion implantation, but the gate oxide film in this region is removed later, and further the semiconductor below it. Since the substrate is a region doped with impurities, there is no problem even if diffusion occurs.
[0066]
As shown in FIG. 5G, the polycrystalline silicon layer 15 is etched using the pattern of the oxide film 17 and the silicide layer 16 as a mask. In this manner, gate electrodes Gn and Gp each including a stacked layer of doped polycrystalline silicon layer 15 and silicide layer 16 are formed.
[0067]
As shown in FIG. 5G, low concentration n-type impurities are ion-implanted in the n-channel MOS transistor region to form n-type low concentration source / drain regions 19. Further, p-type impurity ions are implanted into the p-channel MOS transistor region to form a p-type low concentration source / drain region 20. These ion implantations are performed separately for n-type impurities and p-type impurities by forming resist masks similar to those shown in FIGS. 4D and 5E, respectively.
[0068]
Thereafter, as shown in FIG. 5H, an oxide film 21 is deposited on the entire surface of the substrate by CVD, and anisotropic etching is performed to leave the sidewall 21 only on the side wall of the gate electrode structure.
[0069]
Using the gate electrode structure, sidewalls 21 and field oxide layer 13 as a mask, high-concentration ion implantation is performed to perform high-concentration n-type source / drain regions 22 of the n-channel MOS transistor and high-concentration p-type source / drain of the p-channel MOS transistor. A drain region 23 is formed. These ion implantations are also performed by separate ion implantations using a resist mask. Thereafter, the semiconductor substrate is heat-treated to activate the ion-implanted impurities and recover crystal defects generated during the ion implantation.
[0070]
FIG. 7 schematically shows a plan view of the state of FIG. The electrode Gn of the n-channel MOS transistor and the gate electrode Gp of the p-channel MOS transistor cross the active region, form a wide portion on the field oxide film, and form a contact region. In the figure, the contact region is indicated by a broken line.
[0071]
FIG. 6I shows a state in which an insulating film 24 is further formed on the substrate surface, contact holes are opened, and electrodes 25 are formed.
[0072]
In the embodiment described above, the polycrystalline silicon layer is used as the lower gate electrode layer, but an amorphous silicon layer may be used. In addition, as the lower gate electrode layer, one that can be rendered conductive by impurity diffusion can be used.
[0073]
Although the WSi layer is used as the upper electrode layer, other silicide materials such as CoSi and TiSi, metals such as W, Ti, TiN, and WN, or composite materials or laminates of these materials can be used instead. .
[0074]
However, if silicide is used, impurities in the first gate electrode film may become a problem of escape on the silicide side depending on the heat treatment. Therefore, there is a layer serving as a barrier for impurity diffusion, for example, a thin layer of TiN or WN. A laminate having a metal layer thereon is desirable.
[0075]
Further, although the case where an oxide film is formed on the silicide of the gate electrode has been shown, this oxide film is not essential.
[0076]
According to the manufacturing method described above, the etching of the laminated gate electrode is divided into two separate steps, but the number of masks is not increased. The purely increasing process is only heat treatment performed after ion implantation into the semiconductor gate electrode layer. This heat treatment has also been necessary for impurity activation in the past, so that the number of steps is not necessarily increased.
[0077]
FIG. 8 shows another embodiment of the ion implantation process. Assume that a gate oxide film 2 and a polycrystalline silicon layer 3 are formed on a p-type silicon substrate 1, and a silicide pattern 4 is disposed thereon. Ion implantation performed in this state is performed so that the peak impurity concentration is located in the vicinity of the gate oxide film 2. The shape of the impurity concentration N1 to be ion-implanted is schematically shown on the right side in the drawing. If such ion implantation is performed, the maximum value of the impurity concentration is in the vicinity of the surface of the silicon substrate 1, an impurity doped region having a high surface concentration can be formed, and ion implantation into the polycrystalline silicon layer 3 can be performed simultaneously.
[0078]
Further, as shown on the right side in the figure, a plurality of types of ion implantation are continuously performed, and an impurity concentration distribution having a peak in the polycrystalline silicon layer 3 and an impurity concentration having a peak near the surface of the silicon substrate 1 are added. The impurity concentration N2 may be formed.
[0079]
Even if such ion implantation is performed, impurity ions can be prevented from being implanted into the underlying gate oxide film 2 if the combined thickness of the silicide pattern 4 and the polycrystalline silicon layer 3 is sufficient. . The polycrystalline silicon layer 3 may be implanted with impurity ions to some extent. However, even if impurities are implanted into the polycrystalline silicon layer 3, the concentration thereof is insufficient, so that a subsequent heat treatment for impurity diffusion is essential. Further, the steps shown in FIGS. 5G to 6I are performed to complete the semiconductor device.
[0080]
In the example, Pch. And Nch. In the case of the CMOS using the two types of transistors of Pch. Nch. Each of these may be used alone, and of course applicable to the case of PMOS and NMOS.
[0081]
In the example, Pch. P-type gate, Nch. Although the N-type gate is used for the circuit, there is a case where the reverse combination is more advantageous depending on circuit demands. In this case, the reverse combination may be used.
[0082]
The method of introducing impurities into the polysilicon region immediately below the gate by diffusion from the lateral direction used this time becomes easier to implement because the shorter the gate length, the lower the temperature and the shorter the heat treatment. When the gate length is long, it may be possible by shortening the gate even if heat treatment is too much impossible due to the overall balance.
[0083]
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0084]
【The invention's effect】
As described above, according to the present invention, even if the height of the gate electrode is lowered and ion implantation is performed on the gate electrode, it is possible to prevent the penetration of impurity ions penetrating the gate insulating film.
[Brief description of the drawings]
1A and 1B are a cross-sectional view and a plan view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a graph showing diffusion of P in polycrystalline silicon.
FIG. 3 is a graph showing thermal diffusion of B in polycrystalline silicon.
FIG. 4 is a cross-sectional view for explaining a method of manufacturing a CMOS type semiconductor device according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view for explaining a method of manufacturing a CMOS type semiconductor device according to an embodiment of the present invention.
FIG. 6 is a cross-sectional view for explaining a method of manufacturing a CMOS type semiconductor device according to an embodiment of the present invention.
7 is a plan view of the structure shown in FIG.
FIG. 8 is a schematic view for explaining another embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining a conventional method for manufacturing a MOS type semiconductor device.
[Explanation of symbols]
1 Semiconductor substrate
2 Gate insulation film
3 Semiconductor gate electrode layer
4 Upper gate electrode layer
5, 8 Impurity ions
6 Heating source
7 fever
9 Source / drain (impurity doped region)
11 p-type silicon substrate
12 n-type well
13 Field oxide layer
14 Gate oxide film
15 Polycrystalline silicon layer
16 Silicide layer
17 Oxide film
M (M1, M2, M3) resist mask
18 Heat
19, 20 Lightly doped region
22, 23 Highly doped region
24 Insulating layer
25 electrodes

Claims (2)

Forming a gate insulating film on the surface of the semiconductor substrate;
Next, forming a first gate electrode film that can be made into a conductor by doping impurities on the gate insulating film;
Next, forming a second gate electrode film made of a conductor on the first gate electrode film;
A first etching step of selectively etching the second gate electrode film to leave a second gate electrode pattern on the first gate electrode film;
Next, an ion implantation step of implanting impurities into the exposed first gate electrode film using the second gate electrode pattern as a mask;
Next, a heat treatment process for performing heat treatment on the first gate electrode film and diffusing impurities implanted into the first gate electrode film to a region under the second gate electrode pattern;
A second etching step of etching the first gate electrode film using the second gate electrode pattern as a mask to form a gate electrode;
Including
The ion implantation step performs ion implantation of impurities into the first gate electrode film and the semiconductor substrate thereunder, and
The ion implantation step includes a step of ion-implanting impurities with two or more acceleration energies. The ion implantation is mainly performed with high acceleration energy ion implantation, and mainly with low acceleration energy ion implantation. And a method of manufacturing a MIS type semiconductor device in which ions are implanted into the first gate electrode film. Forming a gate insulating film on the surface of the semiconductor substrate;
Next, forming a first gate electrode film that can be made into a conductor by doping impurities on the gate insulating film;
Next, forming a second gate electrode film made of a conductor on the first gate electrode film;
A first etching step of selectively etching the second gate electrode film to leave a second gate electrode pattern on the first gate electrode film;
Next, an ion implantation step of implanting impurities into the exposed first gate electrode film using the second gate electrode pattern as a mask;
Next, a heat treatment process for performing heat treatment on the first gate electrode film and diffusing impurities implanted into the first gate electrode film to a region under the second gate electrode pattern;
A second etching step of etching the first gate electrode film using the second gate electrode pattern as a mask to form a gate electrode;
Including
The ion implantation step performs ion implantation of impurities into the first gate electrode film and the semiconductor substrate thereunder, and
The ion implantation step includes a step of implanting two or more ion species having different average ranges with respect to the same acceleration energy, and performing ion implantation mainly on the semiconductor substrate with ion species having a long average range, A method for manufacturing a MIS type semiconductor device, wherein ion implantation is performed mainly on the first gate electrode film with ion species having a short average range.

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