JP2016004952A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can reduce 1/f noise even when a gate insulation film of a transistor is thin.SOLUTION: A semiconductor device manufacturing method comprises: a step S30 of forming a second gate insulation film with a film thickness of equal to or less than 6.5 nm on a silicon substrate; a step S40 of depositing a non-doped polysilicon film on the second gate insulation film; a step S50 of performing first annealing at 965°C and over on the silicon substrate after depositing the non-doped polysilicon film; a step S60 of injecting an impurity into the non-doped polysilicon film after performing the first annealing to make the non-doped polysilicon film be a gate electrode film; and a step S70 of performing patterning on the gate electrode film to form a second electrode on the second gate insulation film and performing second annealing for diffusing the impurity in the gate electrode film or in the gate electrode.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which 1 / f noise can be reduced even when a gate insulating film of a transistor is thin.

  In a MOSFET formed on a silicon substrate, the state of the gate oxide film / silicon substrate interface is an important factor affecting the 1 / f noise characteristics of the MOSFET. If carrier traps exist at the gate oxide film / silicon substrate interface, carriers are trapped and released by them, and 1 / f noise increases. In order to reduce 1 / f noise, it is required to form a gate oxide film / silicon substrate interface with as few carrier traps as possible.

A typical carrier trap is an interface state. The interface level is a level generated in the forbidden band on the surface of the semiconductor, and is generated due to dangling bonds (ie, dangling bonds) of crystal atoms. In order to suppress the generation of this interface state, in Patent Document 1, high-temperature annealing is performed immediately after the gate oxide film is formed (that is, after the gate oxide film is formed and before the gate electrode film is formed). Thus, a method is described in which the unbonded Si—O bond at the gate oxide film / silicon substrate interface is changed to SiO ₂ bond to obtain good interface characteristics.

Japanese Patent Publication No. 7-70535

Incidentally, in the case of a manufacturing method in which high-temperature annealing is performed immediately after formation of a gate oxide film, which is a manufacturing method described in Patent Document 1, the effect of reducing 1 / f noise depends on the gate oxide film thickness. They found out.
FIG. 9 shows the results of experiments conducted by the present inventors.
FIG. 9 shows the results of investigating the relationship between the temperature of annealing performed immediately after formation of the gate oxide film and the 1 / f noise for the PMOSFET having a gate oxide film thickness of 3 nm and the PMOSFET having a gate oxide film thickness of 12 nm. Shown in The horizontal axis in FIG. 9 indicates the annealing temperature [° C.], and the vertical axis indicates the 1 / f noise coefficient ratio [%].

In this experiment, | Vg | (gate potential) = | Vd | (drain potential) = | Vth | (threshold voltage) +0.4 V, Vs (source potential) = Vsub (substrate potential) = 0 V, A voltage was applied to each PMOSFET. 1 / f noise is expressed as shown in Equation (1).
S _vg = K _f / (C _ox * W * L * f) (1)
In equation (1), S _vg represents voltage conversion noise, K _f represents 1 / f noise coefficient, C _ox represents gate oxide film capacitance, W represents gate width, L represents gate length, and f represents frequency. Noise factor K _f is dependent on the process conditions. Therefore, K compared to the _f value to calculate the 1 / f noise coefficient ratio [%], calculated 1 / f noise between the coefficient ratio each PMOSFET and annealing time without annealing K _f values for each annealing temperature 1 / f noise was evaluated by comparing between temperatures.

As shown in FIG. 9, in a MOSFET with a gate oxide film thickness of 12 nm, which is an example of a thick film, the 1 / f noise coefficient ratio decreases when the annealing temperature immediately after formation of the gate oxide film is increased.
However, it was found that in a MOSFET having a gate oxide film thickness of 3 nm, which is an example having a film thickness of 6.5 nm or less, the noise coefficient ratio increases when the annealing temperature immediately after the formation of the gate oxide film is increased.
This is because the 1 / f noise is improved by increasing the annealing temperature when the gate oxide film thickness is 12 nm, but conversely by increasing the annealing temperature when the gate oxide film thickness is 3 nm, the 1 / f noise is improved. f means increasing noise.
In addition, the present inventors mention to suppress depletion of the gate electrode as another problem for reducing the 1 / f noise of the MOSFET.

FIG. 10 shows the result of an experiment conducted by the present inventors, and shows the result of investigating the relationship between the depletion of the gate electrode and the 1 / f noise coefficient ratio during MOSFET operation.
The horizontal axis of FIG. 10 is the gate oxide capacity ratio (ratio of the gate oxide capacity in the accumulation state to the inverted gate oxide capacity) [%] representing the depletion of the gate electrode, and the vertical axis is the 1 / f noise coefficient. The ratio [%] is shown.
This experimental result means that the increase in depletion of the gate electrode is a factor that increases 1 / f noise. The depletion of the gate electrode appears as the gate oxide film thickness becomes thinner (that is, the thinner the film), so suppressing the depletion of the gate electrode reduces the 1 / f noise of the thin film gate oxide MOSFET. It will be an important issue.
Accordingly, the present invention has been made in view of the above problems found by the present inventors, and is a method for manufacturing a semiconductor device that can reduce 1 / f noise even when the gate insulating film thickness of a transistor is thin. The purpose is to provide a method.

  That is, in the method for manufacturing a semiconductor device according to one embodiment of the present invention, a step of forming a gate insulating film having a thickness of 6.5 nm or less on a substrate and a step of depositing a non-doped polysilicon film on the gate insulating film. And, after depositing the non-doped polysilicon film, subjecting the substrate to a first annealing at 965 ° C. or higher, and after the first annealing, implanting impurities into the non-doped polysilicon film and A step of using a non-doped polysilicon film as a gate electrode film; a step of patterning the gate electrode film to form a gate electrode on the gate insulating film; and the impurity in the gate electrode film or in the gate electrode And performing a second annealing for diffusing.

In the method for manufacturing a semiconductor device, the first annealing may be performed in a non-doped state in which no impurity is implanted into the non-doped polysilicon film.
In the method for manufacturing a semiconductor device described above, it is not necessary to apply heat of 965 ° C. or higher to the substrate after the gate insulating film is formed and before the non-doped polysilicon film is deposited.

In the method for manufacturing a semiconductor device, in the step of depositing the non-doped polysilicon film, a non-doped polysilicon film having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ or less may be deposited.
In the semiconductor device manufacturing method, in the step of performing the second annealing, the impurity contained in the gate electrode film or the gate electrode may be uniformly diffused in a depth direction toward the substrate. Good.

In the method for manufacturing a semiconductor device, the processing temperature of the second annealing may be lower than the processing temperature of the first annealing.
In the method for manufacturing a semiconductor device, the first annealing treatment temperature is in the range of 965 ° C. to 1125 ° C., and the first annealing treatment time is in the range of 15 seconds to 60 seconds. Also good.
In the method for manufacturing a semiconductor device, the first annealing treatment atmosphere may be nitrogen gas or a mixed gas containing nitrogen and oxygen.

  According to one embodiment of the present invention, 1 / f noise can be reduced even when a gate insulating film of a transistor is thin.

The figure which shows the main processes of the manufacturing method of the semiconductor device 100 which concerns on embodiment. FIG. 6 is a diagram showing a method for manufacturing the semiconductor device 100 in the order of steps. FIG. 6 is a diagram showing a method for manufacturing the semiconductor device 100 in the order of steps. FIG. 6 is a diagram showing a method for manufacturing the semiconductor device 100 in the order of steps. The figure which shows the result of the experiment which the present inventors conducted. The figure which shows the result of the experiment which the present inventors conducted. The figure which shows the result of the experiment which the present inventors conducted. The figure which shows the result of the experiment which the present inventors conducted. The figure for demonstrating a subject, which is the result of the experiment which the present inventors conducted. The figure for demonstrating a subject, which is the result of the experiment which the present inventors conducted.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and repeated description thereof is omitted.
The present inventors believe that the cause (mechanism) that the 1 / f noise of the thin-film gate oxide MOSFET cannot be reduced by the method of Patent Document 1 is the gate oxide film thickness and the gas atmosphere during annealing.
More specifically, when annealing is performed immediately after the formation of the gate oxide film, the annealing is generally performed in a nitrogen atmosphere in consideration of an increase in the gate oxide film thickness.

However, when the gate oxide film is thin, nitrogen, which is the atmosphere during annealing, enters the gate oxide film, diffuses in the gate oxide film, and reaches the gate oxide film / silicon substrate interface. As a result, the interface state of the gate oxide film / silicon substrate is increased, and 1 / f noise is increased. For this reason, as shown in FIG. 9, when the gate oxide film thickness is 3 nm, the 1 / f noise cannot be reduced unlike the case of 12 nm.
Based on such considerations, the present inventors considered that it is sufficient to perform high-temperature annealing after depositing a non-doped polysilicon film to be a gate electrode film, not immediately after forming the gate oxide film.

In addition, in order to suppress the depletion of the gate electrode, which is another problem, a high concentration impurity is implanted into the polysilicon to be the gate electrode and further diffused uniformly in the polysilicon. Good.
However, the implantation of the high concentration impurity needs to be performed before patterning the polysilicon film to be the gate electrode. This is because if high-concentration impurities are implanted after patterning the gate electrode, impurities are also implanted into the source / drain regions, and considering the influence of the short channel effect, This is because the impurity cannot be sufficiently diffused.

  Furthermore, in order to achieve both high temperature annealing after deposition of the polysilicon film to be the gate electrode film and suppression of depletion of the gate electrode film, it is necessary to perform the high temperature annealing before injecting impurities into the gate electrode. The reason is that if high-temperature annealing is performed after implanting high-concentration impurities, impurities will ooze out from the gate electrode to the substrate, causing adverse effects such as changing the threshold voltage (Vth) of the MOSFET. It is because it ends. Based on such considerations, the present inventors conducted a high-temperature annealing after depositing a non-doped polysilicon film to be a gate electrode film, and a method for manufacturing a semiconductor device that effectively suppresses depletion of the gate electrode. suggest.

(Production method)
FIG. 1 is a diagram showing main steps of a method for manufacturing a semiconductor device 100 according to an embodiment of the present invention. As shown in FIG. 1, in the method of manufacturing the semiconductor device 100, a step of preparing a wafer (step S10), a step of forming an element isolation film / injecting an impurity (step S20), and a gate oxide film are formed. Step (step S30), step of forming a non-doped polysilicon film to be the gate electrode film 13 (step S40), step of performing high temperature annealing (step S50), and into the gate electrode film 13 which is a non-doped polysilicon film A step of injecting a high concentration impurity (step 60), a step of patterning / diffusing the gate electrode film 13 (step S70), and a step of completing a transistor by a normal CMOS process (step S80). . Hereinafter, each step will be described more specifically.

2 to 4 are cross-sectional views showing the method of manufacturing the semiconductor device 100 in the order of steps.
As shown in FIG. 2A, as an example of a wafer, a silicon substrate 1 made of, for example, single crystal silicon is prepared (step S10). The surface of the silicon substrate 1 may be a silicon epitaxial layer (not shown) obtained by epitaxially growing single crystal silicon.

  Next, a field oxide film 3 is formed on the surface of the silicon substrate 1, and the regions where MOSFETs are formed and regions where other elements are formed are electrically isolated (step S20). The field oxide film 3 may be of any form as long as it is formed as an element isolation layer, and may be, for example, LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation). In the present embodiment, for example, STI is illustrated. By this field oxide film 3, for example, a region where a gate oxide film forms a thick MOSFET (hereinafter referred to as a first MOS region) and a region where a gate oxide film forms a thin MOSFET (hereinafter referred to as a second MOS region). ) Are separated from each other.

  Next, an impurity for forming a well (WELL) layer (not shown) or adjusting the threshold value of the MOSFET is ion-implanted in each of the first MOS region and the second MOS region of the silicon substrate 1 (step S20). Here, the impurity is, for example, a donor element such as phosphorus (P) or an acceptor element such as boron (B). Depending on the purpose, donor elements or acceptor elements are selected.

Next, as shown in FIG. 2B, the surface of the silicon substrate 1 is thermally oxidized to form a first gate oxide film 5 in each of the first MOS region and the second MOS region. The film thickness of the first gate oxide film 5 is, for example, about 12 nm.
Next, as shown in FIG. 2C, the first gate oxide film 5 is removed from the second MOS region to expose the surface of the silicon substrate 1. The partial removal of the first gate oxide film 5 is performed by wet etching using a resist pattern as a mask.

  More specifically, first, a low-pressure CVD oxide film 7 is deposited on the entire upper portion of the silicon substrate 1. The film thickness after deposition of the low-pressure CVD oxide film 7 is, for example, about 10 nm. Next, a resist pattern 9 having a shape that opens above the second MOS region and covers the top of the first MOS region is formed on the low-pressure CVD oxide film 7. Then, using this resist pattern 9 as a mask, low-pressure CVD oxide film 7 and first gate oxide film 5 are removed by etching. This etching is, for example, wet etching using hydrofluoric acid (HF). As a result, the low-pressure CVD oxide film 7 and the first gate oxide film 5 are removed from the second MOS region to expose the surface of the second MOS region. Thereafter, the resist pattern 9 is removed by ashing, for example.

Next, wet etching is performed on the entire surface of the silicon substrate 1 to remove the low-pressure CVD oxide film 7 from the first MOS region. In this wet etching process, the processing conditions (eg, hydrofluoric acid concentration in the etchant, etching processing time, etc.) are adjusted so that the first gate oxide film 5 formed in the first MOS region is not etched as much as possible. To do.
Next, as shown in FIG. 3A, the surface of the silicon substrate 1 is thermally oxidized to form a second gate oxide film 11 in the second MOS region (step S30). The film thickness of the second gate oxide film 11 is 6.5 nm or less, for example, about 3 nm.
Next, as shown in FIG. 3B, the gate electrode film 13 is deposited over the entire upper portion of the silicon substrate 1 (step S40). The film thickness of the gate electrode film 13 is, for example, about 250 nm.

When a polysilicon film is deposited as the gate electrode film 13, the polysilicon film has a donor element and an acceptor element concentration of not more than a detection limit value (for example, each impurity concentration is not more than 1 × 10 ¹⁶ cm ⁻³ . It is essential that the non-doped polysilicon film be zero. The reason is that when an acceptor element or the like is present in the gate electrode film 13 which is a polysilicon film, the first and second gate oxide films 5 are formed from the gate electrode film 13 by performing high-temperature annealing in the next step. This is because the acceptor element or the like oozes out to the silicon substrate 11 or the silicon substrate 1 and may adversely affect the threshold voltage (Vth) of the MOSFET. That is, the “non-doped polysilicon film” in this embodiment is a silicon film that is not deposited together with impurities for doping when the film is deposited, or in which no impurities are implanted into the non-doped polysilicon film. That's it.

Next, immediately after depositing the non-doped polysilicon film to be the gate electrode film 13, high temperature annealing is performed on the silicon substrate 1 by, for example, RTA (Rapid Thermal Anneal) method (step S50). In other words, the high temperature annealing is performed in a non-doped state in which no impurity is implanted into the non-doped polysilicon film. The high temperature annealing is performed in a mixed gas atmosphere containing, for example, nitrogen (N ₂ ) and oxygen (O ₂ ). As shown in the experimental results described later, in this step, 1 / f noise can be effectively reduced by setting the annealing temperature to 965 ° C. or more and the annealing time to 15 seconds or more.

Although the annealing temperature is high and the 1 / f noise can be further reduced by lengthening the annealing time, if these values are increased without limit, demerits (for example, transistor characteristics vary greatly, The grain size of the polysilicon increases, the load on the processing apparatus increases, the throughput decreases, and the like). Therefore, in order to reduce 1 / f noise while suppressing demerits, it is necessary to set an upper limit value for the annealing temperature and the annealing time, respectively. From the experimental results described later, it is preferable that the annealing temperature in step S50 has an upper limit of 1125 ° C. and the annealing time has an upper limit of 60 seconds. Further, the annealing in step S50 may be performed in an N ₂ gas atmosphere, for example, in addition to the mixed gas atmosphere containing N ₂ and O ₂ .

Next, as shown in FIG. 3C, an impurity for imparting conductivity to the gate electrode film 13 which is a non-doped polysilicon film is ion-implanted (step S60). Here, the impurity is, for example, a donor element such as phosphorus (P) or an acceptor element such as boron (B). Depending on the purpose, donor elements or acceptor elements are selected. Impurity implantation is performed immediately after the annealing (high temperature annealing) in step S50, so that impurities do not leak from the gate electrode film 13 to the silicon substrate 1 side, and the 1 / f noise of the MOS is adversely affected. It is possible to suppress the depletion of the gate electrode.
Note that the 1 / f noise can be reduced as the concentration of the impurity implanted into the gate electrode film 13 approaches the solid solution limit concentration of the impurity in silicon. Therefore, a donor element or an acceptor element is implanted into the gate electrode film 13 by ion implantation with a dose amount of 4 × 10 ¹⁴ cm ⁻² or more according to the purpose.

Next, as shown in FIG. 4A, the gate electrode film 13 is patterned to form the first gate electrode 15 on the first gate oxide film 5 in the first MOS region, and at the same time, the second A second gate electrode 17 is formed on the second gate oxide film 11 in the MOS region (step S70).
Next, immediately after patterning the gate electrode film 13 to form each gate electrode, annealing is performed to activate the impurities contained in each gate electrode (step S70). The annealing process in this step is performed at a temperature necessary for activation without causing an acceptor element or the like in each gate electrode to exude to the silicon substrate 1 side. For example, it is performed at 850 ° C. for 40 minutes in a mixed gas atmosphere containing nitrogen (N ₂ ) and oxygen (O ₂ ). That is, the annealing in step S70 is performed at a lower temperature than the annealing in step S50.
This step may be performed before patterning the gate electrode film 13 to form each gate electrode.

  Thereafter, using a general semiconductor manufacturing process, the MOSFET is completed through a sidewall forming process, a source / drain forming process, an interlayer insulating film forming process, a wiring forming process, and the like (step S80). For example, as shown in FIG. 4B, a side wall 19 made of an insulating layer is formed on the side surface of the first gate electrode 15 and a side wall 21 made of an insulating layer is formed on the side surface of the second gate electrode 17. To do. Further, by performing ion implantation of impurities twice before and after the step of forming the sidewalls 19 and 21, the source / drain 23 having the LDD structure is formed in the first MOS region and the LDD is formed in the second MOS region. A source / drain 25 of the structure is formed. Thereafter, as shown in FIG. 4C, silicides 31 are formed on the upper surfaces of the first and second gate electrodes 15 and 17 and the surfaces of the source / drains 23 and 25, respectively. Thereafter, an interlayer insulating film, wiring and the like (not shown) are formed.

Through these steps, the first MOSFET 110 having the thick first gate oxide film 5 in the first MOS region is completed, and the thin second gate oxide film 11 is formed in the second MOS region. The second MOSFET 120 is completed.
In this embodiment, the silicon substrate 1 corresponds to the “substrate” of the present invention, the second gate oxide film 11 corresponds to the “gate insulating film” of the present invention, and the second gate electrode 17 corresponds to the “substrate” of the present invention. It corresponds to the “gate electrode”. Further, the annealing in step S50 (high temperature annealing) corresponds to the “first annealing” of the present invention, and the annealing in step S70 corresponds to the “second annealing” of the present invention.

(Effect of embodiment)
According to the embodiment of the present invention, nitrogen that adversely affects the interface state of the gate insulating film / substrate interface can be suppressed from being injected into the gate insulating film, and impurities in the gate electrode can enter the silicon substrate side. There is no seepage, and depletion of the gate electrode during MOSFET operation can be suppressed. Therefore, even when the gate insulating film is thin, 1 / f noise can be reduced.

(1) High-temperature annealing (step S50) is performed after forming the gate electrode film 13 and before patterning the gate electrode film 13. Since the first and second gate oxide films 5 and 11 are covered with the gate electrode film 13 during the high temperature annealing, nitrogen that adversely affects the interface state of the gate oxide film / silicon substrate interface is the first and second. Implantation into the gate oxide films 5 and 11 can be suppressed.
This makes it possible to select an annealing temperature and annealing time that have a 1 / f noise reduction effect without depending on the gate oxide film thickness. For example, even when the gate oxide film of the MOSFET is thin like the second gate oxide film 11 having a thickness of 3 nm, 1 / f noise can be sufficiently reduced by high-temperature annealing.

(2) Further, an annealing process is performed between the step of forming the first and second gate oxide films 5 and 11 (step S30) and the step of forming the gate electrode film 13 which is a non-doped polysilicon film (step S40). Do not do. This prevents nitrogen or the like from being implanted into the first and second gate oxide films 5 and 11 before the first and second gate oxide films 5 and 11 are covered with the gate electrode film 13. Can do.

(3) A non-doped polysilicon film is deposited as the gate electrode film 13. The doping of the non-doped polysilicon film with impurities (that is, a donor element or an acceptor element) is performed immediately after the high-temperature annealing in step S50. This prevents impurities doped in the non-doped polysilicon film from being diffused into the first and second gate oxide films 5 and 11 and the silicon substrate 1 by high-temperature annealing, and the first and second gates. An impurity amount necessary for suppressing depletion of the electrodes 15 and 17 can be implanted.

(4) Moreover, it is preferable that the high temperature annealing treatment temperature is in the range of 965 ° C. or more and 1125 ° C. or less, and the high temperature annealing treatment time is in the range of 15 seconds or more and 60 seconds or less. As shown in the experimental results to be described later, by setting the processing temperature and processing time of the high-temperature annealing within the above ranges, the demerits (for example, the transistor characteristics vary greatly even in the MOSFET 120 having a gate oxide film thickness of 6.5 nm or less. 1 / f noise can be efficiently reduced while suppressing the increase in the grain size of the polysilicon, the load on the processing apparatus, and the decrease in throughput.
(5) Moreover, it is preferable to perform the high temperature annealing of step S50 in nitrogen gas atmosphere or mixed gas atmosphere containing nitrogen and oxygen. As a result, the gate electrode film 13 made of a non-doped polysilicon film can be prevented from being etched (ie, thermally etched) during high temperature annealing.

(6) Further, the annealing in step S70 is performed at 920 ° C. or lower after the impurity is implanted into the gate electrode film 13 or after the gate electrode film 13 is patterned and the first and second gate electrodes 15 and 17 are formed. . As a result, the impurities contained in the first and second gate electrodes 15 and 17 do not diffuse into the first and second gate oxide films 5 and 11 and the silicon substrate 1, and the first and second polysilicon are formed. It becomes possible to diffuse uniformly in the depth direction in the two gate electrodes 15 and 17, and depletion of the first and second gate electrodes 15 and 17 can be suppressed.
(Other)
The present invention is not limited to the embodiment described above. Based on the knowledge of those skilled in the art, design changes and the like can be made to each embodiment, and an aspect in which such changes and the like are added is also included in the scope of the present invention.

Next, the experiment conducted by the present inventors and the result will be described. In Experiments 1 to 4 described below, the experiment was performed under the conditions of | Vg | = | Vd | = | Vth | +0.4 V and Vs = Vsub = 0 V, as in the case of FIG. 9 described above. Further, by the K _f value for each annealing temperature as compared to the K _f value when no annealing calculates 1 / f noise coefficient ratio, it compares the calculated 1 / f noise coefficient ratio, 1 / f noise Evaluated.

(Experiment 1)
FIG. 5 shows the results of Experiment 1 conducted by the present inventors. Regarding the PMOSFET having a gate oxide film thickness of 3 nm, the relationship between the annealing temperature and noise when annealing is performed immediately after the formation of the gate oxide film, and FIG. 5 is a diagram showing the results of examining the relationship between the annealing temperature and 1 / f noise when annealing is performed immediately after formation of the gate electrode film (corresponding to the MOSFET 120 of this embodiment). The horizontal axis in FIG. 5 indicates the annealing temperature [° C.], and the vertical axis indicates the 1 / f noise coefficient ratio [%].

  As shown in FIG. 5, when annealing is performed immediately after the formation of the gate oxide film, the noise coefficient ratio increases from around 1025 to 1050 ° C. when the annealing temperature is raised. On the other hand, when annealing was performed immediately after the formation of the gate electrode film, not immediately after the formation of the gate oxide film, it was found that the noise coefficient ratio decreased when the annealing temperature was raised. In particular, it has been found that when the annealing temperature is 965 ° C. or higher, the difference in the noise coefficient ratio between the two data increases. From this result, it was found that when the gate oxide film thickness is 3 nm and annealing is performed immediately after the formation of the gate electrode film, the annealing temperature is preferably 965 ° C. or higher.

(Experiment 2)
FIG. 6 shows the result of Experiment 2 conducted by the present inventors. The processing time when annealing is performed immediately after the formation of the gate electrode film for the PMOSFET having a gate oxide film thickness of 3 nm (that is, the annealing time) is shown in FIG. It is a figure which shows the result of having investigated the relationship with 1 / f noise. The horizontal axis of FIG. 6 shows annealing time [s], and the vertical axis shows 1 / f noise coefficient ratio [%]. The annealing temperature was set to 1100 ° C.
As shown in FIG. 6, it was found that the longer the annealing time, the lower the noise coefficient ratio. In addition, the degree of reduction in the noise coefficient ratio is particularly large in the range of 0 to 15 seconds. From this result, when the gate oxide film thickness is 3 nm and annealing is performed immediately after the formation of the gate electrode film, the annealing time is 15 seconds. It turned out that it is preferable to set it above.

(Experiment 3)
FIG. 7 shows the result of Experiment 3 conducted by the present inventors, and the relationship between annealing temperature and noise when annealing is performed immediately after formation of a gate oxide film for a PMOSFET having a gate oxide film thickness of 6.5 nm. FIG. 5 is a diagram showing the results of investigating the relationship between annealing temperature and 1 / f noise when annealing is performed immediately after formation of a gate electrode film. In FIG. 7, the horizontal axis indicates the annealing temperature [° C.], and the vertical axis indicates the 1 / f noise coefficient ratio [%].

  As shown in FIG. 7, when annealing was performed immediately after the formation of the gate oxide film, the noise coefficient ratio did not change even when the annealing temperature was raised. On the other hand, when annealing was performed immediately after the formation of the gate electrode film, it was found that the noise coefficient ratio decreased when the annealing temperature was raised. In particular, it has been found that when the annealing temperature is 965 ° C. or higher, the difference in the noise coefficient ratio between the two data increases. From this result, it was found that when the gate oxide film thickness is 6.5 nm and annealing is performed immediately after the formation of the gate electrode film, the annealing temperature is preferably 965 ° C. or higher.

(Experiment 4)
FIG. 8 shows the result of Experiment 4 conducted by the present inventors. Regarding the PMOSFET having a gate oxide film thickness of 12 nm, the relationship between the annealing temperature and noise when annealing is performed immediately after the formation of the gate oxide film, and FIG. 10 is a diagram showing the results of examining the relationship between the annealing temperature and 1 / f noise when annealing is performed immediately after formation of the gate electrode film (corresponding to the MOSFET 110 of this embodiment). The horizontal axis in FIG. 8 indicates the annealing temperature [° C.], and the vertical axis indicates the 1 / f noise coefficient ratio [%].

  As shown in FIG. 8, when annealing is performed immediately after the formation of the gate oxide film and when annealing is performed immediately after the formation of the gate electrode film, the noise coefficient ratio is reduced when the annealing temperature is increased. I understood that. As described above, from the results of Experiments 2 to 4, in a MOSFET having a gate oxide film thickness of 6.5 nm or less, a 1 / f noise reduction effect is sufficiently obtained by performing high-temperature annealing at 965 ° C. or more immediately after the formation of the gate electrode film. I found out I could get it.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 Field oxide film 5 First gate oxide film 7 Low-pressure CVD oxide film 9 Resist pattern 11 Second gate oxide film 13 Gate electrode film 15 First gate electrode 17 Second gate electrodes 19 and 21 Side wall 23, 25 Source / drain 31 Silicide 100 Semiconductor device 110 First MOSFET
120 second MOSFET

Claims (8)

Forming a gate insulating film having a film thickness of 6.5 nm or less on the substrate;
Depositing a non-doped polysilicon film on the gate insulating film;
After depositing the non-doped polysilicon film, subjecting the substrate to a first annealing at 965 ° C. or higher;
After performing the first annealing, implanting impurities into the non-doped polysilicon film to make the non-doped polysilicon film a gate electrode film;
Patterning the gate electrode film to form a gate electrode on the gate insulating film;
Performing a second annealing for diffusing the impurities in the gate electrode film or in the gate electrode.   The method of manufacturing a semiconductor device according to claim 1, wherein the first annealing is performed in a non-doped state in which no impurity is implanted into the non-doped polysilicon film.   3. The method of manufacturing a semiconductor device according to claim 1, wherein after the gate insulating film is formed and before the non-doped polysilicon film is deposited, heat of 965 ° C. or higher is not applied to the substrate. . 4. The semiconductor according to claim 1, wherein in the step of depositing the non-doped polysilicon film, a non-doped polysilicon film having an impurity concentration in the film of 1 × 10 ¹⁶ cm ⁻³ or less is deposited. Device manufacturing method.   5. The method according to claim 1, wherein in the second annealing step, the impurities contained in the gate electrode film or the gate electrode are uniformly diffused in a depth direction toward the substrate. The manufacturing method of the semiconductor device of description.   6. The method of manufacturing a semiconductor device according to claim 1, wherein a processing temperature of the second annealing is lower than a processing temperature of the first annealing. The treatment temperature of the first annealing is in the range of 965 ° C. or more and 1125 ° C. or less,
7. The method of manufacturing a semiconductor device according to claim 1, wherein a processing time of the first annealing is in a range of 15 seconds to 60 seconds.   8. The method of manufacturing a semiconductor device according to claim 1, wherein a processing atmosphere of the first annealing is nitrogen gas or a mixed gas containing nitrogen and oxygen.

Images