JP2014140025A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can reduce 1/f noise even when a gate insulation film of a transistor is thin.SOLUTION: A semiconductor device manufacturing method comprises: a process of forming a second gate oxide film 11 having a film thickness of 6.5 nm and under on a silicon substrate 1; a process of depositing a gate electrode film 13 on the second gate oxide film 11; a process of performing high-temperature annealing at 965°C and over on the silicon substrate 1 after depositing the gate electrode film 13; and a process of patterning the gate electrode film 13 after performing the high-temperature annealing on the silicon substrate 1 to form a second gate electrode 17 composed of the gate electrode film 13 on the second gate oxide film 11.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which 1 / f noise can be reduced even when a gate insulating film of a transistor is thin.

  In a MOSFET formed on a silicon substrate, the state of the gate oxide film / silicon substrate interface is an important factor affecting the 1 / f noise characteristics of the MOSFET. If carrier traps exist at the gate oxide film / silicon substrate interface, carriers are trapped and released by them, and 1 / f noise increases. In order to reduce 1 / f noise, it is required to form a gate oxide film / silicon substrate interface with as few carrier traps as possible.

A typical carrier trap is an interface state. The interface level is a level generated in the forbidden band on the surface of the semiconductor, and is generated due to dangling bonds (ie, dangling bonds) of crystal atoms. In order to suppress the generation of this interface state, in Patent Document 1, high-temperature annealing is performed immediately after the gate oxide film is formed (that is, after the gate oxide film is formed and before the gate electrode film is formed). Thus, a method is described in which the unbonded Si—O bond at the gate oxide film / silicon substrate interface is changed to SiO ₂ bond to obtain good interface characteristics.

Japanese Patent Publication No. 7-70535

By the way, as described in Patent Document 1, the present inventor indicates that when high-temperature annealing is performed immediately after the formation of the gate oxide film, the 1 / f noise reduction effect depends on the gate oxide film thickness. I found it.
FIG. 9 shows the results of an experiment conducted by the present inventor. The temperature of annealing performed immediately after formation of the gate oxide film for a PMOSFET having a gate oxide film thickness of 3 nm and a PMOSFET having a gate oxide film thickness of 12 nm is shown in FIG. FIG. 5 is a diagram illustrating a result of investigating a relationship with 1 / f noise. The horizontal axis in FIG. 9 indicates the annealing temperature [° C.], and the vertical axis indicates the 1 / f noise coefficient ratio [%].
In this experiment, voltage is applied to each PMOSFET under the conditions of Vg (gate potential) = Vd (drain potential) = Vth (threshold voltage) −0.4 V and Vs (source potential) = Vsub (substrate potential) = 0 V. Applied. 1 / f noise is expressed as shown in Equation (1).

S _vg = K _f / (C _ox * W * L * f) (1)
In equation (1), S _vg represents voltage conversion noise, K _f represents 1 / f noise coefficient, C _ox represents gate oxide film capacitance, W represents gate width, L represents gate length, and f represents frequency. Noise factor K _f is dependent on the process conditions. Therefore, K compared to the _f value to calculate the 1 / f noise coefficient ratio [%], calculated 1 / f noise between the coefficient ratio each PMOSFET and annealing time without annealing K _f values for each annealing temperature 1 / f noise was evaluated by comparing between temperatures.

  As shown in FIG. 9, in a MOSFET having a gate oxide film thickness of 12 nm, the 1 / f noise coefficient ratio decreases when the annealing temperature immediately after formation of the gate oxide film is increased. However, it has been found that in a MOSFET having a gate oxide film thickness of 3 nm, the noise coefficient ratio increases when the annealing temperature immediately after formation of the gate oxide film is increased. This is because the 1 / f noise is improved by increasing the annealing temperature when the gate oxide film thickness is 12 nm, but conversely by increasing the annealing temperature when the gate oxide film thickness is 3 nm, the 1 / f noise is improved. f means increasing noise.

  Accordingly, the present invention has been made in view of the above problems found by the present inventors, and a method for manufacturing a semiconductor device capable of reducing 1 / f noise even when the gate insulating film thickness of a transistor is thin. The purpose is to provide.

  The present inventor believes that the cause (mechanism) in which the above problem occurs is the gate oxide film thickness and the gas atmosphere during annealing. More specifically, when annealing is performed immediately after the formation of the gate oxide film, the annealing is generally performed in a nitrogen atmosphere in consideration of an increase in the gate oxide film thickness. However, when the gate oxide film is thin, nitrogen, which is the atmosphere during annealing, enters the gate oxide film, diffuses in the gate oxide film, and reaches the gate oxide film / silicon substrate interface. As a result, the interface state of the gate oxide film / silicon substrate is increased, and 1 / f noise is increased. For this reason, as shown in FIG. 9, when the gate oxide film thickness is 3 nm, the 1 / f noise cannot be reduced unlike the case of 12 nm. Based on such considerations, the present inventor proposes a semiconductor device manufacturing method described below.

  That is, in the method for manufacturing a semiconductor device according to one embodiment of the present invention, a step of forming a gate insulating film having a thickness of 6.5 nm or less over a substrate, and a step of depositing the gate electrode film on the gate insulating film And, after depositing the gate electrode film, subjecting the substrate to a high temperature annealing of 965 ° C. or higher, and after subjecting the substrate to the high temperature annealing, patterning the gate electrode film to remove the gate electrode film from the gate electrode film Forming a gate electrode on the gate insulating film.

In the method for manufacturing a semiconductor device, heat of 965 ° C. or higher may not be applied to the substrate between the step of forming the gate insulating film and the step of forming the gate electrode film.
In the method of manufacturing a semiconductor device, in the step of depositing the gate electrode film, a non-doped polysilicon film having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ or less is deposited as the gate electrode film. The method may further comprise a step of doping the non-doped polysilicon film with an impurity after the high temperature annealing is performed on the substrate.

In the method for manufacturing a semiconductor device, the high temperature annealing treatment temperature may be 965 ° C. or more and 1125 ° C. or less, and the high temperature annealing treatment time may be 15 seconds or more and 60 seconds or less.
In the method for manufacturing a semiconductor device, the high-temperature annealing treatment atmosphere may be a mixed gas containing nitrogen and oxygen.

  According to one embodiment of the present invention, high-temperature annealing is performed after forming a gate electrode film and before patterning the gate electrode film. Accordingly, nitrogen that adversely affects the interface state of the gate insulating film / substrate interface can be suppressed from being injected into the gate insulating film. Therefore, even when the gate insulating film of the transistor is thin, high temperature annealing is effective. / F noise can be reduced.

The figure which shows the main processes of the manufacturing method of the semiconductor device 100 which concerns on embodiment. FIG. 6 is a diagram showing a method for manufacturing the semiconductor device 100 in the order of steps. FIG. 6 is a diagram showing a method for manufacturing the semiconductor device 100 in the order of steps. FIG. 6 is a diagram showing a method for manufacturing the semiconductor device 100 in the order of steps. The figure which shows the result of the experiment which this inventor conducted. The figure which shows the result of the experiment which this inventor conducted. The figure which shows the result of the experiment which this inventor conducted. The figure which shows the result of the experiment which this inventor conducted. FIG. 6 is a diagram for explaining a problem, which is a result of an experiment performed by the inventor.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and repeated description thereof is omitted.
(Production method)
FIG. 1 is a diagram showing main steps of a method for manufacturing a semiconductor device 100 according to an embodiment of the present invention. As shown in FIG. 1, the method of manufacturing the semiconductor device 100 includes a wafer preparation step (step S10), an element isolation film formation / impurity implantation step (step S20), and a gate oxide film formation step. (Step S30), a step of forming the gate electrode film 13 (Step S40), a step of performing high-temperature annealing (Step S50), a step of patterning / implanting the gate electrode film 13 (Step S60), And a step of completing the transistor by the CMOS process (step S70). Hereinafter, each step will be described more specifically.

2 to 4 are cross-sectional views showing the method of manufacturing the semiconductor device 100 in the order of steps.
As shown in FIG. 2A, as an example of a wafer, a silicon substrate 1 made of, for example, single crystal silicon is prepared (step S10). The surface of the silicon substrate 1 may be a silicon epitaxial layer (not shown) obtained by epitaxially growing single crystal silicon.
Next, a field oxide film 3 is formed on the surface of the silicon substrate 1, and the regions where MOSFETs are formed and regions where other elements are formed are electrically isolated (step S20). The field oxide film 3 may be of any form as long as it is formed as an element isolation layer, and may be, for example, LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation). In the present embodiment, for example, STI is illustrated. By this field oxide film 3, for example, a region where a gate oxide film forms a thick MOSFET (hereinafter referred to as a first MOS region) and a region where a gate oxide film forms a thin MOSFET (hereinafter referred to as a second MOS region). ) Are separated from each other.

  Next, an impurity for forming a well (WELL) layer (not shown) or adjusting the threshold value of the MOSFET is ion-implanted in each of the first MOS region and the second MOS region of the silicon substrate 1 (step S20). Here, the impurity is, for example, a donor element such as phosphorus (P) or an acceptor element such as boron (B). Depending on the purpose, donor elements or acceptor elements are selected.

Next, as shown in FIG. 2B, the surface of the silicon substrate 1 is thermally oxidized to form a first gate oxide film 5 in each of the first MOS region and the second MOS region. The film thickness of the first gate oxide film 5 is, for example, about 12 nm. The film quality of the first gate oxide film 5 is not limited to the silicon oxide film (SiO ₂ ), but may be a silicon oxynitride film (SiON).
Next, as shown in FIG. 2C, the first gate oxide film 5 is removed from the second MOS region to expose the surface of the silicon substrate 1. The partial removal of the first gate oxide film 5 is performed by wet etching using a resist pattern as a mask.

  More specifically, first, a low-pressure CVD oxide film 7 is deposited on the entire upper portion of the silicon substrate 1. The film thickness after deposition of the low-pressure CVD oxide film 7 is, for example, about 10 nm. Next, a resist pattern 9 having a shape that opens above the second MOS region and covers the top of the first MOS region is formed on the low-pressure CVD oxide film 7. Then, using this resist pattern 9 as a mask, low-pressure CVD oxide film 7 and first gate oxide film 5 are removed by etching. This etching is, for example, wet etching using hydrofluoric acid (HF). As a result, the low-pressure CVD oxide film 7 and the first gate oxide film 5 are removed from the second MOS region to expose the surface of the second MOS region. Thereafter, the resist pattern 9 is removed by ashing, for example.

Next, wet etching is performed on the entire surface of the silicon substrate 1 to remove the low-pressure CVD oxide film 7 from the first MOS region. In this wet etching process, the processing conditions (eg, hydrofluoric acid concentration in the etchant, etching processing time, etc.) are adjusted so that the first gate oxide film 5 formed in the first MOS region is not etched as much as possible. To do.
Next, as shown in FIG. 3A, the surface of the silicon substrate 1 is thermally oxidized to form a second gate oxide film 11 in the second MOS region (step S30). The film thickness of the second gate oxide film 11 is 6.5 nm or less, for example, about 3 nm.

Next, as shown in FIG. 3B, the gate electrode film 13 is deposited over the entire upper portion of the silicon substrate 1 (step S40). The film thickness of the gate electrode film 13 is, for example, about 250 nm.
In the case where a polysilicon film is deposited as the gate electrode film 13, the polysilicon film has a donor element and an acceptor element concentration of not more than a detection limit value (for example, each concentration is 1 × 10 ¹⁶ cm ⁻³ or less, which is ideal. It is preferable that the non-doped polysilicon film be zero). The reason is that when the acceptor element or the like is present in the polysilicon, the acceptor element or the like oozes out from the gate electrode film 13 to the gate oxide film or the silicon substrate by performing the high temperature annealing in the next step. This is because there is a possibility of adverse effects such as changing the threshold voltage (Vth).

Next, immediately after the gate electrode film 13 is formed, the silicon substrate 1 is subjected to high temperature annealing by, for example, RTA (Rapid Thermal Anneal) method (step S50). This high temperature annealing is performed in a mixed gas atmosphere containing, for example, nitrogen (N ₂ ) and oxygen (O ₂ ). As shown in the experimental results described later, in this step, 1 / f noise can be effectively reduced by setting the annealing temperature to 965 ° C. or more and the annealing time to 15 seconds or more.

  Note that the annealing temperature is high, and the 1 / f noise can be further reduced by increasing the annealing time. However, if these values are increased indefinitely, disadvantages (for example, a transistor whose thermal history changes) The characteristics greatly change, the load on the processing apparatus increases, the throughput decreases, and the like). Therefore, in order to reduce 1 / f noise while suppressing demerits, it is necessary to set an upper limit value for the annealing temperature and the annealing time, respectively. From the experimental results described later, it is preferable that the annealing temperature is 1125 ° C. as the upper limit and the annealing time is 60 sec as the upper limit.

  In this high temperature annealing step, it is preferable that the polysilicon film deposited as the gate electrode film 13 is annealed at a high temperature in a state where it is a non-doped polysilicon film. By not implanting impurity ions into the gate electrode film 13 before the high-temperature annealing, acceptor elements and the like exude from the gate electrode film 13 to the gate oxide film and the silicon substrate, thereby changing the threshold voltage (Vth) of the MOSFET. It is possible to reduce adverse effects such as

In order to improve the MOS characteristics, it is necessary to suppress the gate depletion during the MOS operation. If annealing is performed after the gate pattern is formed, impurities may leak out from the gate electrode to the Si substrate. Therefore, impurities into the gate polysilicon for suppressing gate depletion during MOS operation Infusion may not be performed.
However, in this embodiment, high temperature annealing is performed immediately after depositing the gate polysilicon, and impurities are implanted into the gate polysilicon after the high temperature annealing. As a result, it is possible to introduce impurities into the gate polysilicon for suppressing the gate depletion during the MOS operation while suppressing the leakage of impurities from the gate electrode film 13 to the silicon substrate. Become. Therefore, not only 1 / f noise but also MOS characteristics with improved characteristics can be obtained.

  Next, as shown in FIG. 3C, an impurity is implanted to make the gate electrode film 13 conductive (to suppress depletion of the gate during the MOS operation) (step S60). Here, the impurity is, for example, a donor element such as phosphorus (P) or an acceptor element such as boron (B). Depending on the purpose, donor elements or acceptor elements are selected. Note that the impurity implantation step in step S60 may be omitted. In the source / drain formation process, which will be described later, the first and second gate electrodes are doped with impurities at a high concentration by ion-implanting the impurities using the first and second gate electrodes as a mask. is there.

Next, as shown in FIG. 4A, the gate electrode film 13 is patterned to form the first gate electrode 15 on the first gate oxide film 5 in the first MOS region, and at the same time, the second A second gate electrode 17 is formed on the second gate oxide film 11 in the MOS region (step S60).
Thereafter, using a general semiconductor manufacturing process, the MOSFET is completed through a sidewall forming process, a source / drain forming process, an interlayer insulating film forming process, a wiring forming process, and the like (step S70). For example, as shown in FIG. 4B, a side wall 19 made of an insulating layer is formed on the side surface of the first gate electrode 15 and a side wall 21 made of an insulating layer is formed on the side surface of the second gate electrode 17. To do. Further, by performing ion implantation of impurities twice before and after the step of forming the sidewalls 19 and 21, the source / drain 23 having the LDD structure is formed in the first MOS region and the LDD is formed in the second MOS region. A source / drain 25 of the structure is formed. Thereafter, as shown in FIG. 4C, silicides 31 are formed on the upper surfaces of the first and second gate electrodes 15 and 17 and the surfaces of the source / drains 23 and 25, respectively. Thereafter, an interlayer insulating film, wiring and the like (not shown) are formed.

Through these steps, the first MOSFET 110 having the thick first gate oxide film 5 in the first MOS region is completed, and the thin second gate oxide film 11 is formed in the second MOS region. The second MOSFET 120 is completed.
In this embodiment, the silicon substrate 1 corresponds to the “substrate” of the present invention, the second gate oxide film 11 corresponds to the “gate insulating film” of the present invention, and the second gate electrode 17 corresponds to the “substrate” of the present invention. It corresponds to the “gate electrode”.

(Effect of embodiment)
The embodiment of the present invention has the following effects.
(1) High-temperature annealing (step S50) is performed after forming the gate electrode film 13 and before patterning the gate electrode film 13. Since the gate oxide films 5 and 11 are covered with the gate electrode film 13 during the high temperature annealing, nitrogen that adversely affects the interface state at the gate oxide film / silicon substrate interface is implanted into the gate oxide films 5 and 11. Can be suppressed.
This makes it possible to select an annealing temperature and annealing time that have a 1 / f noise reduction effect without depending on the gate oxide film thickness. For example, even when the gate oxide film of the MOSFET is thin like the gate oxide film 11 having a thickness of 3 nm, the 1 / f noise can be sufficiently reduced by high-temperature annealing.

(2) Further, no annealing treatment is performed between the step of forming the gate oxide films 5 and 11 and the step of forming the gate electrode film 13. Thereby, it is possible to prevent nitrogen or the like from being implanted into the gate oxide films 5 and 11 before the gate oxide films 5 and 11 are covered with the gate electrode film 13.
(3) It is preferable to form a non-doped polysilicon film as the gate electrode film 13. The doping of the impurity (that is, donor element or acceptor element) into the non-doped polysilicon film is performed at least after high-temperature annealing. Thereby, impurities doped in the non-doped polysilicon film can be prevented from being implanted into the gate oxide films 5 and 11 by high-temperature annealing.

(4) Moreover, it is preferable that the processing temperature of high temperature annealing shall be 965 degreeC or more and 1125 degrees C or less, and the processing time of high temperature annealing shall be 15 seconds or more and 60 seconds or less. As shown in the experimental results to be described later, by setting the processing temperature and processing time of the high temperature annealing within the above ranges, even in the MOSFET 120 having a gate oxide film thickness of 6.5 nm or less, the demerits (for example, the thermal history changes, 1 / f noise can be efficiently reduced while suppressing large variations in transistor characteristics, an increase in load on the processing apparatus, and a decrease in throughput.

(5) Further, the high temperature annealing in step S50 is preferably performed in a mixed gas atmosphere containing nitrogen and oxygen. As a result, the gate electrode film 13 made of a non-doped polysilicon film can be prevented from being etched (ie, thermally etched) during high temperature annealing.
(6) In order to improve the MOS characteristics, it is necessary to suppress the depletion of the gate during the MOS operation. In this embodiment, high-temperature annealing is performed immediately after depositing gate polysilicon, and impurities are implanted into the gate polysilicon after this high-temperature annealing. As a result, it is possible to introduce impurities into the gate polysilicon for suppressing the gate depletion during the MOS operation while suppressing the leakage of impurities from the gate electrode film 13 to the silicon substrate. Become. Therefore, not only 1 / f noise but also more excellent MOS characteristics can be obtained.

(Other)
The present invention is not limited to the embodiment described above. Based on the knowledge of those skilled in the art, design changes and the like can be made to each embodiment, and an aspect in which such changes and the like are added is also included in the scope of the present invention.
Further, fluorine ion implantation may be performed before and after the high temperature annealing step. Fluorine injected into the gate electrode diffuses in the vicinity of the interface between the gate oxide film and the silicon substrate in a subsequent thermal process in the manufacturing process, and terminates dangling bonds existing at the interface, thereby reducing the 1 / f noise. is there. Here, the fluorine ion implantation is effective regardless of whether it is performed before or after the high-temperature annealing process, but it is more effective if it is performed before the high-temperature annealing process. This is because the high-temperature annealing process has the highest temperature in the thermal process after the gate electrode film is formed, and thus greatly contributes to the activation rate of fluorine. The greater the amount of heat after fluorine injection, the greater the dangling bond termination effect, and the greater the 1 / f noise reduction effect.

Next, the experiment conducted by the inventor and the result thereof will be described. In Experiments 1 to 4 described below, the experiment was performed under the conditions of Vg = Vd = Vth−0.4 V and Vs = Vsub = 0 V as in the case of FIG. 9 described above. Further, by the K _f value for each annealing temperature as compared to the K _f value when no annealing calculates 1 / f noise coefficient ratio, it compares the calculated 1 / f noise coefficient ratio, 1 / f noise Evaluated.

(Experiment 1)
FIG. 5 shows the results of Experiment 1 conducted by the present inventors, and the relationship between the annealing temperature and noise when annealing is performed immediately after formation of the gate oxide film for a PMOSFET having a gate oxide film thickness of 3 nm, and It is a figure which shows the result of investigating the relationship between the annealing temperature and 1 / f noise, respectively, when annealing is performed immediately after the formation of the gate electrode film (corresponding to the MOSFET 120 of this embodiment). The horizontal axis in FIG. 5 indicates the annealing temperature [° C.], and the vertical axis indicates the 1 / f noise coefficient ratio [%].

  As shown in FIG. 5, when annealing is performed immediately after the formation of the gate oxide film, the noise coefficient ratio increases as the annealing temperature is increased. On the other hand, when annealing was performed immediately after the formation of the gate electrode film, not immediately after the formation of the gate oxide film, it was found that the noise coefficient ratio decreased when the annealing temperature was raised. In particular, it has been found that when the annealing temperature is 965 ° C. or higher, the difference in the noise coefficient ratio between the two data increases. From this result, it was found that when the gate oxide film thickness is 3 nm and annealing is performed immediately after the formation of the gate electrode film, the annealing temperature is preferably 965 ° C. or higher.

(Experiment 2)
FIG. 6 shows the result of Experiment 2 conducted by the present inventor. For a PMOSFET having a gate oxide film thickness of 3 nm, the processing time when annealing is performed immediately after the formation of the gate electrode film (that is, annealing time), It is a figure which shows the result of having investigated the relationship with 1 / f noise. The horizontal axis of FIG. 6 shows annealing time [s], and the vertical axis shows 1 / f noise coefficient ratio [%]. The annealing temperature was set to 1100 ° C.

  As shown in FIG. 6, it was found that the longer the annealing time, the lower the noise coefficient ratio. Further, it was found that the degree of reduction in the noise coefficient ratio was large between 0 and 15 seconds and decreased at 15 seconds or more. From this result, it was found that when the gate oxide film thickness is 3 nm and annealing is performed immediately after the formation of the gate electrode film, the annealing time is preferably set to 15 seconds or more.

(Experiment 3)
FIG. 7 shows the result of Experiment 3 conducted by the inventor. Regarding the PMOSFET having a gate oxide film thickness of 6.5 nm, the relationship between the annealing temperature and noise when annealing is performed immediately after the formation of the gate oxide film, and FIG. 10 is a diagram showing the results of investigating the relationship between the annealing temperature and 1 / f noise when annealing is performed immediately after formation of the gate electrode film. In FIG. 7, the horizontal axis indicates the annealing temperature [° C.], and the vertical axis indicates the 1 / f noise coefficient ratio [%].

  As shown in FIG. 7, when annealing is performed immediately after the formation of the gate oxide film, the noise coefficient ratio increases as the annealing temperature is increased. On the other hand, when annealing was performed immediately after the formation of the gate electrode film, it was found that the noise coefficient ratio decreased when the annealing temperature was raised. In particular, it has been found that when the annealing temperature is 965 ° C. or higher, the difference in the noise coefficient ratio between the two data increases. From this result, it was found that when the gate oxide film thickness is 6.5 nm and annealing is performed immediately after the formation of the gate electrode film, the annealing temperature is preferably 965 ° C. or higher.

(Experiment 4)
FIG. 8 shows the result of Experiment 4 conducted by the inventor. The relationship between the annealing temperature and noise in the case of annealing the PMOSFET having a gate oxide film thickness of 12 nm immediately after forming the gate oxide film, and the gate It is a figure which shows the result of investigating the relationship between the annealing temperature and 1 / f noise, respectively, when annealing is performed immediately after formation of the electrode film (corresponding to the MOSFET 110 of this embodiment). The horizontal axis in FIG. 8 indicates the annealing temperature [° C.], and the vertical axis indicates the 1 / f noise coefficient ratio [%].

  As shown in FIG. 8, when annealing is performed immediately after the formation of the gate oxide film and when annealing is performed immediately after the formation of the gate electrode film, the noise coefficient ratio is reduced when the annealing temperature is increased. I understood that. As described above, from the results of Experiments 2 to 4, in a MOSFET having a gate oxide film thickness of 6.5 nm or less, a 1 / f noise reduction effect can be sufficiently obtained by performing high-temperature annealing at 965 ° C. or more immediately after forming the gate electrode film. I found out I could get it. In addition, it was found that the effect is remarkable even in high-temperature annealing at 1125 ° C.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 Field oxide film 5 First gate oxide film 7 Low-pressure CVD oxide film 9 Resist pattern 11 Second gate oxide film 13 Gate electrode film 15 First gate electrode 17 Second gate electrodes 19 and 21 Side wall 23, 25 Source / drain 31 Silicide 100 Semiconductor device 110 First MOSFET
120 second MOSFET

Claims (5)

Forming a gate insulating film having a film thickness of 6.5 nm or less on the substrate;
Depositing the gate electrode film on the gate insulating film;
Subjecting the substrate to high temperature annealing at 965 ° C. or higher after depositing the gate electrode film;
And a step of patterning the gate electrode film to form a gate electrode made of the gate electrode film on the gate insulating film after performing the high temperature annealing on the substrate. Production method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein heat of 965 ° C. or higher is not applied to the substrate between the step of forming the gate insulating film and the step of forming the gate electrode film. In the step of depositing the gate electrode film, an undoped polysilicon film having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ or less is deposited as the gate electrode film,
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of doping the non-doped polysilicon film with an impurity after the high-temperature annealing is performed on the substrate. The processing temperature of the high-temperature annealing is 965 ° C. or more and 1125 ° C. or less,
4. The method for manufacturing a semiconductor device according to claim 1, wherein a processing time of the high-temperature annealing is set to 15 seconds or more and 60 seconds or less. 5.   5. The method of manufacturing a semiconductor device according to claim 1, wherein a processing atmosphere for the high-temperature annealing is a mixed gas containing nitrogen and oxygen.

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