JP2006245306A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for suppressing damage to a gate insulation film to reduce gate leakage current and having a gate electrode with a work function similar to that of p-type polysilicon. <P>SOLUTION: The gate insulation film 3 is formed on a silicon substrate 1. A TiN film 4 is formed on the gate insulation film 3 by a CVD method at a temperature of 450°C or lower. The TiN film 4 is etched to form the gate electrode 5. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device using TiN (titanium nitride) as a metal gate material.

  Currently, as a CMOS device, a silicon oxide film is used as a gate insulating film, and p-type or n-type polysilicon is used as a gate electrode. In the logic after the 45 nm node of the CMOS, in order to improve the on-current, for example, the practical application of a metal gate technique using a metal material for the gate electrode shown in Non-Patent Document 1 is required. The on-current is the current that flows between the source and drain when a voltage is applied to the gate electrode of a MISFET (Metal-Insulator-Semiconductor Field Effect Transistor). It increases in proportion to the amount of charge induced in the channel region formed in the substrate.

  Therefore, in order to increase the amount of charge, practical application of a high dielectric (High-k) material as a gate insulating film has been studied. However, when a high-k material is used for the gate insulating film and polysilicon is used for the gate electrode, the threshold voltage increases in the p-type MISFET, and the device performance is degraded. For this reason, it is necessary to use a metal material for the gate electrode.

  A major obstacle in putting the metal gate technology into practical use is that it is difficult to control the threshold voltage. Conventionally, an n-type polysilicon is used for an n-type MISFET and a p-type polysilicon is used for a p-type MISFET, thereby obtaining a work function equivalent to that of a substrate channel. As a result, a MISFET having a low threshold voltage can be formed, and a CMOS transistor capable of low voltage operation can be realized.

  Further, TiN (titanium nitride) having a work function close to that of p-type polysilicon has attracted attention in order to control an increase in threshold voltage in the p-type MISFET. TiN deposited by the conventional sputtering method has a work function of about 4.6 eV, and has a large difference from the work function of p-type polysilicon, and the increase in threshold voltage cannot be sufficiently suppressed.

  In order to solve this problem, for example, Non-Patent Document 2 proposes a technique for controlling the work function by controlling the nitrogen concentration in the TiN film. Further, when the TiN film is formed by the CVD method, the mainstream is that the film forming temperature is about 600 ° C. However, for example, when the divided film forming disclosed in Patent Document 1 is applied, the temperature is about 450 ° C. However, film formation is possible.

International Technology Roadmap for Semiconductors (ITRS), 2003 Edition, April 2004 H.Wakabayashi, Y.Saito, K.Takeuchi, and T.Kunio, "A Dual-Metal Gate CMOS Technology Using Nitrogen-Concentration-Controlled TiNx Film", IEEE Transactions on Electron Devices, Vol. 48, No. 10, Oct 2001, p2363-p2369. Japanese Patent Laid-Open No. 2003-77864

  TiN (titanium nitride) has a work function close to that of p-type polysilicon, and can control an increase in threshold voltage in the p-type MISFET. However, when the gate electrode is formed by sputtering, damage due to the charge-up of the gate insulating film is caused, which increases the gate leakage current.

  In addition, the TiN film formed by the sputtering method has a work function of about 4.6 eV and a large difference from the work function of p-type polysilicon. It was.

  A method for controlling the work function by controlling the nitrogen concentration in the TiN film as in Non-Patent Document 2 has also been proposed. However, in the method disclosed in Non-Patent Document 2, only a control with a work function equivalent to n-type polysilicon is performed, and a TiN film corresponding to the work function of p-type polysilicon is not obtained. For this reason, there exists a subject that the raise of the threshold voltage in p-type MISFET cannot be suppressed.

  In the conventional split film formation disclosed in Patent Document 1, a TiN film is formed at about 450 ° C., and film formation at a lower temperature is not disclosed.

  The present invention has been made to solve the above-described problems, and by forming a TiN film as a metal gate material by a thermal CVD method, damage to the gate insulating film is suppressed and gate leakage current is reduced. An object of the present invention is to obtain a method of manufacturing a semiconductor device having a gate electrode having a work function close to that of p-type polysilicon.

  In the semiconductor device manufacturing method according to the present invention, a gate insulating film is formed on a semiconductor substrate, a TiN film is formed on the gate insulating film by a CVD method at a temperature of 450 ° C. or lower, and the TiN film is etched to form a gate. An electrode is formed.

  According to this invention, a gate insulating film is formed on a semiconductor substrate, a TiN film is formed on the gate insulating film by a CVD method at a temperature of 450 ° C. or less, and the TiN film is etched to form a gate electrode. Since the TiN film as the metal gate material is formed by the thermal CVD method, it is possible to suppress damage to the gate insulating film and reduce the gate leakage current. Further, by reducing the temperature of TiN film formation by CVD to 450 ° C. or lower, a work function close to that of p-type polysilicon can be realized. Further, when the temperature of TiN film formation by CVD is lowered to 350 ° C. or lower, a low stress TiN film can be obtained. This can also suppress the gate leakage current.

Embodiment 1 FIG.
As a result of the inventor's research and analysis in order to solve the conventional problem, TiN (titanium nitride) having a work function close to that of p-type polysilicon is used as a gate electrode material, and CVD (Chemical Vapor Deposition; It was found that the work function can be controlled by the film forming conditions by forming the film by the chemical vapor deposition method. In the first embodiment, the conditions for forming a TiN film by the CVD method are optimized, and the work function thereof is controlled substantially equal to that of p-type polysilicon.

FIGS. 1 to 5 are diagrams showing a configuration in each step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention, and the process proceeds from the manufacturing process shown in FIG. 1 to the manufacturing process shown in FIG. Note that each step is shown in a cross-sectional view so that the inside of the transistor can be seen.
In the process shown in FIG. 1, an element isolation oxide film 2 is formed in a predetermined region in the surface layer portion of a silicon substrate (semiconductor substrate) 1. The element isolation oxide film 2 is formed by, for example, the STI method (Shallow Trench Isolation method; shallow trench insulation method).

In the process shown in FIG. 2, the gate insulating film 3 is formed on the silicon substrate 1, and the TiN film 4 is formed thereon by the CVD method. The gate insulating film 3 is, for example, HfO ₂ (hafnium oxide film), HfSiON (hafnium silicon oxide), or SiON (silicon oxynitride).

Further, when the TiN film 4 is formed on the gate insulating film 3 by the CVD method, the TiN film 4 is formed by the CVD method using, for example, gas TiCl ₄ and gas NH ₃ and the film forming temperature is 450 ° C. or less. And The flow rates of these gases during film formation are in the range of 1 to 100 sccm and 1 to 1000 sccm, respectively.
1 sccm corresponds to 1.667 × 10 ⁻⁸ m ³ / s.

The TiN film 4 may be formed in a batch with a desired film thickness, or may be divided film formation in which the film is formed in steps from a thinner film thickness to a desired film thickness. In addition, after the TiN film 4 is formed, heat treatment may be performed for 3 seconds to 2 minutes in an NH ₃ atmosphere. Furthermore, when performing the divided film formation, the step of forming the TiN film 4 and the step of performing the heat treatment for 3 seconds to 2 minutes in the NH ₃ atmosphere may be alternately repeated.
This heat treatment will be briefly described. When a TiN film is formed using TiCl ₄ gas and NH ₃ gas, chlorine (Cl) remains in the TiN film. If the residual chlorine is contained in a large amount in the film, the specific resistance of the TiN film is increased, or if the TiN film is exposed to the air after film formation, the TiN film reacts with the air and is likely to be oxidized. Therefore, it is necessary to reduce and reduce residual chlorine in the film by heat treatment with NH ₃ after the film formation. In the present invention, by forming the TiN film as described above, a sufficient residual chlorine reduction effect can be obtained by a short-time NH ₃ heat treatment of about 3 seconds to 2 minutes. Furthermore, when the TiN film is dividedly formed, a sufficient residual chlorine reduction effect can be exhibited in a short time by performing NH ₃ heat treatment at the time when the TiN film is formed with a desired film thickness.

  In the process shown in FIG. 3, the TiN film 4 is patterned into a desired pattern by a combination of lithography and etching. As a result, a patterned TiN film 4 is formed on the gate electrode 5. Thereafter, the gate insulating film 3 formed other than immediately below the gate electrode 5 is removed.

In the step shown in FIG. 4, the first impurity diffusion layer 6 is formed by ion implantation. In forming the first impurity diffusion layer 6, B or BF ₂ is implanted at an acceleration voltage of, for example, 1 to 20 keV and an ion implantation amount of, for example, 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² .

In the process shown in FIG. 5, a silicon nitride film is deposited around the gate electrode 5, and the sidewall 7 is formed on the gate electrode 5 by an etch back method. Thereafter, the second impurity diffusion layer 8 is formed by ion implantation. In forming the second impurity diffusion layer 8, B or BF ₂ is implanted at an acceleration voltage of 5 to 30 keV and an ion implantation amount of, for example, 1 × 10 ^{15 to} 5 × 10 ¹⁵ cm ⁻² .

  Subsequently, for example, heat treatment is performed at 1000 ° C. to 1100 ° C. for about 10 seconds by RTA (Rapid Thermal Anneal). Thereafter, the device is completed through a wiring formation process for connecting to a known interlayer insulating film and FET.

  FIG. 6 is a graph showing capacitance-voltage (CV: Capacitance-Voltage) characteristics in the MIS capacitor. The curve connecting the black rhombus plots with the symbol a in the figure shows the TiN film formed by the CVD method, and the curve connecting the black square plots with the symbol b in the figure is the conventional curve. 2 shows a TiN film formed by the sputtering method.

  When the TiN film 4 is formed by the sputtering method, the work function of the gate electrode 5 made of the TiN film 4 estimated from the CV curve b is 4.56 eV. In this case, since the work function value is located almost in the middle between the n-type polysilicon and the p-type polysilicon, no improvement in performance can be expected in both the n-type and p-type MISFETs.

  On the other hand, when the TiN film 4 is formed by the CVD method, the gate bias is shifted in the positive direction as compared with the case where the TiN film 4 is formed by the sputtering method. This indicates that the work function of the gate electrode 5 made of the TiN film 4 estimated from the CV curve a has shifted toward the work function of p-type polysilicon, and the work function is 4.92 eV. . Accordingly, when the gate electrode 5 made of a TiN film formed by the CVD method is used for the p-type MISFET, the threshold voltage can be reduced without causing depletion of the gate electrode. For this reason, the performance of the device can be improved.

  FIG. 7 is a graph showing a current-voltage (IV) curve measured by the MIS capacitor. The curve connecting the black square plots with the symbol c in the figure shows a TiN film formed by the conventional sputtering method, and the curve connecting the black diamond plots with the symbol d in the figure is 2 shows a TiN film formed by a CVD method. As is clear from FIG. 7, the MIS capacitor using the gate electrode 5 made of the TiN film 4 by the CVD method has less damage to the gate insulating film 3 than the case where it is formed by the sputtering method, and suppresses the gate leakage current. You can see that it is made.

  As described above, according to the first embodiment, since the TiN film 4 as the gate electrode is formed by the CVD method, damage to the gate insulating film 3 at the time of forming the TiN film 4 is formed by the sputtering method. It can be significantly suppressed compared with. As a result, since the gate insulating film 3 is not deteriorated, the gate leakage current can be suppressed.

  Further, by forming the TiN film 4 by the CVD method, the work function of the gate electrode by the TiN film 4 can be controlled in the range of 4.9 to 5.0 eV, and the performance of the p-type MISFET can be improved. it can. Thereby, a high-performance device can be provided.

Embodiment 2. FIG.
In the second embodiment, the work function of the gate electrode is controlled by performing a heat treatment in a hydrogen atmosphere after the formation of the TiN film by the CVD method in the first embodiment.

  FIG. 8 is a diagram for explaining a heat treatment in manufacturing a semiconductor device according to the second embodiment of the present invention. The heat treatment shown in FIG. 8 is performed, for example, in a heat treatment atmosphere of hydrogen alone or a mixed atmosphere of hydrogen and nitrogen, for example, at a heat treatment temperature of 300 ° C. to 800 ° C. and a heat treatment time of 1 minute to 1 hour. In addition, as shown in FIG. 9, the heat treatment as described above may be performed after the second impurity diffusion layer 8 in FIG. 5 shown in the first embodiment is formed.

  FIG. 10 is a graph of capacitance-voltage (CV: Capacitance-Voltage) characteristics in the MIS capacitor. The curve connecting the black square plots with the symbol e in the figure shows the result of heat treatment at 400 ° C. for 10 minutes in a hydrogen atmosphere after the formation of the TiN film by the CVD method shown in the first embodiment. The curve obtained by connecting the black rhombus plots with the symbol f in the figure shows the result of forming the TiN film by the CVD method shown in the first embodiment without performing the heat treatment. .

  The CV curve e is more positive than the CV curve f by performing a heat treatment at 400 ° C. for 10 minutes in a hydrogen atmosphere on the TiN film 4 formed by the CVD method shown in the first embodiment. Shift in the direction of. The work function at this time is 5.03 eV, which is closer to the work function of p-type polysilicon. For this reason, further performance improvement can be aimed at.

  FIG. 11 is a diagram showing the work function of a TiN film electrode that has been heat-treated in a hydrogen atmosphere after film formation by sputtering, CVD, or CVD, respectively. As described above, by performing the processing according to the second embodiment, the level can be controlled to the same level as that of p-type polysilicon in the range of +0.47 eV as compared with the TiN film formed by the conventional sputtering method.

  As described above, according to the second embodiment, the work function of the gate electrode 5 formed of the TiN film 4 is formed by performing heat treatment in a hydrogen atmosphere after the formation of the TiN film 4, as shown in FIG. Can be increased to 5.03 eV. As a result, the gate electrode 5 closer to the work function of p-type polysilicon can be formed, so that higher performance of the device can be realized by further lowering the threshold electrode.

  In addition, by performing the process according to the second embodiment, the number of steps is increased as compared with the first embodiment. However, further performance improvement can be realized, and the required device specifications are matched. The adoption of the process shown in the second embodiment can be selected.

Embodiment 3 FIG.
In the third embodiment, when forming the TiN film in the manufacturing process of FIG. 2 shown in the first embodiment, the film forming temperature is set to 350 ° C., and the desired film thickness is formed by divided film formation. is there.

  FIG. 12 is a graph showing the results of measuring the stress of the TiN film when the film forming temperature is 450 ° C. and 350 ° C. in the TiN film forming process according to the third embodiment. As shown in FIG. 12, when the TiN film formation temperature is lowered to 350 ° C., the stress of the TiN film is dramatically reduced to almost 0 MPa. Further, even when the film formation temperature is lowered to 350 ° C., the divided film formation is used, so that an increase in sheet resistance of the film can be suppressed.

  FIG. 13 is a graph showing the current-voltage (IV) characteristics in the MIS capacitor. The curve connecting the black square plots with the symbol g in the figure shows the case where the film forming temperature is 450 ° C. The results show the results, and the curve connecting the black rhombus plots with the symbol h in the figure shows the results when the film forming temperature is 350 ° C.

  When comparing the MIS capacitors formed at the film forming temperatures under the above two conditions, the effect of reducing the gate leakage current was observed under the conditions of 350 ° C. Note that such a low-stress film can be obtained particularly at 350 ° C. or lower. As described above, by performing the processing according to the third embodiment, a low-stress film can be obtained and the gate leakage current can be suppressed. Thereby, the improvement of device performance is realizable.

  As described above, according to the third embodiment, the work function can be controlled to the same level as that of p-type polysilicon because the low-stress TiN film divided and formed at a low temperature is used as the gate electrode 5. In addition, membrane stress can be dramatically reduced. As a result, the threshold voltage can be controlled and the gate leakage current can be suppressed in the p-type MISFET, so that a high-performance device can be obtained.

It is a figure which shows the structure in each process of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows the structure in each process of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows the structure in each process of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows the structure in each process of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows the structure in each process of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a graph which shows the CV characteristic in a MIS capacitor. It is a graph which shows the IV characteristic measured with the MIS capacitor. It is a figure explaining the heat processing in the semiconductor device manufacture by Embodiment 2 of this invention. It is a figure explaining the other heat processing in the semiconductor device manufacture by Embodiment 2. FIG. It is a graph of the CV characteristic in a MIS capacitor. It is a figure which shows the work function of the TiN film | membrane electrode which heat-processed in the hydrogen atmosphere after film-forming by sputtering method, CVD method, and CVD method. It is a graph which shows the measurement result of the stress of the TiN film | membrane formed by TiN film-forming by Embodiment 3 of this invention. It is a graph which shows the IV characteristic in a MIS capacitor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate (semiconductor substrate), 2 isolation oxide film, 3 gate insulating film, 4 titanium nitride film, 5 gate electrode, 6 1st impurity diffused layer, 7 side wall, 8 2nd impurity diffused layer.

Claims (8)

  Forming a gate insulating film on the semiconductor substrate; forming a titanium nitride film on the gate insulating film by a CVD method at a temperature of 450 ° C. or less; and etching the titanium nitride film to form a gate electrode. And a method of manufacturing a semiconductor device. 2. The titanium nitride film is formed by using TiCl ₄ gas and NH ₃ gas in a CVD method, and forming the flow rates of these gases in the range of 1 to 100 sccm and 1 to 1000 sccm, respectively. Semiconductor device manufacturing method. _{3. The} method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing a heat treatment for 3 seconds to 2 minutes in an NH3 atmosphere after forming the titanium nitride film.   2. The titanium nitride film is formed by batch film formation up to a desired film thickness, or division film formation in a stepwise manner from a thinner film thickness to the desired film thickness. A method for manufacturing a semiconductor device according to claim 1. 5. The semiconductor device according to claim 4, wherein the divisional film formation is performed by alternately repeating a step of forming a titanium nitride film and a step of performing a heat treatment for 3 seconds to 2 minutes in an NH ₃ atmosphere. Production method.   6. The method of manufacturing a semiconductor device according to claim 4, wherein the divisional film formation is performed at a temperature of 350 [deg.] C. or less.   The method for manufacturing a semiconductor device according to claim 1, further comprising a step of performing a heat treatment at a temperature of 300 ° C. or higher in a hydrogen atmosphere after the formation of the titanium nitride film. 7. The method according to claim 1, further comprising a step of performing a heat treatment at a temperature of 300 ° C. or higher in a hydrogen atmosphere after the titanium nitride film is etched to form a gate electrode. Semiconductor device manufacturing method.

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