JP2005294799A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of optimizing the threshold voltage of both an NMOSFET and a PMOSFET and securing a large inversion capacity at the same time, and to provide its manufacturing method. <P>SOLUTION: An element isolation insulating film 2 is formed in the circumference of the element region of a silicon substrate 1. Moreover, an N-type diffusion layer region 6, a P-type diffusion layer region 7, a P-type extension region 18, an N-type extension region 19, a P-type source-drain region 23, an N-type source-drain region 24, and a nickel silicide film 25 are formed in the element region. A gate insulating film comprises a silicon oxide film 8 and a hafnium silicate nitride film 9. Moreover, the N-type gate electrode comprises a N-type silicon film 10a and a nickel silicide film 28. The P-type gate electrode comprises a nickel silicide film 28. On the sidewall of each gate electrode, the hafnium silicate nitride film 9 is not formed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a CMOSFET formed of an NMOSFET and a PMOSFET on a silicon substrate and a manufacturing method thereof.

  In recent years, high integration in semiconductor integrated circuit devices has greatly advanced. In MOS (Metal Oxide Semiconductor) type semiconductor devices, miniaturization of elements such as transistors and high performance have been achieved. In particular, with regard to the gate insulating film which is one of the elements constituting the MOS structure, the thinning is rapidly progressing to cope with the miniaturization, high speed operation and low voltage of the transistor.

Conventionally, a silicon oxide film (SiO ₂ film), a silicon oxynitride film (SiON film), or the like has been used as a material constituting the gate insulating film. However, when these materials are used, there is a problem that leakage current increases as the film thickness is reduced.

  On the other hand, a sub 0.1 μm generation CMOS (Complementary Metal Oxide Semiconductor) requires a performance of 1.5 nm or less in terms of a silicon oxide film with respect to a gate insulating film. For this reason, it has been proposed to use a material having a high relative dielectric constant, such as a metal oxide film or a metal silicate film (metal silicate film), as the gate insulating film, and to suppress the leakage current by increasing the film thickness.

  Hereinafter, a case where a semiconductor device is manufactured by a conventional method using a high dielectric constant insulating film as a gate insulating film will be described.

  First, as shown in FIG. 30A, a silicon oxide film is embedded in a predetermined region of the silicon substrate 301 to form an element isolation region 302 and a sacrificial oxide film 303 having an STI (Shallow Trench Isolation) structure.

  Next, as shown in FIG. 30B, P (phosphorus) ions are implanted into the silicon substrate 301 using the resist 304 as a mask. The implantation of P is performed a plurality of times for the purpose of forming a diffusion layer and adjusting the threshold voltage of the transistor. After the implantation of P, the resist 304 is peeled off, and B (boron) is implanted by using the resist (not shown) as a mask by the same method. After removing the resist, heat treatment is performed to diffuse the impurities, thereby forming the N-type diffusion layer 306 and the P-type diffusion layer 307 (FIG. 30C).

After the diffusion layer is formed, the sacrificial oxide film 303 is removed using an NH ₄ F aqueous solution. Thereafter, a thin silicon oxide film 308 is formed on the surface of the silicon substrate 301, and a hafnium silicate nitride film 309 is further formed as a high dielectric constant insulating film (FIG. 31A). Specifically, a hafnium silicate nitride film 309 can be formed by forming a hafnium silicate film on the silicon oxide film 308 and then performing a heat treatment in an NH ₃ atmosphere or an N ₂ plasma atmosphere.

  Next, as shown in FIG. 31B, after an amorphous silicon film 3010 is formed by a CVD (Chemical Vapor Deposition) method, P is ion-implanted using a resist 3011 as a mask to form an N-type gate electrode. To do. Note that a polycrystalline silicon film may be formed instead of the amorphous silicon film 3010.

  After the resist 3011 is removed, ions are implanted into the amorphous silicon film 3010 by the same method to form a P-type electrode. After removing the resist (not shown) used as a mask, a silicon oxide film 3013 is formed on the entire surface, and then the silicon oxide film 3013 is processed using the resist 3014 as a mask (FIG. 31C). In FIG. 31C, 3010a is an N-type amorphous silicon film, and 3010b is a P-type amorphous silicon film.

  Next, as shown in FIG. 32A, after removing the resist 3014, the N-type amorphous silicon film 3010a and the P-type amorphous silicon film 3010b are processed to form gate electrodes. Thereafter, using the silicon oxide film 3013 as a hard mask, the hafnium silicate nitride film 309 and the silicon oxide film 308 are etched so that the gate insulating film remains only under the gate electrode (FIG. 32B). Note that the silicon oxide film 3013 disappears by etching.

  Next, after slightly oxidizing the sidewalls of the gate electrodes 3010a and 3010b at a temperature of 900 ° C. to 1,000 ° C. in an atmosphere having an oxygen concentration of 0.05% to 1%, a silicon oxide film 3015 is formed by a CVD method. Deposited on the entire surface (FIG. 32 (c)).

  Next, B is ion-implanted into the N-type diffusion layer 306 using the resist 3016 and the gate electrode 3010b as a mask (FIG. 33A). Similarly, P ions are implanted into the P-type diffusion layer 307 as well. As a result, a P-type extension region 3018 and an N-type extension region 3019 are formed (FIG. 33B).

  Next, as shown in FIG. 33C, a silicon nitride film 3020 is formed on the entire surface by a CVD method. Thereafter, the silicon oxide film 3015 and the silicon nitride film 3020 are removed by reactive ion etching, leaving the side walls of the gate electrodes 3010a and 3010b.

  Next, as shown in FIG. 34A, B is ion-implanted into the N-type diffusion layer 306 using the resist 3021 and the gate electrodes (3010b, 3015, 3020) formed with the sidewalls as a mask. After the resist 3021 is removed, P is ion-implanted into the P-type diffusion layer 307 by the same method. Thereafter, heat treatment is performed at a temperature of 900 ° C. to 1,100 ° C. to activate the impurities, thereby forming a P-type source / drain diffusion layer 3023 and an N-type source / drain diffusion layer 3024 (FIG. 34B). ).

  Next, after forming a nickel film (not shown) and a titanium nitride film (not shown) on the entire surface, heat treatment is performed. Thereafter, the titanium nitride film and the unreacted nickel film are removed by etching, and a nickel silicide film 3025 is selectively formed only on the source / drain diffusion layers 3022 and 3023 and the silicon gate electrodes 3010a and 3010b (FIG. 34). (C)).

  Next, after an interlayer insulating film 3029 is formed, planarization is performed by a CMP (Chemical Mechanical Polishing) method (FIG. 35). Thereafter, contacts and wirings are formed.

  However, when the characteristics of the transistor formed by the above method are evaluated, an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) has an appropriate threshold voltage, whereas a PMOSFET (P-channel Metal Oxide Semiconductor Semiconductor). In the effect transistor, the threshold voltage is greatly shifted to the negative side. Furthermore, in the PMOSFET, the capacitance on the inversion side is smaller than that in the NMOSFET. For this reason, there arises a problem that a desired drain current cannot be secured (see, for example, Non-Patent Document 1).

  Therefore, in order to suppress the shift of the threshold voltage and obtain a large inversion capacity, studies have been made on using metal for the gate electrode instead of silicon. The metal in this case refers to metal, metal nitride, metal silicide, or the like. When metal is used for the gate electrode, the threshold voltage changes depending on the work function. For this reason, there is an advantage that the threshold voltage can be controlled by using a metal having an optimum work function. In addition, since depletion of the electrode is less likely to occur compared to the silicon electrode, there is an advantage that a large inversion capacity can be secured.

  However, since the metal electrode has poor heat resistance compared to the silicon electrode, it is difficult to form a transistor in the above-described process. That is, in the method of forming the source / drain diffusion layer after forming the gate electrode, high-temperature heat treatment at about 1,000 ° C. is required for activating the impurities. When such a thermal process is performed when a metal electrode is used, a change in the shape of the metal electrode, impurity diffusion into the gate insulating film, or the like occurs. Therefore, in the case of using a metal electrode, a method of forming a source / drain diffusion layer before forming a gate electrode has been proposed (see, for example, Non-Patent Documents 2 and 3).

  This method will be described below. For simplicity, the case where the same type of metal film is used for the gate electrodes of the NMOSFET and the PMOSFET is taken as an example.

  First, in the same manner as in FIGS. 30A to 30C, after the element isolation region 402 and the sacrificial oxide film 403 are formed on the silicon substrate 1, P (phosphorus) and B (boron) are sequentially implanted into the silicon substrate 401. Then, heat treatment is performed to form the N-type diffusion layer 406 and the P-type diffusion layer 407. Next, an amorphous silicon film 4010 is formed on the sacrificial oxide film 403 by a CVD method to obtain a structure shown in FIG. Note that a polycrystalline silicon film may be formed instead of the amorphous silicon film 4010.

  Next, after a silicon oxide film 4013 is formed on the entire surface, the silicon oxide film 4013 is processed using the resist 4014 as a mask (FIG. 36B). Further, after the resist 4014 is removed, the amorphous silicon film 4010 is processed using the silicon oxide film 4013 as a hard mask to form a gate electrode (FIG. 36C).

  Next, after slightly oxidizing the side wall of the gate electrode 10 at a temperature of 900 ° C. to 1,000 ° C. in an atmosphere having an oxygen concentration of 0.05% to 1%, a silicon oxide film 4015 is formed on the entire surface by CVD. accumulate. Thereafter, using a resist (not shown) and the gate electrode 4010 as a mask, B is ion-implanted into the N-type diffusion layer 406, and P is ion-implanted into the P-type diffusion layer 407, respectively, and the P-type extension region 4018 and the N-type extension region are implanted. 4019 is formed (FIG. 37A).

  Next, after a silicon nitride film 4020 is formed on the entire surface by using the CVD method, the silicon oxide film 4015 and the silicon nitride film 4020 are removed by reactive ion etching, leaving the side wall portion of the gate electrode 4010. Thereafter, B is ion-implanted into the N-type diffusion layer 406 by using the resist 4021 and the gate electrodes (4010, 4013, 4015, 4020) formed with the sidewalls as a mask (FIG. 37B).

  After removing the resist 4021, P is ion-implanted into the P-type diffusion layer 407 in the same manner. Thereafter, heat treatment is performed at a temperature of 900 ° C. to 1,100 ° C. to activate the impurities, thereby forming a P-type source / drain diffusion layer 4023 and an N-type source / drain diffusion layer 4024 (FIG. 37C). ).

Next, after removing the sacrificial oxide film 403 other than the lower portion of the gate electrode 4010 using dilute hydrofluoric acid or NH ₄ F aqueous solution, a nickel film and a titanium nitride film are formed on the entire surface, and heat treatment is performed. Thereafter, the nickel nitride film 4025 is selectively formed only on the source / drain diffusion layers 4023 and 4024 by etching away the titanium nitride film and the unreacted nickel film (FIG. 38A).

  Next, after an interlayer insulating film 4026 is formed by a CVD method or a coating method, it is polished by a CMP method until the amorphous silicon film 4010 is exposed. Thereafter, the exposed amorphous silicon film 4010 is removed by reactive ion etching (FIG. 38B).

  Next, after removing the exposed sacrificial oxide film 403, a thin silicon oxide film 408 is formed on the surface of the silicon substrate 401, and a hafnium silicate film 409 is formed on the entire surface as a high dielectric constant insulating film (FIG. c)).

  Thereafter, a titanium nitride film 4030 and a tungsten film 4031 are deposited, and the tungsten film 4031 and the titanium nitride film 4030 on the interlayer insulating film 4026 other than the gate electrode 4010 are removed by CMP, and further on the interlayer insulating film 4026. After removing the hafnium silicate film 409, an interlayer insulating film 4029 is deposited and planarized (FIG. 39). Thereafter, contacts, wirings and the like are formed.

  However, when one type of metal film is used for the gate electrodes of both the NMOSFET and the PMOSFET, one of the threshold voltages deviates from an appropriate value. For example, as described above, when a titanium nitride film having a Fermi level near the center of the silicon band gap is used as the electrode of the high dielectric constant gate insulating film, the PMOSFET approaches an appropriate threshold voltage, whereas the NMOSFET However, there is a problem that the threshold voltage shifts to the positive side as compared with the case where a silicon electrode is used (FIG. 29B). This problem is not only when the titanium nitride film is used as the gate electrode of the high dielectric constant gate insulating film, but there is a Fermi level near the center of the silicon band gap, such as nickel silicide and cobalt silicide, as well as titanium nitride. This also occurs when the material is used for an NMOSFET electrode. Since such a problem does not occur when the silicon oxide film is used as the gate insulating film and nickel silicide is used as the gate electrode (see, for example, Non-Patent Documents 4 and 5), the high dielectric constant insulating film is used as the gate insulating film. This is considered to be a problem that occurs only when used.

  On the other hand, recently, attempts have been made to use metal gate electrodes having different work functions for NMOSFET and PMOSFET (see, for example, Patent Documents 1 to 3). In this case, an appropriate threshold voltage and a large inversion capacity can be expected. However, since the metal gate electrodes of NMOSFET and PMOSFET are formed separately, there is a problem that the manufacturing process increases and the cost increases. In the method described above, the nickel silicide 4025 is formed on the source / drain diffusion layers 4023 and 4024 before forming the gate insulating film. From the viewpoint of the resistance to aggregation of nickel silicide, the gate insulating film is formed. There is a problem that heat of 600 ° C. or higher cannot be applied during formation. For this reason, there is a restriction that the thermal process of the gate insulating film must be performed at a temperature of 600 ° C. or less, and it is difficult to improve the film quality of the gate insulating film.

  In order to avoid such a problem, it may be possible to form a gate insulating film having a high dielectric constant in advance instead of the sacrificial oxide film 403. In this case, sufficient heat treatment can be performed at the time of forming the gate insulating film. However, when the silicon electrode 4010 serving as the dummy gate electrode is removed by etching, the gate insulating film is damaged (damaged), and the gate insulating film is also formed. There is a problem that etching is removed together.

T. Aoyama et al., International Workshop on Gate Insulator, 2003, p. 174 A. Chatterjee et al., International Electron Devices Meeting (IEDM), 1997, p. 821 A. Yagishita et al., International Electron Devices Meeting (IEDM), 1998, p. 785 W. P. Maszara et al., International Electron Devices Meeting (IEDM), 2002, p. 367 Z. Krivokapic et al., International Electron Devices Meeting (IEDM), 2002, p. 271 JP 2000-252371 A JP 2003-258121 A Japanese Patent Laid-Open No. 2003-45995

  The above is summarized as follows.

  When the high dielectric constant insulating film is used as the gate insulating film, the silicon electrode has a problem that the threshold voltage of the PMOSFET is greatly shifted to the negative side and the inversion capacitance is decreased.

  In order to solve this problem, the method using a metal electrode has an advantage that a large inversion capacitance can be secured, but it is necessary to form a metal electrode having an optimum work function for each of the NMOSFET and the PMOSFET in a separate process. Become. For this reason, the problem that the number of processes increases and leads to an increase in cost arises newly. Considering the heat resistance of the metal electrode, the source / drain diffusion layer must be formed before the gate electrode is formed. However, since the heat resistance of the silicide formed on the surface of the source / drain diffusion layer is low, heat treatment cannot be performed at a high temperature when forming the gate insulating film, and it is difficult to improve the film quality of the gate insulating film. There is also a problem of becoming.

  Further, in order to avoid such a problem, in the method of forming the gate insulating film before forming the silicide on the source / drain diffusion layer and the source / drain diffusion layer, the gate electrode is removed when the silicon electrode to be a dummy gate electrode is removed by etching. There is a problem that the insulating film is damaged. In this case, the gate insulating film itself may be etched.

  The present invention has been made in view of such problems. That is, an object of the present invention is to provide a semiconductor device having a gate electrode structure that can optimize threshold voltages of both the NMOSFET and the PMOSFET and that can secure a large inversion capacitance, and a method for manufacturing the same. is there.

  Other objects and advantages of the present invention will become apparent from the following description.

  The present invention provides a semiconductor device including a CMOSFET composed of an NMOSFET and a PMOSFET on a silicon substrate, wherein the gate insulating film of the NMOSFET and the PMOSFET includes a first insulating film formed on the silicon substrate, A gate electrode of the NMOSFET having an N-type silicon film formed on the gate insulating film; and an N-type silicon film formed on the first insulating film. A gate electrode of the PMOSFET is formed of a second metal silicide film formed on the gate insulating film, and the second insulating film is a high metal film. A dielectric constant insulating film, wherein the high dielectric constant insulating film is disposed on either side of the gate electrode of the NMOSFET and the gate electrode of the PMOSFET. Is characterized in that is also not formed in.

  According to the present invention, in the semiconductor device including a CMOSFET composed of an NMOSFET and a PMOSFET on a silicon substrate, the gate insulating film of the NMOSFET and the PMOSFET is a first insulating film formed on the silicon substrate. And a second insulating film formed on the first insulating film, and the gate electrode of the NMOSFET includes an N-type silicon film formed on the gate insulating film, And a first metal silicide film formed on the N-type silicon film. The gate electrode of the PMOSFET includes a metal film formed on the gate insulating film and a second film formed on the metal film. The second insulating film is a high dielectric constant insulating film, and the high dielectric constant insulating film is a gate electrode of the NMOSFET. Preliminary is characterized in that the not be formed in any of the sidewalls of the gate electrode of the PMOSFET.

  In the semiconductor device of the present invention, the metal film may contain at least one metal selected from the group consisting of nickel, cobalt, palladium, rhodium, ruthenium, platinum and iridium.

  In the semiconductor device of the present invention, the first metal silicide film is selected from the group consisting of a nickel silicide film, a cobalt silicide film, a palladium silicide film, a rhodium silicide film, a ruthenium silicide film, a platinum silicide film, and an iridium silicide film. Any one single-layer film or a laminated film composed of two or more films can be used.

  In the semiconductor device of the present invention, the second metal silicide film is selected from the group consisting of a nickel silicide film, a cobalt silicide film, a palladium silicide film, a rhodium silicide film, a ruthenium silicide film, a platinum silicide film, and an iridium silicide film. Any one single-layer film or a laminated film composed of two or more films can be used.

  In the semiconductor device of the present invention, the high dielectric constant insulating film can be made of one substance selected from the group consisting of silicate nitride, silicate and oxide containing at least one of hafnium and zirconium. .

  In the semiconductor device of the present invention, the first insulating film can be any one film selected from the group consisting of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

  Furthermore, in the semiconductor device of the present invention, a third insulating film may be further formed on the high dielectric constant insulating film. Here, the third insulating film can be any one film selected from the group consisting of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

  The present invention relates to a method of manufacturing a semiconductor device including a CMOSFET composed of an NMOSFET and a PMOSFET, on a silicon substrate provided with an element isolation insulating film, an N-type diffusion layer region, and a P-type diffusion layer region. Forming a gate insulating film including a dielectric insulating film; forming a silicon film on the gate insulating film; implanting N-type impurities into the NMOSFET region of the silicon film; Processing the film into the shape of a gate electrode to form an N-type silicon film pattern and an undoped silicon film pattern; and removing the gate insulation except under the N-type silicon film pattern and the undoped silicon film pattern A step of removing the film, and a step of forming a first sidewall insulating film on the entire surface of the silicon substrate after the removal of the gate insulating film. Using the N-type silicon film pattern and the undoped silicon film pattern as a mask, implanting impurities into the silicon substrate to form an N-type extension region and a P-type extension region; and Forming a second sidewall insulating film on the first sidewall insulating film and the second sidewall insulating film except for a step of forming a second sidewall insulating film thereon and a sidewall portion of the N-type silicon film pattern and the undoped silicon film pattern; A step of removing, and implanting impurities into the silicon substrate using the N-type silicon film pattern and the undoped silicon film pattern in which the first and second sidewall insulating films are formed on the sidewall portions as a mask Forming an N-type source / drain region and a P-type source / drain region, and the N-type source Forming a first metal silicide film on the drain region and the P-type source / drain region; and forming the N-type silicon film pattern on the silicon substrate after the formation of the first metal silicide film; Forming an interlayer insulating film so as to embed an undoped silicon film pattern; processing the interlayer insulating film to expose surfaces of the N-type silicon film pattern and the undoped silicon film pattern; Etching the undoped silicon film pattern to a predetermined film thickness, forming a metal film on the entire surface of the silicon substrate, and heat-treating the upper part of the N-type silicon film pattern and all of the undoped silicon film pattern And a step of changing the metal film to a silicided second metal silicide film. It is characterized by having.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including a CMOSFET composed of an NMOSFET and a PMOSFET on a silicon substrate provided with an element isolation insulating film, an N-type diffusion layer region, and a P-type diffusion layer region. A step of forming a gate insulating film including a high dielectric constant insulating film, a step of forming a silicon film on the gate insulating film, a step of injecting an N-type impurity into the NMOSFET region of the silicon film, Processing the silicon film into the shape of a gate electrode to form an N-type silicon film pattern and an undoped silicon film pattern; and excluding the lower part of the N-type silicon film pattern and the undoped silicon film pattern Removing the gate insulating film; and forming a first sidewall insulating film on the entire surface of the silicon substrate after the gate insulating film is removed. A step of implanting impurities into the silicon substrate using the N-type silicon film pattern and the undoped silicon film pattern as a mask to form an N-type extension region and a P-type extension region, and the first sidewall insulation. Forming a second sidewall insulating film on the film; and excluding the sidewalls of the N-type silicon film pattern and the undoped silicon film pattern, the first sidewall insulating film and the second sidewall insulating film Removing the film, and using the N-type silicon film pattern and the undoped silicon film pattern in which the first sidewall insulating film and the second sidewall insulating film are formed on the sidewall portion as a mask, impurities in the silicon substrate And forming an N-type source / drain region and a P-type source / drain region, and the N-type Forming a first metal silicide film on the source / drain region and the P-type source / drain region, and forming the N-type silicon film on the silicon substrate after the formation of the first metal silicide film. Forming an interlayer insulating film so as to embed a pattern and the undoped silicon film pattern, and processing the interlayer insulating film to expose surfaces of the N-type silicon film pattern and the undoped silicon film pattern Forming a first metal film on the entire surface of the silicon substrate, and heat-treating the upper part of the N-type silicon film pattern and the upper part of the undoped silicon film pattern into a silicide by heat treatment. Changing to the second metal silicide film formed, and the second metal silicide film on the undoped silicon film pattern. A step of removing the metal silicide film, a step of sequentially forming a second metal film and a third metal film on the undoped silicon film pattern, and a heat treatment to thereby form the undoped silicon film and the second metal A structure in which the second metal film and the third metal silicide film in which the third metal film is silicided are sequentially stacked by reacting the film and the third metal film. And a step of forming on the substrate.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including a CMOSFET composed of an NMOSFET and a PMOSFET on a silicon substrate provided with an element isolation insulating film, an N-type diffusion layer region, and a P-type diffusion layer region. A step of forming a gate insulating film including a high dielectric constant insulating film, a step of forming a silicon film on the gate insulating film, a step of injecting an N-type impurity into the NMOSFET region of the silicon film, Processing the silicon film into the shape of a gate electrode to form an N-type silicon film pattern and an undoped silicon film pattern; and excluding the lower part of the N-type silicon film pattern and the undoped silicon film pattern Removing the gate insulating film; and forming a first sidewall insulating film on the entire surface of the silicon substrate after the gate insulating film is removed. A step of implanting impurities into the silicon substrate using the N-type silicon film pattern and the undoped silicon film pattern as a mask to form an N-type extension region and a P-type extension region, and the first sidewall insulation. Forming a second sidewall insulating film on the film; and excluding the sidewalls of the N-type silicon film pattern and the undoped silicon film pattern, the first sidewall insulating film and the second sidewall insulating film Removing the film, and using the N-type silicon film pattern and the undoped silicon film pattern in which the first sidewall insulating film and the second sidewall insulating film are formed on the sidewall portion as a mask, impurities in the silicon substrate And forming an N-type source / drain region and a P-type source / drain region, and the N-type Forming a first metal silicide film on the source / drain region and the P-type source / drain region, and forming the N-type silicon film on the silicon substrate after the formation of the first metal silicide film. Forming an interlayer insulating film so as to embed a pattern and the undoped silicon film pattern, and processing the interlayer insulating film to expose surfaces of the N-type silicon film pattern and the undoped silicon film pattern Forming a first metal film on the entire surface of the silicon substrate, and heat-treating the upper part of the N-type silicon film pattern and the upper part of the undoped silicon film pattern into a silicide by heat treatment. Changing to the second metal silicide film formed, and the second metal silicide in the region of the PMOSFET. Forming a second metal film on the doped film, and reacting the undoped silicon film, the second metal silicide film, and the second metal film by a heat treatment, to thereby form the second metal silicide. Forming a structure in which a film and a third metal silicide film obtained by siliciding the second metal film are sequentially stacked on the gate insulating film.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including a CMOSFET composed of an NMOSFET and a PMOSFET on a silicon substrate provided with an element isolation insulating film, an N-type diffusion layer region, and a P-type diffusion layer region. A step of forming a gate insulating film including a high dielectric constant insulating film, a step of forming a silicon film on the gate insulating film, a step of injecting an N-type impurity into the NMOSFET region of the silicon film, Processing the silicon film into the shape of a gate electrode to form an N-type silicon film pattern and an undoped silicon film pattern; and excluding the lower part of the N-type silicon film pattern and the undoped silicon film pattern Removing the gate insulating film; and forming a first sidewall insulating film on the entire surface of the silicon substrate after the gate insulating film is removed. A step of implanting impurities into the silicon substrate using the N-type silicon film pattern and the undoped silicon film pattern as a mask to form an N-type extension region and a P-type extension region, and the first sidewall insulation. Forming a second sidewall insulating film on the film; and excluding the sidewalls of the N-type silicon film pattern and the undoped silicon film pattern, the first sidewall insulating film and the second sidewall insulating film Removing the film, and using the N-type silicon film pattern and the undoped silicon film pattern in which the first sidewall insulating film and the second sidewall insulating film are formed on the sidewall portion as a mask, impurities in the silicon substrate And forming an N-type source / drain region and a P-type source / drain region, and the N-type Forming a first metal silicide film on the source / drain region and the P-type source / drain region, and forming the N-type silicon film on the silicon substrate after the formation of the first metal silicide film. Forming an interlayer insulating film so as to embed a pattern and the undoped silicon film pattern, and processing the interlayer insulating film to expose surfaces of the N-type silicon film pattern and the undoped silicon film pattern Forming a first metal film on the entire surface of the silicon substrate, and heat-treating the upper part of the N-type silicon film pattern and the upper part of the undoped silicon film pattern into a silicide by heat treatment. Changing to the second metal silicide film formed, and the second metal silicide in the region of the PMOSFET. A step of forming the first metal film on the doped film and a heat treatment to cause the undoped silicon film, the second metal silicide film, and the first metal film to react with each other to form the gate insulating film; And a step of forming the second metal silicide film thereon.

  Furthermore, the present invention provides a method of manufacturing a semiconductor device having a CMOSFET composed of an NMOSFET and a PMOSFET, on a silicon substrate provided with an element isolation insulating film, an N-type diffusion layer region, and a P-type diffusion layer region. A step of forming a gate insulating film including a high dielectric constant insulating film, a step of forming a silicon film on the gate insulating film, a step of injecting an N-type impurity into the NMOSFET region of the silicon film, Processing the silicon film into the shape of a gate electrode to form an N-type silicon film pattern and an undoped silicon film pattern; and excluding the lower part of the N-type silicon film pattern and the undoped silicon film pattern A step of removing the gate insulating film; and forming a first sidewall insulating film on the entire surface of the silicon substrate after the gate insulating film is removed. Using the N-type silicon film pattern and the undoped silicon film pattern as a mask, implanting impurities into the silicon substrate to form an N-type extension region and a P-type extension region, and the first sidewall insulation Forming a second sidewall insulating film on the film; and excluding the sidewalls of the N-type silicon film pattern and the undoped silicon film pattern, the first sidewall insulating film and the second sidewall insulating film Removing the film, and using the N-type silicon film pattern and the undoped silicon film pattern in which the first sidewall insulating film and the second sidewall insulating film are formed on the sidewall portion as a mask, impurities in the silicon substrate And forming an N-type source / drain region and a P-type source / drain region; Forming a first metal silicide film on the source / drain region and the P-type source / drain region; and forming the N-type silicon film pattern on the silicon substrate after the formation of the first metal silicide film. And forming an interlayer insulating film so as to embed the undoped silicon film pattern; and processing the interlayer insulating film to expose surfaces of the N-type silicon film pattern and the undoped silicon film pattern; The first metal film is silicided on the upper part of the N-type silicon film pattern and the upper part of the undoped silicon film pattern by a step of forming a first metal film on the entire surface of the silicon substrate and heat treatment. Changing to the second metal silicide film, and the second metal silicider in the region of the PMOSFET. A step of forming a second metal film on the id film and a heat treatment to cause the undoped silicon film, the second metal silicide film, and the second metal film to react with each other, and thereby the first metal film And a step of forming, on the gate insulating film, a structure in which a third metal silicide film in which the second metal film is silicided is sequentially laminated.

  In the method of manufacturing a semiconductor device according to the present invention, the step of forming the gate insulating film includes a step of forming a first insulating film on the silicon substrate, and a step of forming the high dielectric constant on the first insulating film. And a step of forming an insulating film.

  In the present invention, as described above, the gate electrode of the NMOSFET is composed of the N-type silicon film formed on the gate insulating film and the first metal silicide film formed thereon, and the gate electrode of the PMOSFET is Since the second metal silicide film is formed on the gate insulating film, the threshold voltages of the NMOSFET and PMOSFETT can be optimized and the inversion capacitance can be increased. In addition, since the high dielectric constant insulating film is not formed on the sidewalls of the gate electrode of the NMOSFET and the gate electrode of the PMOSFET, it is possible to sufficiently suppress the off current.

  According to the present invention, the gate electrode of the NMOSFET includes the N-type silicon film formed on the gate insulating film and the first metal silicide film formed thereon, and the gate electrode of the PMOSFET is Since it has a laminated structure of the metal film formed on the gate insulating film and the second metal silicide film formed thereon, the threshold voltage of each of the NMOSFET and PMOSFETT can be optimized, and It is possible to increase the inversion capacity.

  According to the present invention, since the high dielectric constant insulating film is formed before the gate electrode, there is no restriction such as setting the heat treatment temperature in consideration of the heat resistance of the silicide, and the heat treatment is performed at a desired temperature. be able to. Therefore, a high quality gate insulating film can be obtained.

  As described above, the present invention provides a gate electrode structure for controlling the threshold voltages of both the NMOSFET and the PMOSFET to be in an optimum state and securing a large inversion capacitance, and a method for manufacturing the same. Objective.

  In order to solve this problem, the following method is used in the present invention.

  First, after forming the element isolation region, a gate insulating film using a high dielectric constant insulating film is formed, and necessary and sufficient heat treatment is performed. Thereafter, a silicon film is deposited, and impurities such as P and As are ion-implanted into the silicon film in the region where the N-type gate electrode is formed. Then, the gate electrode is processed, the gate insulating film other than the gate portion is removed, and after forming the gate sidewall and the source / drain, silicide such as Ni or Co is formed on the surface of the source / drain in a self-aligned manner. Next, an interlayer insulating film is deposited on the entire surface, and the surface of the silicon electrode is exposed by CMP. The region where the N-type gate electrode is to be formed is masked with, for example, a resist or a SiN film, and the surface of the dummy silicon gate electrode in the region where the P-type gate electrode is formed is retreated and thinned. After removing the mask such as the resist or the SiN film, silicide is formed by reacting Ni, Co or the like with the silicon electrode in a self-aligning manner (salicide process). By making the film thickness of Ni, Co or the like equal to or greater than 54% of the remaining film thickness of the P-type dummy silicon gate, and less than 54% of the film thickness of the N-type silicon electrode, the N-type The gate electrode has a structure in which the gate insulating film and the N-type silicon electrode are in contact, and the P-type gate electrode has a structure in which Ni silicide or Co silicide is in contact with the gate insulating film.

  As a method for retreating the dummy silicon gate electrode of the P-type gate electrode portion, there are a method using reactive ion etching and a method of forming a silicide such as Ti in a self-aligned manner and removing the silicide by etching. Further, there is a method in which silicide such as Ni or Co is brought into contact with the gate insulating film by a silicon replacement method without retreating the dummy silicon electrode of the P-type gate electrode portion. That is, by masking the N-type gate electrode portion, a Ni film or a Co film is formed, then a Ti film or the like is formed, and further a TiN film or the like is formed and heat-treated. Ni silicide, Co silicide, and the like, which are diffusion species, are diffused in the silicon, and Ni silicide, which is a metal component, and Si silicide are diffusion species. When the reaction proceeds to absorb Si and form Ti silicide, a silicide of Ni or Co is formed immediately above the gate insulating film, and a silicide of Ti or the like is formed thereon. TiN functions as a cap film and suppresses oxidation of the Ti film, deterioration of the morphology of the silicide film, and the like. By thickening this Ti film, Si in Ni silicide or Co silicide is sufficiently sucked out, and metal Ni or Co can be in contact with the gate insulating film. In addition to Ni and Co, a similar method can be used for Pt group metals such as Ru, Rh, Ir, Pd and Pt because the diffusion species at the time of silicide formation are metals. In the above method, since all the dummy silicon electrodes in the P-type gate electrode portion are not removed, it is possible to suppress damage to the gate insulating film and avoid the problem that the gate insulating film is removed.

When formed in this way, N ⁺ polycrystalline silicon is in contact with the gate insulating film on the N-type gate electrode, and Pt group metal or metal silicide is in contact with the gate insulating film on the P-type gate electrode. Thus, it becomes possible to control the threshold voltage of the PMOSFET and ensure a sufficient inversion capacity.

Embodiment 1 FIG.
FIG. 1 is an example of a cross-sectional view of the semiconductor device in this embodiment.

  In FIG. 1, an element isolation insulating film 2 is formed around the element region of the silicon substrate 1. In the element region, an N type diffusion layer region 6, a P type diffusion layer region 7, a P type extension region 18, an N type extension region 19, a P type source / drain region 23, an N type source / drain region 24, and A nickel silicide film 25 is formed.

  The gate insulating film formed on the channel includes a first insulating film and a second insulating film formed on the first insulating film. Here, the first insulating film is a silicon oxide film 8 as a base interface layer. On the other hand, the second insulating film is a hafnium silicate nitride film 9 as a high dielectric constant insulating film.

  The N-type gate electrode is composed of an N-type silicon film 10 a and a nickel silicide film 28. On the other hand, the P-type gate electrode is made of a nickel silicide film 28. A silicon oxide film 15 and a silicon nitride film 20 are formed on the side walls of each gate electrode. However, the hafnium silicate nitride film 9 is not formed on the side wall of the gate electrode.

  2 and 3 are other examples of cross-sectional views of the semiconductor device in this embodiment. In these drawings, the same reference numerals as those in FIG. 1 indicate the same parts.

  FIG. 2 differs from FIG. 1 in that the P-type gate electrode is composed of a nickel silicide film 28 and a titanium nitride film 30 and a tungsten film 31 formed thereon.

  FIG. 3 differs from FIG. 2 in that the N-type gate electrode is composed of an N-type silicon film 10a and a nickel silicide film 28, and a titanium nitride film 30 and a tungsten film 31 formed thereon. In FIG. 3, a titanium film or the like may be formed between the nickel silicide film 28 and the titanium nitride film 30.

  Thus, in the present embodiment, the gate insulating film is composed of the silicon oxide film 8 and the hafnium silicate nitride film 9, and the gate electrode material in contact with the gate insulating film is an N-type silicon electrode, P for the N-type gate electrode. The type gate electrode is nickel silicide, and the hafnium silicate nitride film 9 is not located on the side wall portion of the gate electrode and is only on the lower portion of the gate electrode.

  In the above example, the hafnium silicate nitride film is used as the high dielectric constant insulating film, but the present invention is not limited to this. For example, a zirconium oxynitride film or the like may be used as the high dielectric constant insulating film, a hafnium silicate film (not containing nitrogen) or a zirconium silicate film, or the like (not containing silicon). A hafnium oxide film or a zirconium oxide film may be used. The high dielectric constant insulating film may be made of a material containing both elements of hafnium and zirconium.

  In the above example, the silicon oxide film 8 is used as the underlying interface layer, but the present invention is not limited to this. As the base interface layer, a silicon oxynitride film or a silicon nitride film may be used instead of the silicon oxide film.

  Furthermore, in this embodiment, a silicon oxide film or a silicon nitride film may be formed on the high dielectric constant insulating film.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. In these drawings, the same reference numerals indicate the same parts.

  First, as shown in FIG. 4A, a silicon oxide film is embedded in a predetermined region of the silicon substrate 1, and an element isolation region 2 and a sacrificial oxide film 3 having an STI structure are formed. Next, as shown in FIG. 4B, ion implantation of P (phosphorus) is performed using the resist 4 as a mask. The implantation of P is performed not only for the formation of the diffusion layer but also for adjusting the threshold voltage of the transistor, and is performed a plurality of times. In some cases, the threshold voltage may be adjusted by ion implantation of B (boron), In (indium), or the like. After injecting P, the resist 4 is peeled off, and further, B (boron) is injected by the same method to remove the resist, and then thermal diffusion is performed, whereby the N-type diffusion layer 6 and the P-type diffusion layer 7 are formed. It forms (FIG.4 (c)).

Thereafter, the sacrificial oxide film 3 is removed using an NH ₄ F aqueous solution. Thereafter, immediately after surface cleaning with 0.5% to 5% dilute hydrofluoric acid, a silicon oxide film 8 having a thickness of 0.5 nm is formed on the surface of the silicon substrate 1, and tetra-t-butoxyhafnium and Si ₂ H ₆ is used to form a hafnium silicate film 9a having a thickness of 2.0 nm. Thereafter, heat treatment is performed at a temperature of 250 ° C. to 400 ° C. in an atmosphere containing at least one gas selected from the group consisting of O ₂ , O ₃ , N ₂ O and NO at a concentration of 0.001% or more. Then, impurities such as carbon and hydrogen contained in the hafnium silicate film 9a are removed. Next, heat treatment is performed in an NH ₃ atmosphere or a nitrogen plasma atmosphere to modify the hafnium silicate film 9a into the hafnium silicate nitride film 9 (FIG. 5A).

  Next, as shown in FIG. 5B, a polycrystalline silicon film 10 is formed by CVD, and P ions are implanted into the silicon film 10 on the P-type diffusion layer region 7 using the resist 11 as a mask. . The film thickness of the silicon film 10 is preferably about 2 to 3 times the film thickness of the nickel silicide film 28 to be formed later. In this embodiment, an amorphous silicon film may be used instead of the polycrystalline silicon film. Further, a silicon germanium film may be used instead of the silicon film.

  After the resist 11 is removed, a silicon oxide film 13 is deposited, and the silicon oxide film 13 is processed using the resist 14 as a mask, as shown in FIG.

  After removing the resist 14, the N-type silicon film 10a and the silicon film 10 into which no impurity is implanted are processed into the shape of the gate electrode using the silicon oxide film 13 as a hard mask (FIG. 6A). In FIG. 6A, the gate electrode made of the silicon film 10 is a dummy gate electrode, and the gate electrode that actually operates is formed in a later step.

  Thereafter, the hafnium silicate nitride film 9 is removed by etching with dilute hydrofluoric acid or the like (FIG. 6B). At this time, the concentration of hydrofluoric acid and the etching time are selected so that the silicon oxide film 13 used as the hard mask is not completely removed. In this embodiment mode, it is desirable that the concentration of hydrofluoric acid is 1% or less and the etching time is 300 seconds or less. However, these conditions are appropriately determined according to the film type and film thickness of the high dielectric constant insulating film. Incidentally, since the silicon oxide film 8 which is the base interface layer is very thin as 0.5 nm, it is usually removed at the time of etching the hafnium silicate nitride film 9. However, there is no particular problem even if the silicon oxide film 8 remains on the entire surface without being removed.

  Next, the side wall of each gate electrode and the surface of the silicon substrate 1 are slightly oxidized. For example, by performing heat treatment at 1,000 ° C. for 5 seconds in an atmosphere containing 0.2% oxygen, the surface can be oxidized to a depth of about 2 nm. Thereafter, a silicon oxide film 15 as a first sidewall insulating film is formed on the entire surface by a CVD method (FIG. 6C). A film formed by oxidation may be used as the silicon oxide film 15. In some cases, the first sidewall insulating film may be omitted.

  Next, as shown in FIG. 7A, an N-type diffusion layer is formed using a resist 16 and a gate electrode made of the silicon film 10 on which the silicon oxide film 13 and the silicon oxide film 15 are formed as a mask. 6 is ion-implanted with B. After the resist 16 is removed, P is ion-implanted into the P-type diffusion layer 7 in the same manner, and activation is performed by heat treatment after the resist is removed. As a result, as shown in FIG. 7B, a P-type extension region 18 and an N-type extension region 19 are formed.

  Next, as shown in FIG. 7C, a silicon nitride film 20 as a second sidewall insulating film is formed by a CVD method. Thereafter, the silicon oxide film 15 and the silicon nitride film 20 are removed by reactive ion etching except for the side wall portion of the gate electrode.

  Next, as shown in FIG. 8A, B is ion-implanted into the N-type diffusion layer 6 using the resist 21 and the gate electrodes (10, 13, 15, 20) on which the sidewalls are formed as a mask. At this time, when the hard mask 13 is thin, B slightly enters the gate electrode 10. However, since the concentration is sufficiently low, B does not penetrate to the silicon substrate 1 by the activation heat treatment in the subsequent step. After the resist 20 is removed, P is ion-implanted into the P-type diffusion layer 7 in the same manner. After removing the resist, activation by heat treatment is performed to form a P-type source / drain diffusion layer 23 and an N-type source / drain diffusion layer 24 (FIG. 8B).

  Next, after a nickel film (not shown) and a titanium nitride film (not shown) are deposited on the entire surface, heat treatment is performed to form a first metal silicide film on the source / drain diffusion layers 23 and 24. The nickel silicide 25 is formed, and titanium nitride and unreacted nickel are removed by etching (FIG. 8C). In the conventional method, since the gate electrode made of silicon was exposed on the surface, a nickel silicide film was also formed on the gate electrode (FIG. 34C). On the other hand, according to the present embodiment, the silicon oxide film 13 is formed on the gate electrode, and silicon is not exposed on the surface, so that only the source / drain diffusion layers 23 and 24 are silicided.

  Next, a first interlayer insulating film 26 is deposited by the CVD method, and the surface of the gate electrode made of the N-type silicon film 10a and the surface of the dummy gate electrode made of the silicon film 10 in which no impurity is implanted by the CMP method. Are processed so as to be exposed (FIG. 9A). Here, the first interlayer insulating film 26 can be made of an SiN film as an etching stopper and a silicon oxide film having a low dielectric constant.

  Next, the gate electrode made of the N-type silicon film 10a is masked with a resist 27, and the surface of the dummy gate electrode is receded by reactive ion etching, as shown in FIG. 9B. Thereby, the film thickness of the silicon film in the dummy gate electrode portion is reduced. At this time, the silicon oxide film 15 formed on the side wall also recedes in the same manner, but the silicon oxide film 15 may remain on the side wall portion by adjusting the etching conditions.

  Next, after removing the resist 27, a nickel film (not shown) and a titanium nitride film (not shown) are deposited on the entire surface. Subsequently, heat treatment is performed to form nickel silicide 28 as a second metal silicide film on the gate electrode portion, and then titanium nitride and unreacted nickel are removed by etching (FIG. 9C). At this time, the nickel film has a thickness equal to or greater than 54% of the thickness of the dummy gate electrode and is smaller than 54% of the thickness of the gate electrode made of the N-type silicon film 10a. To be. By doing so, the portion in contact with the hafnium silicate nitride film 9 becomes the N-type silicon film 10a in the NMOSFET and the nickel silicide film 28 in the PMOSFET. In other words, the dummy gate electrode made of the silicon film 10 changes to the gate electrode made of the nickel silicide film 28 through the above-described steps.

FIG. 10 shows the relationship between the composition ratio (Ni / Si) of nickel and silicon in the nickel silicide film and the flat band voltage (V _fb ) in this embodiment compared with the conventional example using a polysilicon electrode. It is. As can be seen from the figure, in the PMOSFET, when the proportion of nickel increases, V _fb shifts to the positive side with respect to the conventional example. As a result, the threshold voltage is also shifted to the positive side, so that the drive voltage is reduced and the power consumption is reduced. From FIG. 10, it is preferable that the value of Ni / Si is 1.01-1.40, and it is more preferable that it is 1.13-1.40.

  Note that the silicidation speed is increased on the silicon film into which P as an N-type impurity is implanted. Therefore, the nickel silicide film 28 is formed thicker in the N-type gate electrode portion than in the P-type gate electrode portion. However, in the present embodiment, the silicon film 10 is formed so that the thickness of the silicon film 10 is about 2 to 3 times the thickness of the nickel silicide film 28. Therefore, the portion in contact with the hafnium silicate nitride film 9 is formed. The nickel silicide film 28 can be formed in the state of the N-type silicon film 10a.

  In addition, according to the present embodiment, the N-type impurity is diffused inside the N-type silicon film 10a by the heat treatment when forming the nickel silicide film 28, so that depletion of the gate electrode is suppressed and the inversion capacitance is increased. Thus, the on-current can be increased. In addition to P, As (arsenic) can be used as the N-type impurity, but P having a higher diffusion rate is more effective for activating the silicon film.

  Further, conventionally, the step of forming the nickel silicide on the surface of the silicon electrode is the same as the step of forming nickel silicide on the source / drain diffusion regions. In this case, the thickness of the nickel silicide is reduced in order to suppress junction leakage, so that the resistance of the gate electrode is increased. On the other hand, according to the present embodiment, since a thick nickel silicide film can be formed on the gate electrode, the resistance of the gate electrode can be reduced by an order of magnitude compared to the conventional case in both the NMOSFET and the PMOSFET.

  When the gate length is shorter than the expected nickel film thickness (for example, 37 nm or less), the nickel film thickness in the P-type gate electrode portion recedes from the first interlayer insulating film 26. The depth to the surface of the silicon film 10 can be considered. For example, the thickness of the silicon film 10 after the receding is set to 80 nm, and the thickness of the receding from the surface of the first interlayer insulating film 26 is set to 20 nm. If the thickness of the nickel film in the N-type gate electrode portion is 50 nm, the thickness of the nickel film in the P-type gate electrode portion is apparently 90 nm. Therefore, all the P-type gate electrodes after silicidation are made of nickel silicide 28, while the N-type gate electrode has a two-layer structure in which the lower layer remains N-type silicon and the upper layer is nickel silicide 28. However, in this case, care must be taken because the P-type transistor having a long gate length measured as a performance test may be the nickel silicide film 28 only in the upper part.

  Next, after depositing the second interlayer insulating film 29 by a CVD method or a coating method, the surface is flattened by using a CMP method. Thereby, the structure shown in FIG. 1 is obtained. After planarization, contact and wiring are formed.

  In the present embodiment, the recessed portion of the P-type gate electrode may be filled with an appropriate metal film in order to align the position of the surface of each gate electrode in the NMOSFET and the PMOSFET. For example, after the step shown in FIG. 9C, a titanium nitride film 30 and a tungsten film 31 are formed in this order, and these films are removed by the CMP method except for the depressions. Thereafter, when a second interlayer insulating film 29 is deposited and planarized by the CMP method, the structure shown in FIG. 2 is obtained.

  Further, after the step shown in FIG. 9C, the titanium nitride film 30 and the tungsten film 31 may be formed in order and processed by reactive ion etching or the like using a mask or the like. After that, when a second interlayer insulating film 29 is deposited and planarized by the CMP method, the structure shown in FIG. 3 is obtained.

  In this embodiment, tetra-t-butoxyhafnium is used as the organic metal material when forming the metal silicate film. However, the same is applicable as long as the organic metal material contains elements of hafnium and zirconium. Can be implemented.

According to this embodiment, in the NMOSFET, the N ⁺ silicon film is in contact with the high dielectric constant insulating film, and in the PMOSFET, the nickel silicide film is in contact with the high dielectric constant insulating film. Therefore, the threshold voltages of the NMOSFET and the PMOSFET can be optimized by using channel ion implantation together, and the inversion capacitance can be increased.

  In addition, according to the present embodiment, since the high dielectric constant insulating film is formed before the gate electrode in the manufacturing process, there is no restriction such as setting the heat treatment temperature in consideration of the heat resistance of the silicide, which is desired. Heat treatment can be performed at a temperature of Therefore, a high quality gate insulating film can be obtained.

Further, according to the present embodiment, it is possible to activate the N ⁺ silicon film and the source / drain diffusion layer used for the N-type gate electrode before the formation of the gate electrode. Furthermore, if all the silicon film constituting the dummy gate electrode is removed by etching to form the P-type gate electrode, the underlying gate insulating film may be damaged or the gate insulating film may be etched together. There is. On the other hand, according to the present embodiment, since the nickel silicide film is formed with the silicon film remaining on the gate insulating film without etching all the silicon film, the gate insulating film is damaged or etched. The problem of disappearing can be solved.

  Further, according to the present embodiment, the hafnium silicon nitride film as the high dielectric constant gate insulating film is not on the side wall portion of the gate electrode, but only on the lower portion of the gate electrode. In general, when a high dielectric constant insulating film is used as a gate insulating film, the off-current increases when the high dielectric constant insulating film is longer than the length of the gate electrode (gate length), whereas it is the same length as the gate length. On the other hand, when it is a little short, the off-current becomes small. In a conventional manufacturing method using a metal gate electrode, all of the silicon film constituting the dummy gate electrode is removed by etching, and the sacrificial oxide film is also removed by etching. Was formed on the entire surface. For this reason, as shown in FIG. 9B, the high dielectric constant insulating film is always longer than the gate length by the double film thickness of the high dielectric constant insulating film. On the other hand, according to the present embodiment, as shown in FIG. 6B, etching is performed so that the high dielectric constant insulating film remains only under the gate electrode or slightly shorter than the gate length. Therefore, the off current can be sufficiently suppressed.

  FIG. 11 compares the effective mobility of the PMOSFET according to the present embodiment with that of the conventional example. From the figure, it can be seen that the mobility of the present embodiment is improved over the conventional example. This is because the concentration of B (boron) in the polysilicon electrode is low in this embodiment. That is, in the conventional polysilicon electrode, the mobility is lowered when B penetrates to the substrate. On the other hand, in this embodiment, since the concentration of B is low, the penetration of B into the substrate does not occur, and as a result, the mobility can be improved as compared with the conventional case.

FIG. 12 compares the on-current-off-current characteristics of the PMOSFET according to this embodiment with the conventional example. As can be seen from the figure, according to the present embodiment, a higher on-current can be obtained than in the conventional example. For _example, I off = time of 20 pA / [mu] m, according to this embodiment is _I on = _150μA / μm, comprising conventional _(I on = _106μA / μm) than about 40% higher.

Embodiment 2. FIG.
FIG. 13 is an example of a cross-sectional view of the semiconductor device in this embodiment.

  As shown in FIG. 5, an element isolation insulating film 102 is formed around the element region of the silicon substrate 101. In the element region, an N type diffusion layer region 106, a P type diffusion layer region 107, a P type extension region 1018, an N type extension region 1019, a P type source / drain region 1023, an N type source / drain region 1024, and A nickel silicide film 1025 is formed.

  The gate insulating film formed on the channel includes a first insulating film and a second insulating film formed on the first insulating film. Here, the first insulating film is a silicon oxynitride film 108a as a base interface layer. On the other hand, the second insulating film is a hafnium silicate film 109a as a high dielectric constant insulating film.

  The N-type gate electrode includes an N-type silicon film 1010a and a titanium silicide film 1032 formed thereon. On the other hand, the P-type gate electrode comprises a ruthenium film 1034 and a titanium silicide film 1032 formed thereon. Further, although the silicon oxide film 1015 and the silicon nitride film 1020 are formed on the gate sidewall, the hafnium silicate film 109a is not formed on the sidewall.

  FIG. 14 shows another example of the semiconductor device in this embodiment. FIG. 14 differs from FIG. 13 in that a titanium nitride film 1030 and a tungsten film 1031 are formed instead of the titanium silicide film 1032 of FIG.

  This embodiment is characterized in that the gate electrode material in contact with the gate insulating film is an N-type silicon electrode for an N-type gate electrode and ruthenium for a P-type gate electrode. Further, the second feature is that the hafnium silicate film 109a is not on the side wall portion of the gate electrode in both the N-type and P-type, but only on the lower portion of the gate electrode.

  In the example of FIGS. 13 and 14, a hafnium silicate nitride film is used as the high dielectric constant insulating film, but the present invention is not limited to this. For example, a zirconium oxynitride film or the like may be used as the high dielectric constant insulating film, a hafnium silicate film (not containing nitrogen) or a zirconium silicate film, or the like (not containing silicon). A hafnium oxide film or a zirconium oxide film may be used. The high dielectric constant insulating film may be made of a material containing both elements of hafnium and zirconium.

  In the above example, the silicon oxynitride film 108a is used as the underlying interface layer, but the present invention is not limited to this. As the underlying interface layer, a silicon oxide film or a silicon nitride film may be used instead of the silicon oxynitride film.

  Furthermore, in this embodiment, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like may be formed on the high dielectric constant insulating film.

  Next, with reference to FIGS. 15 to 17, a method for manufacturing the semiconductor device according to the present embodiment will be described. In these drawings, the same reference numerals indicate the same parts.

  In this embodiment mode, after the first interlayer insulating film 1026 is formed, the processes until the surface of the N-type silicon film 1010a and the silicon film 1010 into which impurities are not implanted are exposed by the CMP method are as follows: Since it can be formed in a manner similar to that of Embodiment Mode 1, description thereof is omitted. However, it differs from Embodiment 1 in that the silicon oxynitride film 108a and the hafnium silicate film 109a are used as the gate insulating film.

  First, after the processing of FIG. 15A is completed, a titanium film (not shown) and a titanium nitride film (not shown) as the first metal film are deposited on the entire surface. Next, heat treatment is performed at a temperature of 540 ° C. for 1 hour to remove the unreacted titanium nitride film and the titanium film, whereby the surface of the N-type silicon film 1010a and the silicon film 1010 into which no impurities are implanted Then, a titanium silicide film 1032 as a second metal silicide film is formed (FIG. 15B).

  In addition, according to the present embodiment, the N-type impurity moves into the N-type silicon film 1010a by the heat treatment when forming the titanium silicide film 1032, so that depletion of the gate electrode is suppressed and the inversion capacitance is increased. Thus, the on-current can be increased. In addition to P, As (arsenic) can be used as the N-type impurity, but P having a higher diffusion rate is more effective for activating the silicon film.

  Next, as shown in FIG. 15C, after a silicon nitride film 1033 is deposited on the entire surface, the silicon nitride film 1033 is processed using the resist 1027 as a mask, and silicon nitride as a hard mask is formed in the N-type gate insulating film region. A film 1033 is formed (FIG. 16A).

  Next, the titanium silicide film 1032 on the P-type dummy silicon gate electrode is removed by etching with dilute hydrofluoric acid or the like (FIG. 16B). Thereafter, a ruthenium film 1034 as a second metal film, a titanium film 1035 as a third metal film, and a titanium nitride film 1036 are deposited on the entire surface (FIG. 16C). When heat treatment is performed at a temperature of 540 ° C., the ruthenium film 1034 reacts with the dummy silicon gate electrode 1010 to form ruthenium silicide. The silicon in the formed ruthenium silicide further reacts with the upper titanium film 1035. Thus, titanium silicide is formed.

  The above reaction time differs depending on the film thickness of the silicon film 1010 into which impurities (which constitute a dummy gate electrode) are not implanted. For example, if the titanium film 1035 is more than half the thickness of the silicon film 1010, the ruthenium film 1034 is finally formed on the hafnium silicate film 109a, and titanium as a third metal silicide film is formed. Since the silicide film 1037 is formed thereon, the ruthenium film 1034 and the silicon film 1010 are apparently replaced, and the silicon film 1010 and the titanium film 1035 are reacted. Thereafter, when the titanium nitride film 1036 and the unreacted titanium film 1035 are removed by etching, the structure shown in FIG.

  Thereafter, the ruthenium film 1034 on the first interlayer insulating film 1026 and the hard mask silicon nitride film 1033 is removed by etching with oxygen plasma containing chlorine, and the silicon nitride film 1033 is further formed by reactive ion etching or hot phosphoric acid. Is removed (FIG. 17B). Next, after a second interlayer insulating film 1029 is deposited by a CVD method or a coating method, the surface is planarized by using a CMP method. Thereby, the structure shown in FIG. 13 is obtained. Here, the second interlayer insulating film 1029 can be made of an SiN film as an etching stopper and a silicon oxide film having a low dielectric constant. After planarization, contact and wiring are formed.

  Since the titanium silicide films 1032 and 1037 on the gate electrode formed by the above method are formed at a low temperature, the titanium silicide films 1032 and 1037 are not a low resistance phase C54 phase but a high resistance phase C49 phase. In this case, the titanium silicide films 1032 and 1037 can be formed thick because they are only on both the N-type and P-type gate electrodes. Therefore, no particular problem occurs even if the titanium silicide films 1032 and 1037 are in a high resistance phase. However, when it is desired to form a gate electrode having a lower resistance, the following method may be used.

  First, in the structure of FIG. 17A, the titanium silicide films 1032 and 1037 are removed by etching with dilute hydrofluoric acid or the like (FIG. 17C). Next, after a titanium nitride film 1030 and a tungsten film 1031 are deposited over the entire surface, these films are embedded in the depressions of the N-type and P-type gate electrodes using CMP. After that, when a second interlayer insulating film 1029 is deposited and planarized by CMP, the structure shown in FIG. 14 is obtained.

  Further, after the step shown in FIG. 17C, a titanium nitride film 1030 and a tungsten film 1031 may be formed in order and processed by reactive ion etching or the like using a mask or the like. After that, when a second interlayer insulating film 1029 is deposited and planarized by a CMP method, a structure similar to that shown in FIG.

  The first embodiment is different from the first embodiment in that the thickness of the dummy silicon film 1010 of the P-type gate electrode is reduced by etching away the titanium silicide film 1032 after the titanium silicide film 1032 is formed. It is in thinning. Second, the ruthenium film 1034 is brought into contact with the hafnium silicate film 109a by the silicon replacement method.

  In this embodiment, the recession of the surface of the silicon film 1010 is performed by removing the titanium silicide film 1032 by etching. However, the silicon film 1010 may be directly etched by reactive ion etching. Alternatively, both the removal of the titanium silicide film 1032 and the reactive ion etching of the silicon film 1010 may be used in combination.

  In this embodiment, the silicon film 1010 constituting the dummy gate electrode is replaced with ruthenium. However, the present invention is not limited to this. If the metal element is a diffusing species of silicidation, the process can be similarly performed. Therefore, the process can be similarly performed by using a metal film such as platinum, palladium, nickel, and cobalt instead of ruthenium. However, in the case of using a metal that cannot be easily etched by oxygen-based plasma such as ruthenium, in order to remove the unreacted metal film remaining on the first interlayer insulating film 1026, sputter etching, CMP, or the like is used. It is necessary to use chemical mechanical removal methods.

  In this embodiment, the silicon oxynitride film 108a is used as the base interface layer. However, a silicon oxide film may be used as in the first embodiment, or a silicon nitride film may be used.

  Furthermore, in the present embodiment, the nickel silicide film 1025 is formed on the surface of the source / drain diffusion layer, but other silicides such as cobalt silicide and titanium silicide can also be used.

Embodiment 3 FIG.
18 to 24 are cross-sectional views illustrating configuration examples of the semiconductor device in this embodiment.

  As shown in FIG. 18, an element isolation insulating film 202 is formed around the element region of the silicon substrate 201. In the element region, an N-type diffusion layer region 206, a P-type diffusion layer region 207, a P-type extension region 2018, an N-type extension region 2019, a P-type source / drain region 2023, an N-type source / drain region 2024, and A nickel silicide film 2025 is formed.

  The gate insulating film formed on the channel includes a first insulating film and a second insulating film formed on the first insulating film. Here, the first insulating film is a silicon oxide film 208 as a base interface layer. On the other hand, the second insulating film is a high dielectric constant insulating film, and includes a hafnium oxide film 209b and a silicon nitride film 209c formed thereon.

  The N-type gate electrode includes an N-type silicon film 2010a and a nickel silicide film 2028 formed thereon. On the other hand, the P-type gate electrode is composed of a nickel silicide film 2028 and a titanium silicide film 2037 formed thereon. Further, although the silicon oxide film 2015 and the silicon nitride film 2020 are formed on the gate sidewall, the hafnium oxide film 209b is not formed on the sidewall.

  FIG. 19 differs from FIG. 18 in that the P-type gate electrode is formed of only the nickel silicide film 2028.

  FIG. 20 differs from FIG. 18 in that the nickel film 2038 is in contact with the gate insulating film instead of the nickel silicide film 2028.

  FIG. 21 differs from FIG. 18 in that a nickel silicide film 2028 is formed between the nickel film 2038 and the titanium silicide film 2037.

  22 to 24 are different from FIGS. 18 to 20 in that a titanium nitride film 2030 and a tungsten film 2031 are formed instead of the titanium silicide film 2037 formed on the P-type gate electrode. Is a point. In this case, even if a titanium film is formed under the titanium nitride film 2030, the present invention can be similarly implemented.

  This embodiment is characterized in that the gate electrode material in contact with the gate insulating film is an N-type silicon electrode in the case of an N-type gate electrode, and is a nickel silicide film 2028 or a nickel film 2038 in the case of a P-type gate electrode. And In addition, the second feature is that the hafnium oxide film 209b is not on the side wall portion of the gate electrode in both the N-type and P-type, but only on the lower portion of the gate electrode.

  In the examples shown in FIGS. 18 to 24, the hafnium oxide film is used as the high dielectric constant insulating film, but the present invention is not limited to this. For example, a zirconium oxide film or the like may be used as the high dielectric constant insulating film, a hafnium silicate film (including silicon) or a zirconium silicate film may be used, or hafnium silicate nitriding (including nitrogen). A film or a zirconium silicate nitride film may be used. The high dielectric constant insulating film may be made of a material containing both elements of hafnium and zirconium.

  In the above example, the silicon oxide film 208 is used as the base interface layer, but the present invention is not limited to this. As the base interface layer, a silicon oxynitride film or a silicon nitride film may be used instead of the silicon oxide film.

  Furthermore, in the above example, the silicon nitride film is formed on the high dielectric constant insulating film, but the present invention is not limited to this. For example, a silicon oxide film or a silicon oxynitride film may be formed on the high dielectric constant insulating film. Further, the high dielectric constant insulating film and the gate electrode material may be in direct contact.

  Next, with reference to FIGS. 25 to 28, a method for manufacturing the semiconductor device according to the present embodiment will be described. In these drawings, the same reference numerals indicate the same parts.

  In this embodiment mode, after the first interlayer insulating film 2026 is formed, a process until the surface of the N-type silicon film 2010a and the silicon film 2010 into which impurities are not implanted is exposed by the CMP method is as follows. Since it can be formed in a manner similar to that of Embodiment Mode 1 or Embodiment Mode 2, description thereof is omitted. However, this embodiment differs from the first and second embodiments in that the silicon oxide film 208, the hafnium oxide film 209b, and the silicon nitride film 209c are used as the gate insulating film. The first interlayer insulating film 2026 can be made of an SiN film as an etching stopper and a low dielectric constant silicon oxide film.

  First, after the processing of FIG. 25A is completed, a nickel film (not shown) and a titanium nitride film (not shown) as the first metal film are deposited on the entire surface. Next, heat treatment is performed to remove the unreacted titanium nitride film and nickel film, thereby forming a second metal silicide film on the surface of the N-type silicon film 2010a and the silicon film 2010 in which no impurity is implanted. A nickel silicide film 2028 is formed (FIG. 25B).

  Note that the silicidation speed is increased on the silicon film into which P as an N-type impurity is implanted. Therefore, the nickel silicide film 2028 is formed thicker in the N-type gate electrode portion than in the P-type gate electrode portion. In this embodiment mode, the silicon film 2010 is formed so that the thickness of the silicon film 2010 is about 2 to 3 times the thickness of the nickel silicide film 2028, so that the portion in contact with the silicon nitride film 209 c is an N-type silicon film. The nickel silicide film 2028 can be formed in the state of 2010a.

  Further, according to the present embodiment, the N-type impurity diffuses inside the N-type silicon film 2010a by the heat treatment when forming the nickel silicide film 2028, so that depletion of the gate electrode is suppressed and the inversion capacitance is increased. Thus, the on-current can be increased. In addition to P, As (arsenic) can be used as the N-type impurity, but P having a higher diffusion rate is more effective for activating the silicon film.

  In FIG. 25A, a nickel silicide film 2025 is formed on the surfaces of the source / drain diffusion layers 2023 and 2024 after the gate sidewall is formed. In the present embodiment, the hard mask (corresponding to the silicon oxide film 13 in FIGS. 6 to 8) used for processing the gate electrode is removed in advance, and the nickel silicide film 2025 is formed on the source / drain diffusion layers 2023 and 2024. At the same time, a nickel silicide film 2028 is also formed on the surface of the gate electrode, and the nickel silicide film 2028 on the surface of the gate electrode is exposed by the formation of the first interlayer insulating film 2026 and the subsequent CMP method. A structure similar to that shown in FIG.

  Next, as shown in FIG. 25C, a silicon nitride film 2033 is deposited on the entire surface, the silicon nitride film 2033 is processed using the resist 2027 as a mask, and the silicon nitride film 2033 is used as a hard mask in the N-type gate insulating film region. (FIG. 26A).

  Next, a titanium film 2035 and a titanium nitride film 2036 as second metal films are deposited on the entire surface (FIG. 26B). Thereafter, when heat treatment is performed at 540 ° C., nickel in the nickel silicide film 2028 diffuses into the silicon film 2010 constituting the dummy gate electrode, and silicon is formed in the titanium film 2035 above the nickel silicide film 2028. A diffusing reaction occurs. The reaction time at this time varies depending on the film thickness of the silicon film 2010. For example, if the titanium film 2035 is half the thickness of the silicon film 2010, the nickel silicide film 2028 is finally formed on the silicon nitride film 209c, and the third metal silicide film is formed. Since the titanium silicide film 2037 is formed thereon, the nickel silicide film 2028 appears to replace the silicon film 2010, and the silicon film 2010 reacts with the upper titanium film 2035. Thereafter, when the titanium nitride film 2036 and the unreacted titanium film 2035 are removed by etching, the structure shown in FIG. 26C is obtained.

  Thereafter, the silicon nitride film 2033 as a hard mask is removed by reactive ion etching or hot phosphoric acid. Next, after a second interlayer insulating film 2029 is deposited by a CVD method or a coating method, the surface is planarized by using a CMP method. Thereby, the structure shown in FIG. 18 is obtained. After planarization, contact and wiring are formed.

  Further, as shown in FIG. 27A, before the silicon film 2010 is replaced with the nickel silicide film 2028, a thick nickel film (first metal film) 2038 and a titanium nitride film 2036 are formed on the entire surface. The P-type gate electrode can be all made of a nickel silicide film (second metal silicide film) 2028. Thereafter, when the titanium nitride film 2036 and the unreacted nickel film 2038 are removed, the result is as shown in FIG. After that, the silicon nitride film 2033 is removed by reactive ion etching or hot phosphoric acid, the second interlayer insulating film 2029 is deposited by the CVD method or the coating method, and planarized by the CMP method, the structure shown in FIG. Become. Thereafter, the formation of contacts, wirings, and the like is performed in the same manner as described above.

  Further, as shown in FIG. 28A, before the nickel silicide film 2028 is replaced with the silicon film 2010, the thickness of the titanium film (second metal film) 2035 formed on the entire surface is sufficiently increased. Heat-treat at 1 ° C. for 1 hour. As a result, the nickel silicide film 2028 replaces the silicon film 2010, and silicon diffuses into the titanium film 2035. Therefore, the nickel film (first metal film) 2038 finally contacts the silicon nitride film 209c. Then, a titanium silicide film (third metal silicide film) 2037 is formed on the nickel film 2038. This structure is obtained when the thickness of the titanium film 2035 is larger than the total thickness of the nickel silicide film 2028 and the silicon film 2010. Thereafter, when the titanium nitride film 2036 and the unreacted titanium film 2035 are removed, a state as shown in FIG.

  Thereafter, the silicon nitride film 2033 is removed by reactive ion etching, hot phosphoric acid, or the like, and a second interlayer insulating film 2029 is deposited by a CVD method or a coating method, and is planarized by the CMP method, whereby the structure shown in FIG. It becomes. Thereafter, the formation of contacts, wirings, and the like is performed in the same manner as described above.

  In the above example, the nickel silicide film 2028 and the nickel film 2038 are in contact with the silicon nitride film 209c. On the other hand, when the thickness of the titanium film 2035 formed on the entire surface is larger than that of the silicon film 2010 and smaller than the total thickness of the nickel silicide film 2028 and the dummy silicon film 2010, FIG. As shown in FIG. 21, a titanium silicide film 2037 is formed on the stacked structure of the nickel film 2038 and the nickel silicide film 2028.

  As in the second embodiment, the titanium silicide films 2032 and 2037 are removed by etching with dilute hydrofluoric acid or the like, and then a titanium nitride film 2030 and a tungsten film 2031 are formed, and a hollow portion of the gate electrode is formed by CMP. Then, these films are embedded, a second interlayer insulating film 2029 is deposited, and planarized by the CMP method, resulting in the structure of FIGS. Here, the embedding in the recess may be performed by forming the titanium nitride film 2030 and the tungsten film 2031 in order and processing these films by reactive ion etching or the like using a mask or the like. After that, when a second interlayer insulating film 2029 is deposited and planarized by the CMP method, a structure similar to that shown in FIG.

  The present embodiment is different from the second embodiment in that the thickness of the silicon film 2010 constituting the dummy P-type gate electrode is not reduced. That is, after the nickel silicide film 2028 is formed on the silicon film 2010 in the same manner as the N-type gate electrode, the nickel silicide film 2028 or the nickel film 2038 is (gate insulating) only in the P-type gate electrode portion by using the silicon replacement method. It is characterized by being formed so as to be in contact with the silicon nitride film 209c (which is a film).

  In this embodiment, the silicon film 2010 constituting the dummy gate electrode is replaced with the nickel silicide film 2028, but the present invention is not limited to this. When the metal element is a diffusing species of silicidation, the same can be performed. Therefore, the same can be performed even when a metal silicide film such as platinum silicide, palladium silicide, and cobalt silicide is used instead of nickel silicide. Can do. However, ruthenium silicide is not suitable because of its high resistance.

  In this embodiment, the silicon oxide film 208 is used as the base interface layer. However, a silicon oxynitride film may be used as in the second embodiment, or a silicon nitride film may be used.

  FIG. 29A shows the result of evaluating the subthreshold characteristics of a transistor having a gate length of 40 nm formed according to the present invention. For comparison, FIG. 29B shows the results of evaluation of Comparative Example 1 using a silicon gate electrode as a conventional example and Comparative Example 2 using a titanium nitride electrode. The measurement was performed on a sample in which a gate insulating film made of a silicon oxide film having a thickness of 0.5 nm and a hafnium silicate nitride film having a thickness of 2 nm was formed on a channel not subjected to impurity ion implantation for adjusting the threshold voltage.

  As shown in FIG. 29 (b), in Comparative Example 1, the threshold voltage of the NMOSFET is relatively small, whereas the threshold voltage of the PMOSFET is largely shifted to the negative side. In Comparative Example 2, the absolute value of the threshold voltage of the PMOSFET is a relatively small value, whereas the threshold voltage of the NMOSFET is shifted to the positive side.

  On the other hand, as can be seen from FIG. 29 (a), in the present invention, the NMOSFET using the N-type silicon electrode is the same as that in the comparative example 1, but the PMOSFET shows a contrasting shape with the NMOSFET. Here, when the type of material used for the gate electrode is changed, the threshold voltage value slightly changes. However, the amount of change is in a range that can be sufficiently adjusted by the dose of the channel.

  Further, FIG. 29A shows that the current value of the PMOSFET is a sufficiently large value in the present invention as compared with Comparative Example 1. This indicates that the present invention makes it possible to suppress depletion of the gate electrode as well as to optimize the threshold voltage of the PMOSFET.

  From the above results, it was found that the present invention is very effective when a high dielectric constant insulating film is used as a gate insulating film. The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

3 is an example of a cross-sectional view of the semiconductor device in Embodiment 1. FIG. 3 is an example of a cross-sectional view of the semiconductor device in Embodiment 1. FIG. 3 is an example of a cross-sectional view of the semiconductor device in Embodiment 1. FIG. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 1. FIGS. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 1. FIGS. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 1. FIGS. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 1. FIGS. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 1. FIGS. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 1. FIGS. In Embodiment 1, it is a figure which shows the relationship between (Ni / Si) ratio in a nickel silicide film | membrane, and _Vfb . FIG. 3 is a diagram showing an effective mobility of the PMOSFET according to the first embodiment. It is a figure which shows the on-current-off-current characteristic of PMOSFET by Embodiment 1. FIG. FIG. 3 is an example of a cross-sectional view of a semiconductor device in a second embodiment. FIG. 3 is an example of a cross-sectional view of a semiconductor device in a second embodiment. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 2. FIG. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 2. FIG. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 2. FIG. 10 is an example of a cross-sectional view of a semiconductor device in Embodiment 3. FIG. 10 is an example of a cross-sectional view of a semiconductor device in Embodiment 3. FIG. 10 is an example of a cross-sectional view of a semiconductor device in Embodiment 3. FIG. 10 is an example of a cross-sectional view of a semiconductor device in Embodiment 3. FIG. 10 is an example of a cross-sectional view of a semiconductor device in Embodiment 3. FIG. 10 is an example of a cross-sectional view of a semiconductor device in Embodiment 3. FIG. 10 is an example of a cross-sectional view of a semiconductor device in Embodiment 3. FIG. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 3. FIG. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 3. FIG. (A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 3. FIG. (A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 3. FIG. It is the result of evaluating the subthreshold characteristic of a transistor, (a) is this invention, (b) is a comparative example. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by a conventional method. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by a conventional method. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by a conventional method. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by a conventional method. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by a conventional method. It is sectional drawing which shows the manufacturing method of the semiconductor device by a conventional method. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by a conventional method. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by a conventional method. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device by a conventional method. It is sectional drawing which shows the manufacturing method of the semiconductor device by a conventional method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation insulating film 6 N type diffused layer area | region 7 P type diffused layer area | region 8 Silicon oxide film 9 Hafnium silicate nitride film 10a N type silicon film 15 Silicon oxide film 18 P type extension area | region 19 N type extension area | region 20 Silicon Nitride film 23 P-type source / drain region 24 N-type source / drain region 25, 28 Nickel silicide film 26 First interlayer insulating film 29 Second interlayer insulating film 101 Silicon substrate 102 Element isolation insulating film 106 N-type diffusion layer region 107 P-type diffusion layer region 108a Silicon oxynitride film 109a Hafnium silicate oxide film 1010a N-type silicon film 1015 Silicon oxide film 1018 P-type extension region 1019 N-type extension region 1020 Silicon nitride film 1023 P-type source / drain region 1024 N-type source / drain region 1025 Nickel silicide film 1026 First interlayer insulating film 1029 Second interlayer insulating film 1032, 1037 Titanium silicide film 1034 Ruthenium film 201 Silicon substrate 202 Element isolation insulating film 206 N-type diffusion layer area 207 P Type diffusion layer region 208 Silicon oxide film 209b Hafnium oxide film 209c Silicon nitride film 2010a N-type silicon film 2015 Silicon oxide film

Claims (10)

In a semiconductor device comprising a CMOSFET composed of an NMOSFET and a PMOSFET on a silicon substrate,
The gate insulating films of the NMOSFET and the PMOSFET have a laminated structure including a first insulating film formed on the silicon substrate and a second insulating film formed on the first insulating film. ,
The gate electrode of the NMOSFET comprises an N-type silicon film formed on the gate insulating film and a first metal silicide film formed on the N-type silicon film,
The gate electrode of the PMOSFET is composed of a second metal silicide film formed on the gate insulating film,
The second insulating film is a high dielectric constant insulating film, and the high dielectric constant insulating film is not formed on any side wall of the gate electrode of the NMOSFET or the gate electrode of the PMOSFET. Semiconductor device. In a semiconductor device comprising a CMOSFET composed of an NMOSFET and a PMOSFET on a silicon substrate,
The gate insulating films of the NMOSFET and the PMOSFET have a laminated structure including a first insulating film formed on the silicon substrate and a second insulating film formed on the first insulating film. ,
The gate electrode of the NMOSFET comprises an N-type silicon film formed on the gate insulating film and a first metal silicide film formed on the N-type silicon film,
The gate electrode of the PMOSFET has a stacked structure of a metal film formed on the gate insulating film and a second metal silicide film formed on the metal film,
The second insulating film is a high dielectric constant insulating film, and the high dielectric constant insulating film is not formed on any side wall of the gate electrode of the NMOSFET or the gate electrode of the PMOSFET. Semiconductor device.   The semiconductor device according to claim 2, wherein the metal film includes at least one metal selected from the group consisting of nickel, cobalt, palladium, rhodium, ruthenium, platinum, and iridium.   The first metal silicide film is a single-layer film selected from the group consisting of a nickel silicide film, a cobalt silicide film, a palladium silicide film, a rhodium silicide film, a ruthenium silicide film, a platinum silicide film, and an iridium silicide film, The semiconductor device according to claim 1, wherein the semiconductor device is a laminated film composed of two or more films.   The second metal silicide film is a single-layer film selected from the group consisting of a nickel silicide film, a cobalt silicide film, a palladium silicide film, a rhodium silicide film, a ruthenium silicide film, a platinum silicide film, and an iridium silicide film. The semiconductor device according to claim 1, wherein the semiconductor device is a laminated film composed of two or more films. In a method for manufacturing a semiconductor device including a CMOSFET composed of an NMOSFET and a PMOSFET,
Forming a gate insulating film including a high dielectric constant insulating film on a silicon substrate provided with an element isolation insulating film, an N-type diffusion layer region, and a P-type diffusion layer region;
Forming a silicon film on the gate insulating film;
Implanting N-type impurities into the NMOSFET region of the silicon film;
Processing the silicon film into the shape of a gate electrode to form an N-type silicon film pattern and an undoped silicon film pattern;
Removing the gate insulating film except under the N-type silicon film pattern and the undoped silicon film pattern;
Forming a first sidewall insulating film on the entire surface of the silicon substrate after removing the gate insulating film;
Implanting impurities into the silicon substrate using the N-type silicon film pattern and the undoped silicon film pattern as a mask to form an N-type extension region and a P-type extension region;
Forming a second sidewall insulating film on the first sidewall insulating film;
Removing the first sidewall insulating film and the second sidewall insulating film except for the sidewall portions of the N-type silicon film pattern and the undoped silicon film pattern;
Impurities are implanted into the silicon substrate using the N-type silicon film pattern and the undoped silicon film pattern in which the first sidewall insulating film and the second sidewall insulating film are formed on the sidewall portions as masks, and an N-type source A step of forming a drain region and a P-type source / drain region;
Forming a first metal silicide film on the N-type source / drain region and the P-type source / drain region;
Forming an interlayer insulating film on the silicon substrate after the formation of the first metal silicide film so as to embed the N-type silicon film pattern and the undoped silicon film pattern;
Processing the interlayer insulating film to expose the surfaces of the N-type silicon film pattern and the undoped silicon film pattern;
Etching the undoped silicon film pattern to a predetermined thickness;
Forming a metal film on the entire surface of the silicon substrate;
A step of changing all of the upper portion of the N-type silicon film pattern and the undoped silicon film pattern into a second metal silicide film in which the metal film is silicided by heat treatment. Production method. In a method for manufacturing a semiconductor device including a CMOSFET composed of an NMOSFET and a PMOSFET,
Forming a gate insulating film including a high dielectric constant insulating film on a silicon substrate provided with an element isolation insulating film, an N-type diffusion layer region, and a P-type diffusion layer region;
Forming a silicon film on the gate insulating film;
Implanting N-type impurities into the NMOSFET region of the silicon film;
Processing the silicon film into the shape of a gate electrode to form an N-type silicon film pattern and an undoped silicon film pattern;
Removing the gate insulating film except under the N-type silicon film pattern and the undoped silicon film pattern;
Forming a first sidewall insulating film on the entire surface of the silicon substrate after removing the gate insulating film;
Implanting impurities into the silicon substrate using the N-type silicon film pattern and the undoped silicon film pattern as a mask to form an N-type extension region and a P-type extension region;
Forming a second sidewall insulating film on the first sidewall insulating film;
Removing the first sidewall insulating film and the second sidewall insulating film except for the sidewall portions of the N-type silicon film pattern and the undoped silicon film pattern;
Impurities are implanted into the silicon substrate using the N-type silicon film pattern and the undoped silicon film pattern in which the first sidewall insulating film and the second sidewall insulating film are formed on the sidewall portions as masks, and an N-type source A step of forming a drain region and a P-type source / drain region;
Forming a first metal silicide film on the N-type source / drain region and the P-type source / drain region;
Forming an interlayer insulating film on the silicon substrate after the formation of the first metal silicide film so as to embed the N-type silicon film pattern and the undoped silicon film pattern;
Processing the interlayer insulating film to expose the surfaces of the N-type silicon film pattern and the undoped silicon film pattern;
Forming a first metal film on the entire surface of the silicon substrate;
Changing the upper part of the N-type silicon film pattern and the upper part of the undoped silicon film pattern to a second metal silicide film in which the first metal film is silicided by heat treatment;
Removing the second metal silicide film on the undoped silicon film pattern;
Forming a second metal film and a third metal film in order on the undoped silicon film pattern;
A third metal obtained by reacting the undoped silicon film, the second metal film, and the third metal film by heat treatment to silicide the second metal film and the third metal film. And a step of forming a structure in which a silicide film is sequentially stacked on the gate insulating film. In a method for manufacturing a semiconductor device including a CMOSFET composed of an NMOSFET and a PMOSFET,
Forming a gate insulating film including a high dielectric constant insulating film on a silicon substrate provided with an element isolation insulating film, an N-type diffusion layer region, and a P-type diffusion layer region;
Forming a silicon film on the gate insulating film;
Implanting N-type impurities into the NMOSFET region of the silicon film;
Processing the silicon film into the shape of a gate electrode to form an N-type silicon film pattern and an undoped silicon film pattern;
Removing the gate insulating film except under the N-type silicon film pattern and the undoped silicon film pattern;
Forming a first sidewall insulating film on the entire surface of the silicon substrate after removing the gate insulating film;
Implanting impurities into the silicon substrate using the N-type silicon film pattern and the undoped silicon film pattern as a mask to form an N-type extension region and a P-type extension region;
Forming a second sidewall insulating film on the first sidewall insulating film;
Removing the first sidewall insulating film and the second sidewall insulating film except for the sidewall portions of the N-type silicon film pattern and the undoped silicon film pattern;
Impurities are implanted into the silicon substrate using the N-type silicon film pattern and the undoped silicon film pattern in which the first sidewall insulating film and the second sidewall insulating film are formed on the sidewall portions as masks, and an N-type source A step of forming a drain region and a P-type source / drain region;
Forming a first metal silicide film on the N-type source / drain region and the P-type source / drain region;
Forming an interlayer insulating film on the silicon substrate after the formation of the first metal silicide film so as to embed the N-type silicon film pattern and the undoped silicon film pattern;
Processing the interlayer insulating film to expose the surfaces of the N-type silicon film pattern and the undoped silicon film pattern;
Forming a first metal film on the entire surface of the silicon substrate;
Changing the upper part of the N-type silicon film pattern and the upper part of the undoped silicon film pattern to a second metal silicide film in which the first metal film is silicided by heat treatment;
Forming a second metal film on the second metal silicide film in the region of the PMOSFET;
The undoped silicon film, the second metal silicide film, and the second metal film are reacted by heat treatment to react the second metal silicide film and the second metal film into a silicide. Forming a structure in which the metal silicide films are sequentially stacked on the gate insulating film. In a method for manufacturing a semiconductor device including a CMOSFET composed of an NMOSFET and a PMOSFET,
Forming a gate insulating film including a high dielectric constant insulating film on a silicon substrate provided with an element isolation insulating film, an N-type diffusion layer region, and a P-type diffusion layer region;
Forming a silicon film on the gate insulating film;
Implanting N-type impurities into the NMOSFET region of the silicon film;
Processing the silicon film into the shape of a gate electrode to form an N-type silicon film pattern and an undoped silicon film pattern;
Removing the gate insulating film except under the N-type silicon film pattern and the undoped silicon film pattern;
Forming a first sidewall insulating film on the entire surface of the silicon substrate after removing the gate insulating film;
Implanting impurities into the silicon substrate using the N-type silicon film pattern and the undoped silicon film pattern as a mask to form an N-type extension region and a P-type extension region;
Forming a second sidewall insulating film on the first sidewall insulating film;
Removing the first sidewall insulating film and the second sidewall insulating film except for the sidewall portions of the N-type silicon film pattern and the undoped silicon film pattern;
Impurities are implanted into the silicon substrate using the N-type silicon film pattern and the undoped silicon film pattern in which the first sidewall insulating film and the second sidewall insulating film are formed on the sidewall portions as masks, and an N-type source A step of forming a drain region and a P-type source / drain region;
Forming a first metal silicide film on the N-type source / drain region and the P-type source / drain region;
Forming an interlayer insulating film on the silicon substrate after the formation of the first metal silicide film so as to embed the N-type silicon film pattern and the undoped silicon film pattern;
Processing the interlayer insulating film to expose the surfaces of the N-type silicon film pattern and the undoped silicon film pattern;
Forming a first metal film on the entire surface of the silicon substrate;
Changing the upper part of the N-type silicon film pattern and the upper part of the undoped silicon film pattern to a second metal silicide film in which the first metal film is silicided by heat treatment;
Forming the first metal film on the second metal silicide film in the region of the PMOSFET;
Forming a second metal silicide film on the gate insulating film by reacting the undoped silicon film, the second metal silicide film, and the first metal film by a heat treatment. A method of manufacturing a semiconductor device. In a method for manufacturing a semiconductor device including a CMOSFET composed of an NMOSFET and a PMOSFET,
Forming a gate insulating film including a high dielectric constant insulating film on a silicon substrate provided with an element isolation insulating film, an N-type diffusion layer region, and a P-type diffusion layer region;
Forming a silicon film on the gate insulating film;
Implanting N-type impurities into the NMOSFET region of the silicon film;
Processing the silicon film into the shape of a gate electrode to form an N-type silicon film pattern and an undoped silicon film pattern;
Removing the gate insulating film except under the N-type silicon film pattern and the undoped silicon film pattern;
Forming a first sidewall insulating film on the entire surface of the silicon substrate after removing the gate insulating film;
Implanting impurities into the silicon substrate using the N-type silicon film pattern and the undoped silicon film pattern as a mask to form an N-type extension region and a P-type extension region;
Forming a second sidewall insulating film on the first sidewall insulating film;
Removing the first sidewall insulating film and the second sidewall insulating film except for the sidewall portions of the N-type silicon film pattern and the undoped silicon film pattern;
Impurities are implanted into the silicon substrate using the N-type silicon film pattern and the undoped silicon film pattern in which the first sidewall insulating film and the second sidewall insulating film are formed on the sidewall portions as masks, and an N-type source A step of forming a drain region and a P-type source / drain region;
Forming a first metal silicide film on the N-type source / drain region and the P-type source / drain region;
Forming an interlayer insulating film on the silicon substrate after the formation of the first metal silicide film so as to embed the N-type silicon film pattern and the undoped silicon film pattern;
Processing the interlayer insulating film to expose the surfaces of the N-type silicon film pattern and the undoped silicon film pattern;
Forming a first metal film on the entire surface of the silicon substrate;
Changing the upper part of the N-type silicon film pattern and the upper part of the undoped silicon film pattern to a second metal silicide film in which the first metal film is silicided by heat treatment;
Forming a second metal film on the second metal silicide film in the region of the PMOSFET;
The undoped silicon film, the second metal silicide film, and the second metal film are reacted by heat treatment to react the first metal film and the second metal film into a silicide. And a step of forming a structure in which a metal silicide film is sequentially laminated on the gate insulating film.

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