KR20050010227A - Method for manufacturing semiconductor device with poly-metal gate electrode - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device with a poly metal gate electrode is provided to basically prevent interfacial reaction between a metal layer and a polysilicon layer in a high temperature annealing process by performing a source/drain annealing process before the metal layer is formed. CONSTITUTION: A gate stack in which a gate dielectric layer(32), a polysilicon layer(33), an etch stop layer, a sacrificial layer and a hard mask are sequentially formed is formed on a semiconductor substrate(31). A gate reoxidation process is performed to form a gate reoxidation layer(37) on the sidewall of the polysilicon layer, the etch stop layer and the sacrificial layer. A sidewall spacer(39) is formed on both sidewalls of the gate stack including the gate reoxidation layer. An ion implantation process and an annealing process are performed to form a source/drain region in the semiconductor substrate in the outside the sidewall spacer. An interlayer dielectric(41) is formed on the front surface of the semiconductor substrate. The interlayer dielectric is planarized until the surface of the sacrificial layer among the gate stack is exposed. A part of the sacrificial layer, the etch stop layer and the gate reoxidation layer is selectively removed to form a groove in the upper part of the polysilicon layer. A metal layer(44) for filling the groove is formed on the polysilicon layer.

Description

Method for manufacturing a semiconductor device having a polymetal gate electrode {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH POLY-METAL GATE ELECTRODE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a semiconductor device having a gate electrode capable of implementing stable characteristics in subsequent thermal processes.

Recently, as the design rules of semiconductor devices are rapidly reduced to 90 nm or less, the line widths, gate dielectric film thicknesses, and junction depths of corresponding gate electrodes are also very small. In particular, in view of the gate electrode, there is a need to develop a low resistance gate electrode to solve the RC delay problem.

Accordingly, metal gate electrodes such as tungsten (W), which can replace general polysilicon film gate electrodes, have been introduced. In particular, since it is impossible to implement a thin gate dielectric film required in a high performance device due to the depletion of dopants occurring in a general polysilicon electrode, recently, a metal electrode is directly formed on the gate dielectric film without polysilicon. Direct metal gate electrodes are mainly studied, and direct metal electrodes are known to be essential in devices having an equivalent oxide thickness (EOT) of the gate dielectric layer of 1 nm.

However, in the device having an EOT of 1 nm or more, using polysilicon over the gate dielectric film has various advantages.

Most semiconductor devices require a CMOS process that includes an nMOSFET using an n-type gate electrode and a pMOSFET using a p-type gate electrode. Polysilicon is doped with an n-type gate electrode (work function of about 4.2 eV). ) Or a p-type gate electrode (work function of about 5.2 eV) can be easily formed, making a CMOS device very convenient. However, the metal cannot be arbitrarily controlled as an n-type or p-type material through dopant doping, and thus, the investigation of which metals have n-type properties and which metals have p-type properties is carried out one by one to finally determine the nMOSFET. For example, a dual work function metal gate process using n-type metals and p-type metals for pMOSFETs in a single wafer must be used.

Therefore, the use of a double work function metal gate electrode process is very complicated, and it is very advantageous in terms of process simplification to continue using polysilicon as the gate electrode.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, the gate dielectric film 12, the polysilicon film 13, the tungsten nitride film 14, the tungsten film 15, and the hard mask 16 are stacked on the semiconductor substrate 11 in the order of the following. After the gate stack is formed, the gate electrode is patterned to form a gate electrode. As such, the gate electrode structure in which the tungsten film 15 is formed on the polysilicon film 13 is called a poly-metal gate electrode, and the tungsten nitride film 14 is a polysilicon film 13 and a tungsten film. It acts as a diffusion barrier film to prevent the reaction between (15).

As shown in FIG. 1B, a gate reoxidation process is performed to form a gate reoxidation layer 17, and then a lightly doped drain (LDD) region 18 is formed through ion implantation of a low concentration dopant. . Here, the gate reoxidation process restores microtrench and damage in the gate dielectric layer 12 generated during etching after the gate electrode is etched, and oxidizes the remaining electrode material remaining on the semiconductor substrate 11 and the edge of the gate electrode. In order to improve the reliability by increasing the thickness of the gate dielectric film 12 in the proceeding.

In particular, the gate dielectric film 12 at the edge of the gate electrode has hot carrier characteristics, sub-threshold characteristics, punch-through characteristics, and device operation depending on the thickness and film quality. This will greatly affect the speed, reliability and so on. Therefore, the gate reoxidation process must proceed essentially.

Since the general too easily oxidized not a gate re-oxidation process, the oxidation step proceeding tungsten film 15, the gate electrode is in an oxygen atmosphere, the tungsten film 15 and the tungsten nitride film in a large amount of hydrogen (H ₂ rich) atmosphere ( 14 performs a selective oxidation process in which only the polysilicon film 13 and the semiconductor substrate 11 are oxidized without oxidation.

However, since the selective oxidation process proceeds in the form of Rapid Thermal Oxidation at 850 ° C. to 950 ° C., it is slowly oxidized in a general furnace oxidation process in order to achieve the original purpose of the gate reoxidation process of loss recovery. There are disadvantages compared to the way it is done. In addition, the selective oxidation process has not yet been proven to be a reliable process in terms of mass production. In addition, the selective oxidation process with the polysilicon film is known that only a small number of metal films such as tungsten, WN, Mo, MoN, etc. can be used, and thus, these metals have limitations that cannot be applied to polymetal gate electrodes.

As shown in FIG. 1C, the sidewall spacer 19 and the source / drain 20 process are performed to complete the transistor. Generally, after an ion implantation process for forming the source / drain 20, an annealing heat process for electrically activating the dopant is performed. Typically, a high temperature heat process of 950 ° C to 1000 ° C is required.

On the other hand, another problem that occurs during the selective oxidation process and the source / drain annealing process performed at a high temperature in the prior art is the interfacial reaction between the metal film and the polysilicon film at a high temperature. For example, in a gate electrode composed of a stack of tungsten film / tungsten nitride film / polysilicon film, Si-N, Si-O, etc. are formed by interfacial reaction, and a gate composed of a stack of tungsten film / titanium nitride film / polysilicon film. In the electrode, Ti-O is formed by the interfacial reaction, thereby reducing the circuit speed. In addition, as the metal film and the hard mask repeat thermal expansion / thermal contraction by a high temperature process, the reliability of the gate dielectric film 12 due to mechanical stress occurs.

The present invention has been made to solve the above problems of the prior art, a semiconductor suitable for preventing the deterioration of the characteristics of the gate electrode generated during the selective oxidation process and the source / drain annealing process carried out at a high temperature in the manufacture of the polymetal gate electrode It is an object of the present invention to provide a method for manufacturing a device.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention;

3A to 3C are cross-sectional views illustrating a self-aligned contact process performed after the processes up to FIG. 2H are completed.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 gate dielectric film

33 polysilicon film 37 gate reoxidation film

39: sidewall spacer 40: source / drain region

41: interlayer insulating film 44: metal film

Method of manufacturing a semiconductor device of the present invention for achieving the above object is a step of forming a gate stack stacked in the order of a gate dielectric film, a polysilicon film, an etching barrier film, a sacrificial film and a hard mask on a semiconductor substrate, gate reoxidation Forming a gate reoxidation layer on sidewalls of the polysilicon layer, an etching barrier layer, and a sacrificial layer; forming sidewall spacers on both sidewalls of the gate stack including the gate reoxidation layer; Performing ion implantation and annealing to form source / drain regions in the semiconductor substrate, forming an interlayer insulating film on the entire surface of the semiconductor substrate, and forming the interlayer insulating film until the surface of the sacrificial film is exposed in the gate stack. Planarization of the sacrificial layer, the etching barrier layer and the gate reoxidation layer Selectively removing portions to form grooves on the polysilicon film, and forming a metal film filling the grooves on the polysilicon film, and forming grooves on the polysilicon film. And selectively removing the sacrificial layer using the etch barrier layer as a barrier, and selectively removing a portion of the etch barrier layer and the gate reoxidation layer, wherein the polysilicon layer is formed on the polysilicon layer. In the forming of the grooves, a portion of the sacrificial layer, the etching barrier layer and the gate reoxidation layer may be simultaneously removed in an in-situ manner. Preferably, after forming the metal film filling the groove on the polysilicon film, selectively removing a portion of the metal film and recessing to form a recess groove provided by the sidewall spacer, the recess groove Filling an insulating film in the insulating film, forming a mask layer for self-aligned contact on the insulating film, and forming a contact hole by etching the planarized interlayer insulating film between the gate stacks using the mask layer as an etch mask. Characterized in that.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, a gate dielectric film 32 is formed on the semiconductor substrate 31. Then, after the polysilicon layer 33, the etching barrier layer 34, the sacrificial polysilicon layer 35 and the hard mask 36 are laminated, the hard mask 36 is patterned in the form of a gate electrode, and then patterned. The remaining masks are patterned at once using the hard mask 35 as an etch mask to form a gate stack.

Here, the polysilicon film 33 is formed to have a thickness of 200 kPa to 800 kPa, the etching barrier film 34 is formed to have a thickness of 10 kPa to 100 kPa, and the sacrificial polysilicon film 35 is formed to have a thickness of 500 kPa to 2000 kPa. In addition, the n-type dopant or the p-type dopant is injected into the polysilicon layer 33 through a doping process, as designed.

On the other hand, the etching barrier layer 34 has a selectivity of wet etching or dry etching with respect to the polysilicon layer 33, such as a silicon oxide layer (SiO ₂ ), a silicon nitride layer (Si ₃ N ₄ ), or a nitride oxide layer (Si-ON). It is a film having a. The etching barrier film 34 may use any film having a selectivity with respect to the polysilicon film 33.

Here, in the case of using the silicon oxide film as the etching barrier film 34, the following two methods are used. First, the polysilicon film 33, the silicon oxide film and the sacrificial polysilicon film 35 are deposited in an in-situ method in the polysilicon film 33 deposition process. That is, the polysilicon film 33 is deposited and thermally oxidized in an oxygen atmosphere to form a silicon oxide film, and then the sacrificial polysilicon film 35 is deposited. Second, the silicon oxide film may be formed by chemical vapor deposition (CVD) after the polysilicon film 33 is deposited.

As shown in FIG. 2B, a gate reoxidation film 37 is formed by performing a gate reoxidation process. In this case, since there is no metal film in the gate stack, the gate reoxidation process may be performed by a conventional furnace thermal oxidation method, and the gate reoxidation film 37 may include the polysilicon film 33, the etching barrier film 34, and the sacrificial polysilicon. It is formed on the sidewall of the film 35 to a thickness of 10 to 100 Å.

As shown in FIG. 2C, the LDD region 38 is formed by performing low concentration ion implantation in the state where the gate reoxidation film 37 is formed. Then, after forming sidewall spacers 39 on both sidewalls of the gate stack, ion implantation and annealing processes for forming the source / drain regions 40 are performed.

The sidewall spacers 39 may be formed of a nitride film (SiN) alone or a combination of an oxide film and a nitride film, and a nitride film is preferably used as the final deposition material of the spacer for a subsequent self-aligned contact process. Meanwhile, when the sidewall spacers 39 are formed, the gate reoxidation layer 37 is also partially etched to remain in the form of an L-shaped sidewall spacer. The sidewall spacers 39 may be referred to as dome-shaped spacers.

And the annealing process of the source / drain area | region 40 is accompanied by the high temperature thermal process of 950 degreeC-1000 degreeC.

Next, an interlayer insulating film 41 is deposited on the entire surface of the semiconductor substrate 31.

As shown in FIG. 2D, the interlayer dielectric layer 41 is chemically mechanically polished (CMP) to planarize until the surface of the sacrificial polysilicon layer 35 of the gate stack is exposed. At this time, the planarized interlayer insulating film 41 remains only between the gate stacks, and the hard mask 36 is removed because polishing is performed until the surface of the sacrificial polysilicon film 35 is exposed.

As shown in FIG. 2E, the sacrificial polysilicon layer 35 is selectively removed through a wet etching process or a dry etching process. At this time, since the etching barrier film 34 serves as an etch stop, the polysilicon film 33 is not etched, so that the overall characteristics of the device are maintained accurately and uniformly throughout the wafer without loss of the predetermined thickness of the polysilicon film 33. Can be implemented uniformly.

After removing the sacrificial polysilicon layer 35 as described above, a first groove 42 provided by the sidewall spacer 39 and the gate reoxidation layer 37 is formed on the etching barrier layer 34.

As shown in FIG. 2F, a portion of the etching barrier layer 34 and the gate reoxidation layer 37 are selectively removed through a wet etching process or a dry etching process. In this case, the etching process and the in-situ process of FIG.

After the etching process as described above, the second groove 43 provided by the sidewall spacer 39 is formed on the polysilicon layer 33. Here, the second groove 43 is wider than the first groove 42.

As shown in FIG. 2G, the metal film 44 is deposited on the entire surface until the second groove 43 is filled. At this time, the metal film 44 includes a metal electrode such as a tungsten film and WN, TiN, TaN serving as a diffusion barrier film between the polysilicon film 33 and the metal electrode.

Here, since the gate reoxidation process is performed in advance as shown in FIG. 2B before the deposition of the metal film 44, the application of the metal film 44 is not limited.

As shown in FIG. 2H, the metal film 44 is chemically mechanically polished until the surface of the interlayer insulating film 41 is exposed to leave the metal film 44 only in the second groove 43.

Through the chemical mechanical polishing of the metal film 44, a polymetal gate electrode laminated in the order of the polysilicon film 33 and the metal film 44 is completed.

According to the above-described embodiment, the gate reoxidation process is performed in a general furnace thermal oxidation method instead of the gate reoxidation process performed by the selective oxidation process, and the gate reoxidation process is performed before the deposition of the metal film 44. The metal film may be applied as a gate electrode without limiting the metal film to be applied.

In addition, the annealing process for forming the source / drain region 40 which proceeds at a high temperature is performed before the metal film 44 is formed, so that the metal film 44 generated during the annealing process of the source / drain region 40 and The interfacial reaction between the polysilicon films 33 does not occur fundamentally.

In addition, since the hard mask itself is not introduced, the present invention does not deteriorate the reliability of the gate dielectric film due to mechanical stress caused by repeated thermal expansion / thermal contraction of the metal film and the hard mask by the high temperature thermal process.

On the other hand, the present invention may be difficult to etch subsequent self-aligned contact (SAC) because it does not introduce a hard mask, this can be solved by proceeding in accordance with the accompanying drawings, Figures 3a-3c.

3A to 3C are cross-sectional views illustrating a self-aligned contact process performed after the processes up to FIG. 2H are completed.

As shown in FIG. 3A, a portion of the metal film 44 is recessed by dry etching or wet etching to form a recess groove provided by the sidewall spacer 39, and then the metal film 44. The insulating film 45 is deposited on the entire surface until the recess groove on the top is filled.

At this time, the insulating film 45 is preferably made of the same material as the sidewall spacer 39 for a reliable self-aligned contact process, mainly using a nitride film.

As shown in FIG. 3B, the insulating film 45 is chemically mechanically polished to remain only in the recess grooves on the metal film 44. As shown in FIG.

As shown in FIG. 3C, after forming a contact mask 46 by performing a photo and etching process for self-aligned contact etching, the interlayer insulating layer 41 between the gate stacks is etched with the contact mask 46 to contact the contacts. The hole 47 is formed. Since the insulating film 45 made of a nitride film exists on the metal film 44 at the time of etching for forming the contact hole 47, the same effect as in the case of applying a hard mask is obtained.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Since the gate reoxidation process is performed before the metal film constituting the gate electrode is deposited, the present invention has the effect that all metal films can be applied to the gate electrode without limiting the metal film to be applied as the metal electrode.

In addition, since the present invention performs the source / drain annealing process that proceeds at a high temperature before forming the metal film, an interface reaction between the metal film and the polysilicon film generated during the high temperature annealing process can be essentially avoided, thereby increasing the circuit speed. It works.

In addition, the present invention has an effect of improving the reliability of the gate dielectric film because a hard mask that causes mechanical stress applied to the gate dielectric film is not included in the gate electrode structure.

Claims (13)

Forming a gate stack stacked on the semiconductor substrate in the order of a gate dielectric film, a polysilicon film, an etching barrier film, a sacrificial film, and a hard mask; Forming a gate reoxidation layer on sidewalls of the polysilicon layer, an etching barrier layer and a sacrificial layer by performing a gate reoxidation process; Forming sidewall spacers on both sidewalls of the gate stack including the gate rework film; Performing ion implantation and annealing to form source / drain regions in the semiconductor substrate outside the sidewall spacers; Forming an interlayer insulating film on the entire surface of the semiconductor substrate; Planarizing the interlayer insulating film until the surface of the sacrificial film is exposed in the gate stack; Selectively removing a portion of the sacrificial layer, the etching barrier layer, and the gate reoxidation layer to form a groove on the polysilicon layer; And Forming a metal film filling the groove on the polysilicon film Method for manufacturing a semiconductor device comprising a. The method of claim 1, The sacrificial film, A method for manufacturing a semiconductor device, characterized in that formed from the polysilicon film. The method of claim 1, The etching barrier film, And forming a film having a selectivity with respect to the polysilicon film. The method of claim 3, The etching barrier film, A method of manufacturing a semiconductor device, characterized in that it is formed of a silicon oxide film, a silicon nitride film, or a nitriding film. The method of claim 4, wherein The silicon oxide film is a method of manufacturing a semiconductor device, characterized in that formed by depositing the polysilicon film in an in-situ method in the deposition process of the polysilicon film and thermal oxidation in an oxygen atmosphere. The method of claim 4, wherein The silicon oxide film is a method of manufacturing a semiconductor device, characterized in that formed after the deposition of the polysilicon film by chemical vapor deposition. The method of claim 1, Forming a groove on the polysilicon film, Selectively removing the sacrificial layer using the etching barrier layer as a barrier; And Selectively removing a portion of the etching barrier layer and the gate reoxidation layer Method of manufacturing a semiconductor device comprising a. The method of claim 1, Forming a groove on the polysilicon film, And removing a portion of the sacrificial layer, the etching barrier layer, and the gate reoxidation layer simultaneously in an in-situ manner. The method according to claim 7 or 8, Forming the grooves, A method of manufacturing a semiconductor device, characterized in that it proceeds by wet etching or dry etching. The method of claim 1, Forming the metal film filling the grooves, Depositing the metal film on the entire surface of the semiconductor substrate until the groove is filled; And Chemical mechanical polishing the metal film to leave the metal film only in the groove; Method of manufacturing a semiconductor device comprising a. The method of claim 1, After forming a metal film filling the groove on the polysilicon film, Selectively removing a portion of the metal film to recess to form a recess groove provided by the sidewall spacer; Filling an insulating film in the recess groove; Forming a mask layer for self-aligned contact on the insulating film; Forming a contact hole by etching the planarized interlayer insulating film between the gate stacks using the mask layer as an etch mask Method of manufacturing a semiconductor device further comprising. The method of claim 11, The insulating film and the sidewall spacers, It is formed by a nitride film. The manufacturing method of the semiconductor element characterized by the above-mentioned. The method of claim 11, The recess groove, And forming a portion of the metal film by dry etching or wet etching.