JP3425043B2 - Method for manufacturing MIS type semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS type semiconductor device constructed by introducing impurities into a gate electrode and source / drain regions at the same time.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have been required to have higher performance such as higher integration, higher speed, and lower power consumption due to higher performance of electronic devices such as computers. Most of these semiconductor integrated circuits are MOS (Metal Oxide)
n Semiconductor) type transistor.

Hereinafter, the above-mentioned conventional M will be described with reference to the drawings.
An example of the OS type semiconductor device will be described.

11A to 11C are cross-sectional views showing a manufacturing process of a conventional complementary MOS (CMOS) semiconductor device (FET).

First, as shown in FIG. 11A, a p-type semiconductor region 2a (a region having the same impurity concentration as that of the p-type semiconductor substrate 1 in this conventional example), which is an n-channel MOS transistor forming region, is formed. A p-type semiconductor substrate 1 in which an n-type semiconductor region 2b (n-well) that is a channel-type MOS transistor formation region and an element isolation region 3 that isolates the p-type semiconductor region 2a and the n-type semiconductor region 2b are formed. above,
The gate oxide film 4 having a thickness of 4 to 8 nm and the thickness of 100 to
A 200 nm gate electrode 15 is formed.

Next, as shown in FIG. 11B, arsenic ions () are formed in the gate electrode 15 of the n-channel MOS transistor and the regions 18 located on both sides of the gate electrode 15 in the p-type semiconductor region 2a. As ⁺ ). The implantation conditions are, for example, an acceleration energy of 30 to 60 KeV and an implantation amount of 6 to 8 × 10 ¹⁵ cm ⁻² . On the other hand, p-channel type M
Boron fluoride ions (BF ₂ ⁺ ) are implanted into the gate electrode 15 of the OS transistor and the regions 19 located on both sides of the gate electrode 15 in the n-type semiconductor region 2b. The implantation conditions are, for example, an acceleration energy of 10 to 30 KeV and an implantation amount of 3 to 6 × 10 ¹⁵ cm ⁻² .

Finally, in the step shown in FIG.
Heat treatment (RTA) is performed at 00 ° C. for 10 seconds to activate the impurity ions. By this heat treatment, n-channel MO
In the S transistor formation region, the resistance of the gate electrode 15 is reduced to form the n-type gate electrode 15a, and the n-type source / drain region 18a is formed in the p-type semiconductor region 2a, while in the p-channel MOS transistor formation region. , P-type gate electrode 1 by reducing the resistance of the gate electrode 15
5b, and p-type source / drain regions 19a are formed in the n-type semiconductor region 2b.

[0008]

However, the above-mentioned conventional n-channel MOS transistor formed by simultaneously implanting impurities into the gate electrode and the source / drain regions has the following problems.

Problem (1) N-channel MOS transistor drain region 18a
In, the leakage current at the junction is large due to the crystal defects formed by the implantation of arsenic ions.

Problem (2) N-channel MOS transistor drain region 18a
At GIDL (Gate Induced
Drain Leakage) The current is large.

Problem (3) N-channel MOS transistor drain region 18a
At, since the profile is steep, the parasitic capacitance of the junction becomes large.

Problem (4) N-channel MOS transistor drain region 18a
The electric field in the vicinity is large, and the carriers easily cause impact ionization. As a result, the drain current of the MOS type transistor is reduced, and the threshold value of the MOS type transistor is greatly changed. That is, the reliability is low.

Further, the following problems (5) and (6) occur in the CMOS type transistor.

Problem (5) Due to the difference between the diffusion coefficient of arsenic and the diffusion coefficient of boron, the effective channel length of the p-channel type MOS transistor becomes too shorter than the effective channel length of the n-channel type MOS transistor. The transistor balance deteriorates.

Problem (6) The depletion of the gate electrode 15a of the n-channel MOS transistor and the penetration of boron ions into the gate electrode 15b of the p-channel MOS transistor cannot be suppressed at the same time. That is, a short time heat treatment such as RTA (for example, 1
(000 ° C., 10 seconds), the activation of arsenic ions in the gate electrode 15a of the n-channel MOS transistor is insufficient and depletion occurs, which may reduce the driving force. On the other hand, long-term heat treatment (eg 900 ° C, 30
If this is done, the boron ions in the gate electrode 15b of the p-channel MOS transistor may diffuse into the channel region and deteriorate the characteristics of the device.

The present invention has been made in view of the above problems, and an object thereof is to form an MIS formed by implanting impurity ions into a gate electrode and a source / drain region at the same time.
Type transistor, it is intended to improve the operating speed by reducing the parasitic capacitance, reduce the leak current, and improve the reliability.

[0017]

In order to achieve the above object, the means taken by the present invention is to form a channel adjusting sidewall on both side surfaces of a gate electrode in advance, and then to form the gate electrode and the source / drain. The purpose is to perform simultaneous implantation of phosphorus ions into the region.

[0018] Specifically, the manufacturing method of the M IS-type semiconductor device of the present invention includes a first step of forming a gate insulating film on the n-channel type MIS transistor formation region on a semiconductor substrate, the gate insulating A second step of forming a gate electrode on the film; a third step of forming a channel adjusting sidewall on both side surfaces of the gate electrode; and a step of adjusting the channel in the n-channel MIS transistor forming region. Fourth implantation of phosphorus ions into the gate electrode and the inside of the semiconductor substrate using the sidewall as a mask
And the heat treatment to diffuse and activate the phosphorus ions to form the gate electrode as a low-resistance n-type gate electrode and to form n regions in the semiconductor substrate on both sides of the n-type gate electrode. A fifth step of forming a mold source / drain region , wherein the third step is the semiconductor step.
The exposed part of the substrate and gate electrode is oxidized to
The process of forming an oxide film on the
Etch back the oxide film, and on both sides of the gate electrode
Part of the oxide film is used as a channel adjustment sidewall.
And leaving them to remain .

According to this method, since the source / drain regions of the n-channel MIS transistor are formed by introducing phosphorus ions having an ion radius smaller than that of arsenic ions, crystal defects are reduced and a leak current at the junction is reduced. Will be reduced. Further, since the concentration distribution of phosphorus ions in the source / drain region becomes gentle, the electric field in the drain region becomes small, and the GIDL current is reduced. Furthermore, since the source / drain regions are deepened, the width of the depletion layer is increased and the parasitic capacitance is reduced. Further, the concentration of the electric field in the vicinity of the drain region is relaxed, and the characteristic deterioration due to the generation of hot carriers can be effectively prevented. Furthermore, since the channel adjusting sidewalls are provided on both sides of the gate electrode, the amount of overlap between the gate electrode and the drain region does not increase,
The gate-drain capacitance is reduced. That is, the above problems (1) to (4) are solved. Also, control of film thickness
Oxidation method with good properties and for oxidation of the side of the gate electrode
Since the channel adjustment sidewall is formed,
The gate capacitance and the capacitance between the gate and drain are reduced,
The operation is speeded up. In addition, the channel adjustment side wall
The width of the tool can be made extremely thin,
Exceeding the gate length limit determined by the accuracy of sography
Allows formation of MIS transistors with fine gate length
It becomes Noh.

[0020] In the above SL fourth step, a low concentration of phosphorus ions are implanted in, the fourth and before the fifth step after step, LDD sidewall on said channel adjustment sidewall And a step of implanting high-concentration phosphorus ions into the inside of the gate electrode and the semiconductor substrate by using the LDD sidewall as a mask. In the fifth step, the high-concentration phosphorus ion is formed. Ions can be diffused and activated to form n-type high-concentration source / drain regions outside the n-type source / drain regions in the semiconductor substrate.

By this method, the n-channel type MIS transistor has a so-called LDD structure, so that it is possible to form a fine n-channel type MIS transistor having a high function of preventing the short channel effect.

[0022] In the above SL first to the third step, also on the p-channel type MIS transistor formation region on a semiconductor substrate,
The same gate insulating film, gate electrode, and channel adjusting sidewall as in the n-channel type MIS transistor formation region are formed, and after the third step, the fifth step is performed.
Before the step of (4), the method further comprises a step of implanting p-type impurity ions into the gate electrode and the inside of the semiconductor substrate in the p-channel type MIS transistor formation region using the channel adjusting sidewall as a mask. In the step of, the gate electrode of the p-channel type MIS transistor formation region is a low-resistance p-type gate electrode, and p-type source / drain regions are formed in regions on both sides of the p-type gate electrode in the semiconductor substrate. Can be formed.

According to this method, the CMIS type semiconductor device is formed. Even after the heat treatment is performed under the same conditions to activate the impurity ions, the source / drain regions of the n channel type MIS transistor and the p channel type MIS transistor are formed. The source / drain regions have substantially the same depth and effective channel length. Therefore, in terms of performance, the balance between the p-channel type MIS transistor and the n-channel type MIS transistor is improved. Further, since phosphorus ions are implanted into the n-type gate electrode, the n-gate electrode is depleted even in a heat treatment for a short time or at a low temperature to such an extent that p-type impurity ions do not penetrate from the p-type gate electrode to the channel side. A high driving force can be obtained without That is,
The above problems (5) and (6) will be solved.

[0024] In the above SL fourth step, injecting a low concentration of phosphorus ions, the step of implanting the p-type impurity ions, and implanting low-concentration p-type impurity ions, the fourth step and p-type After the step of implanting the impurity ions and before the fifth step, a step of forming an LDD side wall on the side surface of the channel adjusting side wall;
In the channel type MIS transistor formation region, a step of implanting a high concentration of phosphorus ions into the inside of the gate electrode and the semiconductor substrate using the LDD side wall as a mask, and in the p channel type MIS transistor formation region, the LDD type The method further comprises the step of implanting high-concentration p-type impurity ions into the inside of the gate electrode and the semiconductor substrate using the sidewalls as masks. In the fifth step, the high-concentration phosphorus ions and the high-concentration p-ions are added. Type impurity ions are diffused and activated to form n-type high-concentration source / drain regions outside the n-type source / drain regions, and p-type high-concentration source outside the p-type source / drain regions. -A drain region can be formed.

By this method, the n-channel and p-channel type MIS transistors have a so-called LDD structure, so that a fine MIS transistor having a high function of preventing the short channel effect is provided.
It becomes possible to form a transistor.

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

[0037]

[0038]

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) First, a first embodiment of the present invention will be described with reference to the drawings.

1 (a) to 1 (d) are sectional views showing the manufacturing steps of the n-channel MOS type semiconductor device in the first embodiment.

First, as shown in FIG. 1A, a gate oxide film made of a silicon oxide film having a thickness of 4 to 8 nm is formed on a p-type semiconductor substrate 1 (which functions as a p-type semiconductor region in this embodiment). 4 and a gate electrode 5 made of a polysilicon film having a thickness of 100 to 200 nm are formed.

Next, as shown in FIG. 1B, a silicon oxide film 9 having a thickness of 100 to 150 nm is deposited on the gate electrode 5 and the p-type semiconductor substrate 1 by the CVD method.

Next, as shown in FIG. 1C, anisotropic dry etching is performed to etch back the silicon oxide film 9 to form channel adjusting sidewalls 6 on both side surfaces of the gate electrode 5. To do. The thickness of the channel adjusting sidewall 6 is about 40 to 100 nm.

Next, as shown in FIG. 1D, phosphorus ions (P +) are implanted using the channel adjusting sidewall 6 as a mask to remove the gate electrode 5 and the p-type semiconductor substrate 1 from each other. Phosphorus ions (P ⁺ ) are introduced into the regions located on both sides of the gate electrode 5. The implantation conditions at this time are as follows: acceleration energy is 5 to 20 KeV and implantation amount is 2 to 4 × 10 ^15.
cm ^-2 . Further, in the state shown in FIG.
5 to 1050 ° C for 10 seconds, or 850 ° C for 2 seconds
A heat treatment is performed under the condition of 0 to 30 minutes to activate the impurity ions (P +) to form the gate electrode 5 as the n-type gate electrode 5a having a reduced resistance, and the p-type semiconductor substrate 1
An n-type source / drain region 10a is formed therein. The depth of the n-type source / drain region 10a is 0.15 to 0.2.
It is about μm.

Although the following steps are omitted, a semiconductor device is formed by forming several layers of metal wiring via an interlayer insulating film.

N-channel M manufactured through the above steps
Since the OS-type transistor has the n-type gate electrode 5a formed by implanting phosphorus ions, the n-type gate electrode 15a (FIG. 1) formed using the conventional arsenic ions is used.
1 (b)), depletion of the gate electrode does not occur and the driving power of the n-channel MOS transistor is high.
Further, although the conventional source / drain regions are formed by implanting arsenic ions, since the diffusion coefficient of arsenic ions is small and the junction becomes shallow, the parasitic resistance (sheet resistance) of the source / drain regions becomes large. In order to obtain a structure capable of exhibiting the same function as that of the present embodiment by the above conventional structure, a low concentration source
It is necessary to have a so-called LDD structure in which a drain region is formed. At this time, the depth of the low-concentration source / drain regions formed by implanting arsenic ions is 30 to 50 nm.
The sheet resistance is about 1 KΩ / □. On the other hand, in the present embodiment, since phosphorus ions are used, the depth of the source / drain regions is 0.1 compared to arsenic ions.
It increases to about 5 to 0.2 μm. Therefore, the sheet resistance is reduced to about 80 to 100Ω / □.

In the structure without the channel adjusting sidewall 6 of the present invention, the n-type source / drain region 1 is formed by using phosphorus ions having a long diffusion distance as in the present embodiment.
When 0a is formed, the diffusion distance of phosphorus ions in the lateral direction also becomes long, and the n-type source / drain regions 10a that enter the inside of the n-type gate electrode 5a are formed. for that reason,
The effective channel length of the n-channel MOS transistor becomes small, the characteristics deteriorate in the region where the gate length is small, and the so-called short channel effect becomes large. Therefore, conventionally, when simultaneously implanting impurity ions into the polysilicon gate electrode and the n-type source / drain regions, arsenic ions are implanted.

On the other hand, according to the present invention, since the channel adjusting sidewall 6 is formed and then phosphorus ions are implanted to form the n-type source / drain regions 10a, the effective channel length is the gate length (polysilicon line). The width can be set to be almost equal to the width, and the short channel effect can be suppressed.
Then, while preventing the short channel effect, there is a problem (1) in the above-described conventional n-channel MOS transistor.
~ (5) can be solved as follows.

-To the problem (1)-FIGS. 8A and 8B show the case where the source / drain regions are formed by implanting phosphorus ions according to the present embodiment, and the arsenic ions according to the conventional method. Data of junction leakage current in the case of implanting and forming source / drain regions are shown. As can be seen by comparing FIGS. 8A and 8B, the leakage of a large current value (10 ⁻⁸ A) is high in the implantation of arsenic ions, but in the present embodiment, the leakage of a large current value is high. (10 ⁻⁸ A) does not occur, and only a minute leak of 10 ⁻⁹ A or less occurs. That is, the n-type source / drain region 10 of the n-channel MOS transistor
It is understood that since a is formed by introducing phosphorus ions having an ion radius smaller than that of arsenic ions, crystal defects are reduced and the leak current at the junction is also small.

-To Problem (2) -The concentration distribution of phosphorus ions at the time of implantation is not as steep as that of the concentration distribution at the time of implantation of arsenic ions, and the diffusion distance due to the subsequent heat treatment is long. Becomes gentle. Therefore, the electric field in the n-type drain region 10 becomes small and the GIDL current is reduced.

-To the problem (3)-In FIG.
FIG. 6 is a diagram comparing the capacitance of a pn junction with a case where a drain region is formed and a case where a source / drain region is formed by implanting arsenic ions by a conventional method. As can be seen from the figure, since the source / drain regions are formed by implanting phosphorus ions as in this embodiment, the pn
The capacity of the junction is greatly reduced. As mentioned above,
Since the n-type drain region 10a becomes deep and the concentration distribution of phosphorus ions becomes gentle, the width of the depletion layer increases as compared with the drain region formed by arsenic ions. Therefore, the parasitic capacitance is reduced.

As to the problem (4), as described above, the concentration distribution of phosphorus ions in the n-type drain region 10a becomes gentle, so that the concentration of the electric field in the vicinity of the drain region is relaxed, and hot carriers are generated. It is possible to effectively prevent the deterioration of the characteristics caused by the occurrence, and thus improve the reliability.

Since the channel adjusting sidewalls 6 are provided on both side surfaces of the n-type gate electrode 5a,
There is an advantage that the distance between the n-type gate electrode 5a and the n-type drain region 10a becomes long and the gate-drain capacitance becomes small.

Therefore, in the n-channel MOS transistor according to the present embodiment, the junction leakage current is small, the hot carrier generation probability is low, the parasitic capacitance is small, and the GIDL current is small. In other words, it is possible to provide a device having a large driving force, a small leak current, and excellent reliability.

(Second Embodiment) Next, regarding a MOS type semiconductor device of the second embodiment,
A description will be given with reference to the drawings.

2A to 2D are cross-sectional views showing the manufacturing process of the n-channel MOS type semiconductor device according to the second embodiment.

First, as shown in FIG. 2A, a gate oxide film made of a silicon oxide film having a thickness of 4 to 8 nm is formed on a p-type semiconductor substrate 1 (which functions as a p-type semiconductor region in this embodiment). 4 and a gate electrode 5 made of a polysilicon film having a thickness of 100 to 200 nm are formed.

Next, as shown in FIG. 2B, the upper surface and both side surfaces of the gate electrode 5 and the p-type semiconductor substrate 1 are thermally oxidized.
Oxide film 8 having a thickness of 5 to 20 nm on the surface of
(Thermal oxide film) is deposited.

Next, as shown in FIG. 2C, anisotropic dry etching is performed to etch back the silicon oxide film 8 to form the channel adjusting sidewall 6 on the sidewall of the gate electrode 5.

Next, as shown in FIG. 2D, phosphorus ion (P +) is implanted by using the channel adjusting sidewall 6 as a mask to implant the gate electrode 5 and the p-type semiconductor substrate 1 with each other. Phosphorus ions (P ⁺ ) are introduced into the regions located on both sides of the gate electrode 5. The implantation conditions at this time are as follows: acceleration energy is 5 to 20 KeV and implantation amount is 2 to 4 × 10 ^15.
cm ^-2 . Further, in the state shown in FIG.
Heat treatment is performed at a temperature of 5 to 1050 ° C. for 10 seconds to activate the impurity ions (P ⁺ ) so that the gate electrode 5 becomes the n-type gate electrode 5a having a reduced resistance, and the p-type semiconductor substrate 1 is formed. The n-type source / drain region 10a is formed.

Although the following steps are omitted, a semiconductor device is formed by forming several layers of metal wiring via an interlayer insulating film.

The n-channel type MOS transistor manufactured through the process of this embodiment has basically the same characteristics as the transistor manufactured by the manufacturing process of the above-mentioned first embodiment, and has the above-mentioned conventional n-channel type. Problems (1) to (4) in the MOS transistor can be solved. In addition, in the present embodiment, since the width of the channel adjusting sidewall 6 is determined by thermal oxidation, the controllability is good, and the channel adjusting sidewall 6 is obtained by oxidizing the polysilicon film (gate electrode 5). As shown in FIG. 2D, the position of the gate oxide film 4 is slightly higher than the surface position of the n-type source / drain region 10a. As a result, the gate capacitance and the gate / drain capacitance are reduced, and the circuit operation speed is high. become.

Moreover, the silicon oxide film 8 formed by thermal oxidation
Unlike the silicon oxide film 9 (thickness 100 to 150 nm) formed by the CVD method, the thickness (5 to 20 nm) is extremely thin. Therefore, in this embodiment , since the gate length can be made shorter than the limit gate length determined by the accuracy of photolithography, it is possible to obtain a remarkable effect that an extremely fine MOS transistor can be formed.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to the drawings.

3 (a) to 3 (f) are sectional views showing the manufacturing steps of the n-channel MOS type semiconductor device in the third embodiment.

First, as shown in FIG. 3A, a gate oxide film made of a silicon oxide film having a thickness of 4 to 8 nm is formed on a p-type semiconductor substrate 1 (which functions as a p-type semiconductor region in this embodiment). 4 and a gate electrode 5 made of a polysilicon film having a thickness of 100 to 200 nm are formed.

Next, as shown in FIG. 3B, a silicon oxide film 9 having a thickness of 50 to 80 nm is deposited on the gate electrode 5 and the p-type semiconductor substrate 1 by the CVD method.

Next, as shown in FIG. 3C, anisotropic dry etching is performed to etch back the silicon oxide film 9 so that the width (thickness) is 40 to 5 on both side surfaces of the gate electrode 5.
A 0 nm channel adjusting sidewall 6 is formed.

Next, as shown in FIG. 3D, phosphorus ions (P +) are implanted using the channel adjusting sidewall 6 as a mask to remove the gate electrode 5 and the p-type semiconductor substrate 1 from each other. A low concentration of phosphorus ions (P ⁺ ) is introduced into the regions 10 located on both sides of the gate electrode 5. The implantation conditions at this time are acceleration energy of 5 to 20 KeV and implantation amount of 1
˜5 × 10 ¹⁴ cm ⁻² .

Next, as shown in FIG. 3E, a silicon oxide film (not shown) is deposited by the CVD method and is etched back by anisotropic etching to outside the channel adjusting sidewall 6. Then, the sidewall 7 for LDD having a width of about 150 to 200 nm is formed.

Then, as shown in FIG. 3F, phosphorus ions (P +
) Is performed to introduce high-concentration phosphorus ions (P ⁺ ) into the n-type gate electrode 5a and the region located on the side of the sidewall 7 in the p-type semiconductor substrate 1. The implantation conditions at this time are: an acceleration energy of 5 to 20 KeV and an implantation amount of 2
It is about 4 × 10 ¹⁵ cm ^-2 . Further, in the state shown in FIG. 3F, heat treatment is performed under the conditions of 975 to 1050 ° C. for 10 seconds to activate the impurity ions (P ⁺ ) and to make the gate electrode 5 a low resistance n-type gate electrode. 5a, an n-type low concentration source / drain region 10a and an n-type high concentration source / drain region 12a are formed.

Although the following steps are omitted, a semiconductor device is formed by forming several layers of metal wiring via an interlayer insulating film.

The n-channel MOS transistor obtained by the manufacturing process of this embodiment has the characteristics of the n-channel MOS transistor shown in the first embodiment, and
It also has the advantage of an LDD structure. That is, since the n-type low-concentration source / drain region 10a is formed by ion implantation with low energy (5 to 20 KeV), the junction becomes shallow, and the extension of the depletion layer from the n-type low-concentration drain region 10a is suppressed small. Therefore, the short channel effect can be suppressed more reliably.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to the drawings.

FIGS. 4A to 4D are sectional views showing the manufacturing process of the CMOS type semiconductor device in the fourth embodiment.

First, as shown in FIG. 4A, on the p-type semiconductor substrate 1, a p-type semiconductor region 2a (in this embodiment, p-type semiconductor region 2a) which is an n-channel MOS transistor forming region is formed.
Region having the same impurity concentration as that of the p-type semiconductor substrate 1, an n-type semiconductor region 2b which is a p-channel MOS transistor formation region, and an element isolation region 3 which separates the p-type semiconductor region 2a and the n-type semiconductor region 2b. Has been formed. A thickness of 4 is formed on the p-type semiconductor region 2a and the n-type semiconductor region 2b.
A gate oxide film 4 made of a silicon oxide film of ˜8 nm,
A gate electrode 5 made of a polysilicon film having a thickness of 100 to 200 nm is formed.

Next, as shown in FIG. 4B, a silicon oxide film having a thickness of 100 to 150 nm is deposited on the gate electrode 5 and the p-type semiconductor substrate 1 by the CVD method, and then anisotropic dry etching is performed. Then, the silicon oxide film is etched back to form channel adjusting sidewalls 6 on both side surfaces of the gate electrode 5.

Next, as shown in FIG. 4C, in the p-type semiconductor region 2a, phosphorus ions (P ⁺ ) are implanted using the channel adjusting sidewall 6 as a mask to form the gate electrode 5 and the gate electrode 5. , Phosphorus ions are introduced into the regions 10 located on both sides of the gate electrode 5 in the p-type semiconductor region 2a. The implantation condition at this time is that the acceleration energy is 5 to 20.
KeV, implantation amount is 2 to 4 × 10 ¹⁵ cm ^-2 . However, although not shown, the n-type semiconductor region 2b is covered with a resist mask while the impurity ions are implanted into the p-type semiconductor region 2a. Further, in the n-type semiconductor region 2a,
Boron fluoride ions (BF ₂ ⁺ ) are implanted using the channel adjusting sidewall 6 as a mask, and the gate electrode 5 and the regions 11 located on both sides of the gate electrode 5 in the n-type semiconductor region 2b are implanted. Boron fluoride ions are introduced. The implantation condition at this time is that the acceleration energy is 10 to 3
The injection amount is 0 KeV and the implantation amount is 1 to 4 × 10 ¹⁵ cm ^-2 . However, although not shown, the p-type semiconductor region 2a is covered with a resist mask while the impurity ions are implanted into the n-type semiconductor region 2b.

Further, in the state shown in FIG.
A heat treatment is performed at 1050 ° C. for 10 seconds to activate the impurity ions (P ⁺ , BF ₂ ⁺ ). By this process, the gate electrode 5 is formed in the p-type semiconductor region 2a.
Is a low resistance n-type gate electrode 5a, and
The n-type source / drain region 10a is formed. Also, n
In the type semiconductor region 2b, the gate electrode 5 is a p-type gate electrode 5b having a low resistance, and the p-type source / drain regions 11a are formed.

Although the following steps are omitted, a semiconductor device is formed by forming several layers of metal wiring with an interlayer insulating film interposed therebetween.

This embodiment is basically an application of the first embodiment to a CMOS type semiconductor device, and the n-channel type MOS transistor has the characteristics as described in the first embodiment. Have.

In addition, the CM formed by this embodiment
The OS type semiconductor device has the following advantages as compared with the conventional CMOS type semiconductor device in which an n-channel type MOS transistor using arsenic ion implantation and a p-channel type MOS transistor using boron fluoride ion implantation are combined. Have.

First, the above problem (5) can be solved. That is, in this embodiment, since the n-type source / drain region 10a of the n-channel MOS transistor is formed by introducing phosphorus ions having a diffusion coefficient almost equal to that of boron ions, heat treatment is performed under the same conditions. Even after activating the impurity ions, the n-type source / drain regions 10a and the p-channel MO of the n-channel MOS transistor are activated.
The p-type source / drain region 11a of the S transistor has substantially the same depth and effective channel length. Therefore,
In terms of performance, the balance between the p-channel type MOS transistor and the n-channel type MOS transistor is improved.

Secondly, the above-mentioned problem (6) can be solved.
FIG. 10 is data showing sheet resistances of an n-type gate electrode formed by implanting phosphorus ions and a conventional gate electrode formed by implanting arsenic ions in the present embodiment. As shown in the figure, the sheet resistance value of the n-type gate electrode formed by implanting phosphorus ions is smaller than the sheet resistance value of the n-type gate electrode formed by implanting arsenic ions, and Depletion is suppressed. That is, since phosphorus ions are implanted into the n-type gate electrode 5a of the n-channel MOS transistor, the p-type gate electrode 5b of the p-channel MOS transistor is short-time or short enough to prevent boron penetration into the channel region. A high driving force can be obtained without depleting the n-type gate electrode 5a of the n-channel MOS transistor even by heat treatment under low temperature conditions.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described with reference to the drawings.

5A to 5E are cross-sectional views showing the manufacturing process of the CMOS type semiconductor device according to the fifth embodiment.

First, as shown in FIG. 5A, on the p-type semiconductor substrate 1, a p-type semiconductor region 2a (in this embodiment, p-type semiconductor region 2a) which is an n-channel MOS transistor forming region is formed.
Region having the same impurity concentration as that of the p-type semiconductor substrate 1, an n-type semiconductor region 2b which is a p-channel MOS transistor formation region, and an element isolation region 3 which separates the p-type semiconductor region 2a and the n-type semiconductor region 2b. Has been formed. A thickness of 4 is formed on the p-type semiconductor region 2a and the n-type semiconductor region 2b.
A gate oxide film 4 made of a silicon oxide film of ˜8 nm,
A gate electrode 5 made of a polysilicon film having a thickness of 100 to 200 nm is formed.

Next, as shown in FIG. 5B, a silicon oxide film having a thickness of 50 to 80 nm is deposited on the gate electrode 5 and the p-type semiconductor substrate 1 by the CVD method, and then anisotropic dry etching is performed. Then, the silicon oxide film is etched back to form channel adjusting sidewalls 6 having a width of 40 to 50 nm on both side surfaces of the gate electrode 5.

Next, as shown in FIG. 5C, in the n-channel MOS transistor formation region, phosphorus ions (P ⁺ ) are implanted using the channel adjusting sidewall 6 as a mask to form the gate electrode. Phosphorus ions are introduced into the p-type semiconductor region 2a and the regions 10 located on both sides of the gate electrode 5 in the p-type semiconductor region 2a. The implantation conditions at this time are: an acceleration energy of 5 to 20 KeV and an implantation amount of 1 to 5 × 10 ¹⁴ c.
m ^-2 . However, although not shown, the p-type semiconductor region 2a
The n-type semiconductor region 2b is covered with the resist mask while the impurity ions are implanted into the n-type semiconductor region 2b. In the n-type semiconductor region 2b, boron fluoride ions (BF ₂ ⁺ ) are implanted using the channel adjusting sidewall 6 as a mask, and the gate electrode 5 and the gate electrode 5 in the n-type semiconductor region 2b are implanted. Boron fluoride ions are introduced into the regions 11 located on both sides of. The implantation conditions at this time are as follows: acceleration energy is 5 to 15 KeV and implantation amount is 5 to 10 × 10 ¹⁴ cm.
^-2 . However, although not shown, the p-type semiconductor region 2a is covered with a resist mask while the impurity ions are implanted into the n-type semiconductor region 2b.

Next, as shown in FIG. 5 (d), a silicon oxide film (not shown) is deposited by the CVD method and etched back by anisotropic etching to outside the channel adjusting sidewall 6. Then, the sidewall 7 for LDD having a width of about 150 to 200 nm is formed.

Next, as shown in FIG. 5E, in the p-type semiconductor region 2a, phosphorus ions (P +) are implanted using the sidewalls 6 and 7 as masks to form the gate electrode 5
And phosphorus ions are introduced into the regions located on the sides of the sidewalls 6 and 7 in the p-type semiconductor region 2a. The implantation conditions at this time are an acceleration energy of 5 to 20 KeV and an implantation amount of 2 to 4 × 10 ¹⁵ cm ^-2 . Further, in the n-type semiconductor region 2b, boron fluoride ions (BF ₂ ⁺ ) are implanted by using the sidewalls 6 and 7 as masks, and the gate electrode 5 and the sidewalls 6 and 6 in the n-type semiconductor region 2b are implanted.
Boron fluoride ions are introduced into and into the region located on the side of 7. The implantation condition at this time is that the acceleration energy is 10
˜30 KeV, and implant amount is 1˜4 × 10 ¹⁵ cm ⁻² .
However, although not shown, while the impurity ions are implanted into one semiconductor region, the other semiconductor region is covered with the resist mask.

Further, in the state shown in FIG.
Heat treatment is performed at 1050 ° C. for 10 seconds to activate the impurity ions (P ⁺ , BF ₂ ⁺ ). By this process, in the p-type semiconductor region 2a, the gate electrode 5 is changed to the n-type gate electrode 5a whose resistance is reduced, and n
A low-concentration type source / drain region 10a and a high-concentration n-type source / drain region 12a are formed. In the n-type semiconductor region 2b, the gate electrode 5 is a p-type gate electrode 5b having a low resistance, and the p-type low-concentration source / drain region 11a and the p-type high-concentration source / drain region 13a are formed. Form.

Although the following steps are omitted, a semiconductor device is formed by forming several layers of metal wiring with an interlayer insulating film interposed therebetween.

CMO formed by the process of this embodiment
The S-type transistor has the features of the second embodiment and the third embodiment as described below.

First, since both the n-channel type transistor and the p-channel type MOS transistor have the LDD structure in which the low concentration source / drain regions 10a and 11a are formed by shallow implantation after the channel adjusting sidewall 6 is formed. The short channel effect in each channel type MOS transistor can be suppressed.

Secondly, since the source / drain regions 10a and 12a of the n-channel type MOS transistor are formed by introducing phosphorus ions, each source / drain region of the n-channel type MOS transistor is subjected to heat treatment under the same conditions. The drain regions 10a and 12a can have substantially the same shape as the source / drain regions 11a and 13a of the p-channel type MOS transistor, and the balance of the performance of each MOS transistor is improved.

Thirdly, since the n-type gate electrode 5a of the n-channel MOS transistor is formed by implanting phosphorus ions, boron ions do not penetrate through the p-type gate electrode 5b of the p-channel MOS transistor. N for short time or low temperature
The mold gate electrode 5a is sufficiently activated and a high driving force can be obtained.

(Sixth Embodiment) Next, a sixth embodiment of the present invention will be described with reference to the drawings.

FIGS. 6A to 6D are sectional views showing the manufacturing process of the CMOS type semiconductor device in the sixth embodiment.

First, as shown in FIG. 6A, on the p-type semiconductor substrate 1, a p-type semiconductor region 2a (in this embodiment, p-type semiconductor region 2a) which is an n-channel MOS transistor formation region is formed.
Region having the same impurity concentration as that of the p-type semiconductor substrate 1, an n-type semiconductor region 2b which is a p-channel MOS transistor formation region, and an element isolation region 3 which separates the p-type semiconductor region 2a and the n-type semiconductor region 2b. Has been formed. A thickness of 3 is formed on the p-type semiconductor region 2a and the n-type semiconductor region 2b.
A gate oxide film 4 made of a silicon oxide film of about 5 nm,
A gate electrode 5 made of a polysilicon film having a thickness of 100 to 200 nm is formed.

Next, as shown in FIG. 6B, a silicon oxide film 9 having a thickness of 5 to 20 nm is deposited on the upper surface and both side surfaces of the gate electrode 5 and the substrate surface by the CVD method.
Then, in this state, in the p-type semiconductor region 2a, phosphorus ions are introduced into the silicon oxide film 9 by implantation of phosphorus ions. The implantation conditions are an acceleration energy of 3 to 10 KeV and an implantation amount of 5 to 8 × 10 ¹⁵ cm ^-2 . Further, in the n-type semiconductor region 2b, boron fluoride ions are implanted into the silicon oxide film 9. The implantation conditions are acceleration energy of 3 to 10
KeV, implantation amount is 3 to 8 × 10 ¹⁵ cm ^-2 . These implantations are preferably performed under the condition that the impurity concentration peak RP exists in the oxide film and almost no impurity ions are introduced into the semiconductor substrate immediately after the implantation, but even under the condition that a considerable number of impurities enter into the semiconductor substrate. By implanting through the oxide film, ion channeling at the time of implantation is suppressed, so that a shallow junction can be formed.

Next, as shown in FIG. 6C, after a silicon oxide film is deposited on the gate electrode 5 and the p-type semiconductor substrate 1 by the CVD method, anisotropic dry etching is performed to perform the silicon oxide film. 9 is etched back to form channel adjusting sidewalls 6 having a width of 120 to 200 nm on both side surfaces of the gate electrode 5. When the channel adjusting sidewall 6 is formed, the thermal oxide film on the gate electrode and the substrate surface is etched by anisotropic dry etching. Then, in the state shown in FIG. 6C, in the p-type semiconductor region 2a, phosphorus ions (P +) are implanted using the channel adjusting sidewall 6 as a mask, and the gate electrode 5 is formed.
And phosphorus ions are introduced into the region 12 located on the side of the sidewall 6 in the p-type semiconductor region 2a. The implantation conditions at this time are an acceleration energy of 5 to 20 KeV and an implantation amount of 2 to 4 × 10 ¹⁵ cm ^-2 . However, although not shown, while implanting impurity ions into the p-type semiconductor region 2a, n
The type semiconductor region 2b is covered with a resist mask. In the n-type semiconductor region 2b, boron fluoride ions (BF ₂ ⁺ ) are implanted using the channel adjusting sidewall 6 as a mask, and the gate electrode 5 and the sidewall 6 in the n-type semiconductor region 2b are implanted. Boron fluoride ions are introduced into the region 13 located on the side of. The implantation conditions at this time are an acceleration energy of 10 to 30 KeV and an implantation amount of 1 to 4 × 10 ¹⁵ cm ^-2 . However, although not shown in the drawing, while implanting impurity ions into the n-type semiconductor region 2b, p
The type semiconductor region 2a is covered with a resist mask.

Next, as shown in FIG.
Heat treatment is performed at 1050 ° C. for 10 seconds to activate the impurity ions (P ⁺ , BF ₂ ⁺ ) and simultaneously diffuse the impurity ions in the L-shaped silicon oxide film 9 into the semiconductor substrate. By this process, the gate electrode 5 on each of the regions 2a and 2b is made into the n-type gate electrode 5a and the p-type gate electrode 5b whose resistance is reduced, and the n-type high concentration source / drain region 12a and the p-type high concentration source / drain The region 13a is formed, and phosphorus ions are diffused into the p-type semiconductor region 2a in the n-channel MOS transistor, and boron ions are diffused into the n-type semiconductor region 2b in the p-channel MOS transistor, respectively. Low concentration sauce
A drain region 10a and a p-type low concentration source / drain region 11a are formed. In this case, in both the n-channel type MOS transistor and the p-channel type MOS transistor, the diffusion depth Xj in the low concentration source / drain region is ²⁰ to 40 nm and the surface impurity concentration Cf is 2 to 8 × 10 ²⁰ cm ^{−. Is 3} . In addition, an n-channel MO
In both the S-transistor and the p-channel MOS transistor, the diffusion depth Xj in the high-concentration source / drain region is 100 to 150 nm and the surface impurity concentration Cf is 1 to 10 × 10 ²⁰ cm ⁻³ .

Although the following steps are omitted, a semiconductor device is formed by forming several layers of metal wiring with an interlayer insulating film interposed therebetween.

The feature of this embodiment is that the low-concentration source / drain regions 10a and 11a are formed by diffusion of impurity ions from the silicon oxide film 9 instead of normal ion implantation. According to this method, it is possible to make the depths of the low-concentration source / drain regions 10a and 11a very shallow and increase the impurity concentration thereof. As a result, it is possible to obtain a device that can reduce the parasitic resistance (sheet resistance) of the low-concentration source / drain regions and at the same time suppress the occurrence of the short channel effect.

(Seventh Embodiment) Next, a seventh embodiment of the present invention will be described with reference to the drawings.

7A to 7E are cross-sectional views showing the manufacturing process of the CMOS type semiconductor device in the seventh embodiment.

Here, FIGS. 7A to 7 of the present embodiment.
The process shown in (e) is the same as in FIG. 6 in the sixth embodiment.
The steps are basically the same as those shown in FIGS. However, in the step shown in FIG. 7B, in the present embodiment, the silicon oxide film 8 is formed by a thermal oxidation method instead of the CVD method in the sixth embodiment, and impurity ions are introduced into the silicon oxide film 8. After the implantation, the impurity ions are diffused from the silicon oxide film 8 to form the low concentration source / drain regions 10a and 11a. In addition, FIG. 7C shows a step between the step shown in FIG. 6B and the step shown in FIG. 6C (a state after forming the LDD sidewall and before implanting impurity ions). It shows in more detail.

Therefore, the CMOS type transistor formed in the manufacturing process of this embodiment has the same advantages as the CMOS transistor in the sixth embodiment. In addition, by using a thermal oxide film formed by oxidizing the polysilicon film forming the gate electrode, the gate capacitance and the gate-drain capacitance can be reduced, and the operation of the circuit composed of transistors can be performed at high speed. Can be converted.

However, the impurity diffusion from the thermal oxide film is C
It is necessary to perform it at a higher temperature than the diffusion from the VD oxide film or to change the implantation conditions into the oxide film.

Finally, the present invention is applied to SOI (Silicon On Ins
The following is a brief description of an example of application using an emulator substrate. Since the conventional SOI-MOS device has a buried oxide film, a major drawback is that the substrate potential cannot be obtained. That is, when the carriers flowing in the channel cause impact ionization and electron-hole pairs are generated, the holes remain in the substrate because the potential of the substrate is not taken, and the characteristics of the transistor are significantly deteriorated. On the other hand, when the present invention is applied to the SOI-MOS device, since the source / drain regions are formed by introducing phosphorus ions, the electric field in the vicinity of the drain is weakened and the probability of carriers causing impact ionization is reduced. Therefore, deterioration of the device can be effectively prevented, and a device having a higher breakdown voltage and higher operating accuracy than the conventional one can be obtained.

[0112]

According to the method of manufacturing a MIS type semiconductor device of the present invention , as a method of manufacturing a MIS type semiconductor device, channel adjusting sidewalls are formed on both side surfaces of a gate electrode, and channel adjusting sidewalls are formed. Since phosphorus ions are implanted into the gate electrode and the semiconductor substrate by using as a mask to form a low resistance n-type gate electrode and n-type source / drain regions, introduction of phosphorus ions having a smaller ion radius than arsenic ions Reduction of leakage current at the junction of the n-type source / drain region formed by
The GIDL current can be reduced, the parasitic capacitance can be reduced, and the deterioration of the characteristics due to the generation of hot carriers can be prevented. Therefore, the leakage current is small and the driving capability is large.
Moreover, it is possible to provide a highly reliable MIS semiconductor device.

[0113]

[0114]

[0115]

[0116]

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of an n-channel type MOS transistor according to a first embodiment.

FIG. 2 is a cross-sectional view showing the manufacturing process of the n-channel MOS transistor according to the second embodiment.

FIG. 3 shows an n having an LDD structure according to a third embodiment.
FIG. 7 is a cross-sectional view showing the manufacturing process of the channel MOS transistor.

FIG. 4 is a cross-sectional view showing the manufacturing process of the complementary MOS transistor according to the fourth embodiment.

FIG. 5 is a cross-sectional view showing a manufacturing process of a complementary MOS transistor having an LDD structure according to a fifth embodiment.

FIG. 6 is a cross-sectional view showing the manufacturing process of the complementary MOS transistor according to the sixth embodiment.

FIG. 7 is a cross-sectional view showing the manufacturing process of the complementary MOS transistor according to the seventh embodiment.

FIG. 8 is a diagram showing junction leak currents in a source / drain region formed by implanting phosphorus ions and a source / drain region formed by implanting arsenic ions, respectively.

FIG. 9 is a diagram showing a junction capacitance in a source / drain region formed by implanting phosphorus ions and a source / drain region formed by implanting arsenic ions.

FIG. 10 is a diagram showing sheet resistance in an n-type gate electrode formed by implanting phosphorus ions and an n-type gate electrode formed by implanting arsenic ions.

FIG. 11 is a cross-sectional view showing a manufacturing process of a conventional complementary MOS transistor.

[Explanation of symbols]

1 semiconductor substrate 2a p-type semiconductor region 2b n-type semiconductor region 3 element isolation region 4 gate oxide film 5 gate electrode 6 channel adjustment sidewall 7 LDD sidewall 8 silicon oxide film 9 silicon oxide film 10a n-type source / drain region (N type low concentration source / drain region) 11a p type source / drain region (p type low concentration source / drain region) 12a n type high concentration source / drain region 13a p type high concentration source / drain region 5a n type gate electrode 5b p-type gate electrode

Continuation of the front page (56) Reference JP-A-4-218925 (JP, A) JP-A-4-61254 (JP, A) JP-A-60-81866 (JP, A) JP-A-57-97676 (JP , A) JP 62-293776 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (4)

(57) [Claims] 1. A first step of forming a gate insulating film on an n-channel MIS transistor formation region on a semiconductor substrate, a second step of forming a gate electrode on the gate insulating film, and the gate. A third step of forming channel adjusting sidewalls on both side surfaces of the electrode, and phosphorus in the gate electrode and the semiconductor substrate in the n-channel MIS transistor formation region using the channel adjusting sidewalls as a mask. The fourth step of implanting ions, and the heat treatment to diffuse and activate the phosphorus ions to make the gate electrode a low-resistance n-type gate electrode and both sides of the n-type gate electrode in the semiconductor substrate. and a fifth step of forming a n-type source and drain regions in the regions located above the third step, the semiconductor substrate and the gate electrode Oxidizing the exposed portion of the
Then, a step of forming an oxide film on the entire surface and etching back the oxide film by anisotropic etching,
Channel a part of the oxide film on both sides of the gate electrode.
And a step of leaving it as a side wall for adjustment of a semiconductor device, a method of manufacturing a MIS type semiconductor device. 2. The method for manufacturing a MIS type semiconductor device according to claim 1, wherein in the fourth step, low-concentration phosphorus ions are implanted, and after the fourth step and before the fifth step. And a step of forming an LDD sidewall on the channel adjusting sidewall and a step of implanting a high concentration of phosphorus ions into the gate electrode and the semiconductor substrate using the LDD sidewall as a mask. Further, in the fifth step, the high-concentration phosphorus ions are diffused and activated to form n-type high-concentration source / drain regions outside the n-type source / drain regions in the semiconductor substrate. A method of manufacturing a MIS type semiconductor device, comprising: 3. The method for manufacturing an MIS type semiconductor device according to claim 1, wherein in the first to third steps, the n channel type MIS is also formed on a p channel type MIS transistor formation region on a semiconductor substrate. A gate insulating film, a gate electrode, and a channel adjusting sidewall similar to those in the transistor formation region are formed, and in the p-channel MIS transistor formation region after the third step and before the fifth step, The method further includes a step of implanting p-type impurity ions into the gate electrode and the inside of the semiconductor substrate using the channel adjusting sidewall as a mask. In the fifth step, the gate electrode in the p-channel type MIS transistor formation region is lowered. A p-type gate electrode of a resistor and located on both sides of the p-type gate electrode in the semiconductor substrate. A method for manufacturing a MIS type semiconductor device, which comprises forming p-type source / drain regions in the regions. 4. The method for manufacturing a MIS semiconductor device according to claim 3, wherein in the fourth step, a low concentration of phosphorus ions is implanted, and in the step of implanting the p-type impurity ions, a low concentration of p is added.
Type impurity ions are implanted, and after the fourth step and the step of implanting p-type impurity ions, but before the fifth step, an LDD sidewall is formed on the side surface of the channel adjusting sidewall. And a step of implanting a high concentration of phosphorus ions into the inside of the gate electrode and the semiconductor substrate using the LDD sidewall as a mask in the n-channel MIS transistor formation region, and forming the p-channel MIS transistor. The step of implanting high-concentration p-type impurity ions into the gate electrode and the semiconductor substrate using the LDD sidewall as a mask in the region, and in the fifth step, the high-concentration phosphorus ion is added. And the high-concentration p-type impurity ions are diffused and activated, and
N-type high-concentration source / drain regions are formed outside the p-type source / drain regions, and p-type high-concentration source / drain regions are formed outside the p-type source / drain regions. Device manufacturing method.