JP2808620B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device.
The present invention relates to a method for manufacturing a semiconductor device having a conductive MIS transistor and a second conductive MIS transistor.

[Summary of the Invention]

The present invention relates to a method of manufacturing a semiconductor device having a first conductivity type MIS transistor and a second conductivity type MIS transistor, in which a depletion layer is suppressed from spreading below a channel region of the first conductivity type MIS transistor. At the same time as forming the second conductivity type impurity-introduced portion, the second conductivity type MIS transistor has a lower impurity concentration than the source region and the drain region in contact with at least a part of the source region and the drain region of the second conductivity type MIS transistor. An impurity introduction part is formed. Thereby, the junction capacitance of the source region and the drain region of the MIS transistor of the second conductivity type can be reduced, and the number of steps is not increased.

[Prior art] In recent years, in MOS LSIs, in order to prevent the short channel effect accompanying the miniaturization of MOS transistors, the impurity concentration in the lower part of the channel region is increased by introducing impurities, and especially from the drain region side. A technique for suppressing the spread of the depletion layer is used.

3A to 3C show a conventional CMOS LS using this technique.
The manufacturing method of I is shown. According to this method, as shown in FIG. 3A, first, an n-well 102 is formed in a p-type silicon (Si) substrate 101, and then the surface of the p-type silicon substrate 101 is selectively thermally oxidized. To form a field insulating film 103 such as a SiO ₂ film, thereby performing element isolation. Next, a gate insulating film 104 such as a SiO ₂ film is formed on the surface of the active region surrounded by the field insulating film 103 by thermal oxidation. next,
After forming a resist pattern 105 having an opening corresponding to a region where an impurity introduction portion (hereinafter, also simply referred to as a "high impurity concentration portion") for suppressing the spread of a depletion layer is formed, the resist pattern 105 is used as a mask. n-well 1
During 02, an n-type impurity such as phosphorus (P) is selectively ion-implanted with high energy. After that, the resist pattern 105 is removed.

Next, as shown in FIG. 3B, gate electrodes 106 and 107 are formed on the gate insulating film 104.

Next, a p-type impurity such as, for example, boron (B) is doped with an n-well 102 in the p-channel MOSFET formation portion while the surface of the n-channel MOSFET formation portion is covered with a resist or the like.
After high-concentration ion implantation, for example, arsenic (As)
Is ion-implanted at a high concentration. Thereafter, these implanted impurities are electrically activated by performing a heat treatment. Thereby, as shown in FIG. 3C, for example, a p ⁺ -type source region 108 and a drain region 109 are formed in a self-alignment manner with respect to the gate electrode 106, and are formed in a self-alignment manner with respect to the gate electrode 107. For example, an n ⁺ type source region 110 and a drain region 111 are formed. At the same time, n is placed below the channel region of the p-channel MOSFET.
An n-type high impurity concentration portion 112 having an impurity concentration higher than that of the well 102 is formed. The high impurity concentration portion 112 suppresses the spread of the depletion layer and prevents the short channel effect. The gate electrode 106 is composed is a p-channel MOSFET T ₁ by the source region 108 and drain region 109, gate electrode 107, n-channel MOSFET T ₂ is constituted by the source region 110 and drain region 111.

[Problems to be solved by the invention]

In CMOSLSI produced by conventional manufacturing methods described above, the junction capacitance of the n-channel MOSFET T ₂ of the source region 110 and drain region 111 is large, this is the n-channel MOS
This was one of the factors that reduced the operation speed of FETT ₂ . In order to reduce the junction capacitance between the source region 110 and the drain region 111, an impurity introduction portion having a lower impurity concentration than the source region 110 and the drain region 111 (hereinafter simply referred to as the source region 110 and the drain region 111). It is conceivable to increase the width of the depletion layer at the junction by forming a "low impurity concentration portion". However, a new process for forming the low impurity concentration portion is required. Increase.

Accordingly, an object of the present invention is to provide a source and drain region of an MIS transistor of the second conductivity type when an impurity introduction portion for suppressing the spread of a depletion layer is formed below the channel region of the MIS transistor of the first conductivity type. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can reduce the junction capacitance of the semiconductor device and does not increase the number of steps.

[Means for solving the problem]

In order to solve the above problems, the present invention provides a first conductivity type MI.
In a method for manufacturing a semiconductor device having an S transistor (Q ₁ ) and a MIS transistor (Q ₂ ) of a second conductivity type, the first
Second conductivity-type impurity introduced portion of the for suppressing the spread of a depletion layer in the lower portion of the channel region of the conductivity type of the MIS transistor (Q ₁₎ (12) and simultaneously forming a second conductivity type MIS transistor (Q ₂₎ Forming a second conductivity type impurity doped portion (10a, 11a) having a lower impurity concentration than the source region (10) and the drain region (11), which are in contact with at least a part of the source region (10) and the drain region (11). doing.

[Action]

According to the above-described means, the MIS transistor (Q ₂ ) of the second conductivity type is lower than the source region (10) and the drain region (11) in contact with at least a part of the source region (10) and the drain region (11). Since the impurity introduction portions (10a, 11a) of the second conductivity type having the impurity concentration are formed, the width of the depletion layer at the junction of these impurity introduction portions (10a, 11a) increases,
Accordingly, it is possible to reduce the junction capacitance of the source region (10) and the drain region (11). Moreover, these impurity introduction portions (10a, 11a) are second conductivity type impurity introduction portions (12) for suppressing the spread of the depletion layer.
Since it is formed at the same time, there is no increase in the number of steps.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. This embodiment is an embodiment in which the present invention is applied to the manufacture of a CMOS LSI.

In this embodiment, as shown in FIG. 1A, first, an n-type impurity such as P is selectively ion-implanted into a semiconductor substrate 1 such as a p-type Si substrate.
After the well 2 is formed, the surface of the semiconductor substrate 1 is selectively thermally oxidized to form a field insulating film 3 such as an SiO ₂ film, thereby performing element isolation. The impurity concentration of the semiconductor substrate 1 is, for example, about 10 ¹⁵ to 10 ¹⁶ cm ⁻³ , and the impurity concentration of the n-well 2 is also about the same. Next, a gate insulating film 4 such as a SiO ₂ film is formed on the surface of the active region surrounded by the field insulating film 3 by thermal oxidation. Next, a resist pattern in which a portion corresponding to a region where a high impurity concentration portion is to be formed for suppressing the expansion of a depletion layer described later and a portion corresponding to a region where a source region and a drain region of an n-channel MOSFET described later are to be formed are opened. After the formation of the resist pattern 5, an n-type impurity such as P is selectively ion-implanted into the n-well 2 using the resist pattern 5 as a mask. This ion implantation is performed, for example, under the conditions of an energy of 300 keV and a dose of about 2 × 10 ¹² cm ⁻² . After that, the resist pattern 5 is removed.

Next, as shown in FIG. 1B, for example, a polycrystalline Si film doped with impurities is formed on the entire surface, and then the polycrystalline Si film is patterned into a predetermined shape by etching.
Gate electrodes 6, 7 made of a film are formed. Incidentally, these gate electrodes 6 and 7 can also be constituted by a polycide film in which a high melting point metal silicide film is superposed on a polycrystalline Si film.

Next, first, for example, a p-type impurity such as B is ion-implanted at a high concentration into the n-well 2 of the p-channel MOSFET formation portion while the surface of the n-channel MOSFET formation portion is covered with a resist or the like. An n-type impurity such as As is ion-implanted at a high concentration into the semiconductor substrate 1 of the n-channel MOSFET forming portion by a method. Thereafter, these implanted impurities are electrically activated by performing a heat treatment. Thus, as shown in FIG. 3C, for example, a p ⁺ -type source region 8 and a drain region 9 are formed in a self-alignment manner with respect to the gate electrode 6, and are formed in a self-alignment manner with respect to the gate electrode 7. For example, n ⁺ type source region 10 and drain region 11
Is formed. At the same time, n under the channel region of the p-channel MOSFET has an impurity concentration higher than that of the n-well 2.
A high impurity concentration portion 12 of a mold is formed. The high impurity concentration portion 12 suppresses the expansion of the depletion layer and prevents the short channel effect. The impurity concentration of the high impurity concentration portion 12 is, for example, about 10 ¹⁷ cm ⁻³ . In the present embodiment, the n-channel MO
For example, n ⁻ -type low-impurity-concentration portions 10a and 11a that are in contact with substantially the entire lower portions of the source region 10 and the drain region 11 of the SFET are formed. In this case, the source region 10 and the drain region 11 having a high impurity concentration and the low impurity concentration portions 10a and 11a as a whole function as a source region and a drain region.

The gate electrode 6 is configured p-channel MOSFET Q ₁ by the source region 8 and drain region 9, n-channel by the gate electrode 7, the source region 10 and drain region 11
MOSFETQ ₂ is configured.

FIG. 2, the source region 10 or drain region 11 including a low impurity concentration portions 10a of the above-mentioned n-channel MOSFET Q _2, the 11a
1 shows an example of the impurity concentration distribution in the depth direction of FIG. As shown in FIG. 2, the impurity concentration distribution of the source region 10 or the drain region 11 has two steps due to the formation of the low impurity concentration portions 10a and 11a, and the junction with the semiconductor substrate 1 has It can be seen that the impurity concentration is considerably lower than when the impurity concentration portions 10a and 11a are not formed.

As described above, according to the present embodiment, the p-channel MOSFET
At the same time to form an n-type high impurity concentration portion 12 for suppressing the expansion of the depletion layer in Q _1, the low impurity concentration portion 10a of the n-channel MOSFET Q ₂ of the source region 10 and drain region 11,
11a, these low impurity concentration portions 10a, 1
The width of the depletion layer at the junction 1a is increased, and accordingly, the junction capacitance of these source region 10 and drain region 11 can be reduced. Moreover, since the low impurity concentration portions 10a and 11a are formed simultaneously with the high impurity concentration portions 10a and 11a by a single ion implantation, the number of steps is not increased.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible.

For example, in the above embodiment, the p-channel MOSFET
Has been described to form the high impurity concentration portion 12 for suppressing the expansion of a depletion layer in the lower portion of the channel region of Q _1, the p-type for suppressing the spread of a depletion layer in the lower portion of the channel region of the n-channel MOSFET The present invention can be applied to a case where a high impurity concentration portion is formed. In this case, at the same time as forming the p-type high impurity concentration portion,
A low impurity concentration portion is formed in the source region 8 and the drain region 9 of the p-channel MOSFET. Further, in the above-described embodiment, the case where the present invention is applied to the manufacture of a CMOS LSI has been described. However, the present invention is not limited to a bipolar-CMOS LSI.
Generally, the present invention can be applied to the manufacture of various semiconductor devices having MIS transistors of the first and second conductivity types.

〔The invention's effect〕

As described above, according to the present invention, the first conductivity type
A second conductivity type impurity-introduced portion for suppressing the spread of a depletion layer is formed below the channel region of the MIS transistor, and at the same time, a source region in contact with at least a part of a source region and a drain region of the second conductivity type MIS transistor In addition, since the impurity introduction portion of the second conductivity type having a lower impurity concentration than the drain region is formed, the junction capacitance of the source region and the drain region of the MIS transistor of the second conductivity type can be reduced. There is no additional process.

[Brief description of the drawings]

1A to 1C show a CMOS LSI according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view for explaining a manufacturing method of the CM in the order of steps, and FIG. 2 is a CM manufactured by the manufacturing method shown in FIGS. 1A to 1C.
3A to 3C are graphs showing an example of impurity concentration distribution in the depth direction of a source region or a drain region of an n-channel MOSFET in an OSLSI. FIGS. It is. Description of main symbols in the drawings 1: semiconductor device, 2: n well, 3: field insulating film, 5: resist pattern, 6, 7: gate electrode, 8, 10: source region,
9,11: drain region, 10a, 11a: low impurity concentration portion, Q _1: p-channel MOSFET, Q _2: n-channel MOSFET.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 27/092 H01L 21/8238 H01L 29/78 H01L 21/336

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a first conductivity type MIS transistor and a second conductivity type MIS transistor, wherein a spread of a depletion layer under a channel region of the first conductivity type MIS transistor is suppressed. At the same time as forming the second conductivity type impurity introduction portion for forming the second conductivity type MIS transistor, the second conductivity type MIS transistor has at least a part of the source region and the drain region in contact with at least part of the source region and the drain region. A method for manufacturing a semiconductor device, wherein a conductive type impurity introduction portion is formed.