JPH10242460A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which a MOSFET similar to a MOSFET of an LDD structure can be formed by a simple production process and which comprises a MOSFET whose hot carrier-resistant property is excellent and to provide its manufacturing method. SOLUTION: A manufacturing method is provided with a process wherein a gate insulating film is formed on a semiconductor substrate 1, a gate electrode 4 is formed on it, a thick silicon oxide film 6 is then deposited on the semiconductor substrate 1 and a sidewall silicon oxide film 61 which is composed of the silicon oxide film 6 is formed on the sidewall of the gate electrode 4 and with a process wherein impurities such as arsenic or the like are ion-implanted into the semiconductor substrate 1 through the silicon oxide film 6 by using an ion implantation method, an annealing operation is performed, the ion- implanted impurities are diffused and a semiconductor region 7 as aource/drain is formed so as to have a structure similar to an LDD structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and in particular, to an LDD (Lightly
Doped Drain Structure (MOSFET) (Metal Ox
MOSFETs similar to ide Semiconductor Field Effect Transistor) can be formed by a simple manufacturing process and have excellent hot carrier resistance.
The present invention relates to a semiconductor integrated circuit device having T and a method of manufacturing the same.

[0002]

2. Description of the Related Art The inventor of the present invention has proposed an LDD-structure M
A method for manufacturing a semiconductor integrated circuit device having an OSFET was studied. The following is a technique studied by the present inventors, and the outline is as follows.

That is, a MOSFET having an LDD structure is:
This is a structure for reducing the hot electron effect along with microfabrication.
The electric field of the depletion layer formed here is prevented from increasing by the type diffusion layer.

In a method for manufacturing a semiconductor integrated circuit device having a MOSFET having an LDD structure, a source / drain is formed by two-stage ion implantation. That is,
After a gate insulating film and a gate electrode are formed thereon over a semiconductor substrate, for example, phosphorus (P) as an impurity is ion-implanted into the semiconductor substrate using the gate insulating film as a mask,
An n-type diffusion layer as a low concentration shallow source / drain is formed. Then, a sidewall spacer (sidewall insulating film) made of a silicon oxide film or the like is formed on the sidewall of the gate electrode.
Is formed, using the sidewall spacers and the gate electrode as a mask, phosphorus as an impurity is ion-implanted into the semiconductor substrate to form a high-concentration deep source / drain n-type diffusion layer.

[0005] Incidentally, as a document concerning a method of manufacturing a semiconductor integrated circuit device provided with a MOSFET having an LDD structure, for example, W. Mari published by Keigaku Shuppan Co., Ltd. p216-p2
23.

[0006]

However, the aforementioned L
The method for manufacturing a semiconductor integrated circuit device having a MOSFET having a DD structure requires a large number of manufacturing steps because the source / drain of the MOSFET having an LDD structure is formed by two-stage ion implantation, and therefore, complicated manufacturing is required. There is a problem of becoming a process.

Further, using a gate insulating film and a gate electrode as a mask, for example, phosphorus as an impurity is ion-implanted into a semiconductor substrate to form an n-type diffusion layer as a lightly doped shallow source / drain. When forming a sidewall spacer made of a silicon oxide film or the like on the side wall of the electrode, a CVD (Chemical Va
It is necessary to form an insulating film such as a silicon oxide film using a (por Deposition) method, and then use a lithography technique and a selective etching technique to form a sidewall spacer pattern on the side wall of the gate electrode. Therefore, there is a problem that a complicated manufacturing process is required due to the manufacturing process of forming the sidewall spacer.

An object of the present invention is to provide a MOSFE having an LDD structure.
A MOSFET similar to T can be formed by a simple manufacturing process and has excellent hot carrier resistance.
An object of the present invention is to provide a semiconductor integrated circuit device having an OSFET and a method for manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor integrated circuit device of the present invention, a semiconductor region serving as a source / drain is formed on a semiconductor substrate below a silicon oxide film on a side wall of a gate electrode with a structure similar to an LDD structure. The semiconductor region is formed by using an impurity ion implantation method after the silicon oxide film is formed.

In a method of manufacturing a semiconductor integrated circuit device according to the present invention, after a gate insulating film and a gate electrode are formed on a semiconductor substrate, a thick silicon oxide film is deposited on the semiconductor substrate. Forming a side wall silicon oxide film made of a silicon oxide film on the side wall of the gate electrode, and ion-implanting impurities such as arsenic into the semiconductor substrate through the silicon oxide film using an ion implantation method, followed by annealing. To diffuse the ion-implanted impurities to form a semiconductor region as a source / drain with a structure similar to an LDD structure.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(Embodiment 1) FIGS. 1 to 9 are schematic sectional views showing manufacturing steps of a semiconductor integrated circuit device according to Embodiment 1 of the present invention. The semiconductor integrated circuit device of Embodiment 1 and a method of manufacturing the same will be described with reference to FIG.

First, a semiconductor substrate 1 made of, for example, p-type single-crystal silicon is prepared, and a selective region on the surface of the semiconductor substrate 1 is subjected to thermal oxidation to form an element isolation made of a silicon oxide film. A field insulating film 2 is formed (FIG. 1).

Next, after a gate insulating film 3 made of a silicon oxide film is formed on the surface of the semiconductor substrate 1 by using a thermal oxidation process, the gate insulating film 3 is formed on the semiconductor substrate 1 by using a CVD method.
A gate electrode 4 made of a polycrystalline silicon film containing, for example, phosphorus as an impurity is formed. Then, after a resist film 5 is applied on the semiconductor substrate 1, a patterned resist film 5 as an etching mask for forming a pattern of the gate electrode 4 and the gate insulating film 3 is formed by using a lithography technique. (FIG. 2). In this case, before forming the gate insulating film 3, if necessary,
In order to adjust the threshold voltage of the MOSFET, a mode in which a p-type impurity such as boron (B) is ion-implanted into the semiconductor substrate 1 by using an ion implantation method can be adopted.

Thereafter, using the resist film 5 as an etching mask, a pattern of the gate electrode 4 and the gate insulating film 3 is formed by using a selective etching technique such as dry etching. Next, on the semiconductor substrate 1,
A thick silicon oxide film 6 is deposited by using the CVD method, and a silicon oxide film 6 having a side wall silicon oxide film on the side wall of the gate electrode 4 is formed (FIG. 3).

In this case, the thickness of the silicon oxide film 6 is 0.1
1 μm or more, and in the case of the first embodiment, 0.1 μm.
m. Therefore, the silicon oxide film 6 according to the first embodiment has a thickness larger than that of the conventional sidewall silicon oxide film because the thickness of the sidewall silicon oxide film in the conventional MOSFET having the LDD structure is about 0.01 μm. It is a silicon film 6. In addition, a thick silicon oxide film 6 is deposited by using the CVD method, and a sidewall silicon oxide film made of the silicon oxide film is formed on the sidewall of the gate electrode 4, so that a sidewall having a predetermined thickness is formed. The silicon oxide film can be automatically formed in a state of being self-aligned with the pattern of the gate electrode 4.

Next, a resist and a film 1 are formed on the semiconductor substrate 1.
1 is applied, the surface layer of the silicon oxide film 6 is removed using lithography technology and selective etching technology, and the side wall silicon oxide film 6a (which is thinner than the silicon oxide film 6) A thin silicon oxide film 6b is formed on the side wall silicon oxide film 6a) and the semiconductor substrate 1 (FIG. 4).

After removing the unnecessary resist and the film 11, the semiconductor substrate 1 is passed through the silicon oxide film 6.
First, arsenic as an impurity (A
s) is ion-implanted with an energy of 200 keV and an ion implantation amount of 5 × 10 ¹⁵ cm ⁻² . Thereafter, annealing (thermal diffusion processing) is performed to diffuse the ion-implanted arsenic to form an n-type semiconductor region 7 as a source / drain (FIG. 5).

As another embodiment of this manufacturing process, arsenic (As) as an impurity is implanted into the semiconductor substrate 1 through the silicon oxide film 6 in the state of the silicon oxide film 6 shown in FIG. ) May be implanted with an energy of 200 keV and an ion implantation amount of 5 × 10 ¹⁵ cm ⁻² .

According to the study results of the present inventor, the thickness of the silicon oxide film 6 is set to 0.1 μm or more, and the energy for ion-implanting impurities is 100 keV according to the thickness of the silicon oxide film 6. The embodiment described above can be applied.

By the above-described manufacturing process, the gate electrode 4
Substrate 1 under sidewall silicon oxide film 6a
The semiconductor region 7 having a pattern similar to that of the conventional MOSFET having the LDD structure can be formed in this region.

FIG. 10 is a graph showing the results examined by the present inventors. In the arsenic ion implantation, the thickness of the silicon oxide film corresponding to the silicon oxide film 6 in the first embodiment, FIG. 9 is a graph showing a relationship between a semiconductor region corresponding to a semiconductor region 7 as a drain and a distance in a lateral direction or a depth direction.

FIG. 11 is a graph showing the results examined by the present inventor. In the arsenic ion implantation, the lateral direction of the semiconductor region corresponding to the semiconductor region 7 as the source / drain under the side wall silicon oxide film is shown. FIG. 7 is a graph showing a relationship between a distance of the semiconductor region and a lateral impurity concentration of the semiconductor region corresponding to the semiconductor region 7 as a source / drain. In FIG. 11, P (conventional) indicates phosphorus (P) which is an impurity of a semiconductor region as a source / drain in a conventional MOSFET having an LDD structure.

Therefore, as a result of the study by the present inventor, the conventional LDD can be obtained by ion-implanting arsenic with an energy of 200 keV in a state where the thick silicon oxide film 6 having a thickness of 0.1 μm is formed. MOSFET structure
Compared to the case where arsenic is ion-implanted with an energy of 120 keV in a state where a sidewall silicon oxide film having a
, The distance in the depth direction is almost the same, and the distance in the lateral direction is 0.2 μm at 200 keV, which can be larger than 0.12 μm at 120 keV.

As a result of the study by the present inventor, the conventional LD
Compared with the concentration distribution of phosphorus in a semiconductor region in which phosphorus is used as an impurity used in a MOSFET having a D structure, the conventional specification makes the hot carrier resistance worse due to the steep concentration distribution. ing. However, in the case of the first embodiment, arsenic is reduced to 20.
By implanting ions at an energy of 0 keV, the concentration distribution in the lateral direction of the semiconductor region and the concentration distribution of the semiconductor region 7 of the first embodiment in the case where phosphorus used in a conventional MOSFET having an LDD structure is used as an impurity. Is substantially the same as that of the above, whereby the hot carrier resistance can be improved.

Next, an insulating film 8 made of, for example, a silicon oxide film is formed on the semiconductor substrate 1 by using the CVD method (FIG. 6). Then, for example, CMP (Chemical Mecha)
The surface of the insulating film 8 is planarized by removing the insulating film 8 in the surface layer portion by using a polishing technique such as nical polishing (chemical mechanical polishing) (FIG. 7).

After that, a connection hole is formed in a selective region of the insulation film 8 by using the lithography technique and the selective etching technique, and then the connection hole is formed by using a selective CVD method. For example, the plug 9 is formed by burying tungsten or the like (FIG. 8).

Next, after a wiring layer 10 made of, for example, an aluminum layer is formed on the semiconductor substrate 1 by using a sputtering method, a patterned wiring is formed by using a lithography technique and a selective etching technique. The layer 10 is formed (FIG. 9).

Thereafter, an interlayer insulating film and a wiring layer are laminated on the semiconductor substrate 1 as necessary using a manufacturing process of the interlayer insulating film and the wiring layer, and then a passivation film is formed. Thereby, the manufacturing process of the semiconductor integrated circuit device is completed.

In the above-described semiconductor integrated circuit device of Embodiment 1 and the method of manufacturing the same, after forming the patterns of the gate electrode 4 and the gate insulating film 3, the semiconductor substrate 1
A thick silicon oxide film 6 having a thickness of 0.1 μm or more is deposited thereon, and a silicon oxide film 6 having a side wall silicon oxide film on the side wall of the gate electrode 4 is formed.
Arsenic as an impurity is ion-implanted into the semiconductor substrate 1 through the silicon oxide film 6 using an ion implantation method with an energy of 100 keV or more and an ion implantation amount of 5 × 10 ¹⁵ cm ⁻² to form a source / drain. The n-type semiconductor region 7 is formed.

Therefore, the MOSFE of the first embodiment
The semiconductor region 7 as the source / drain of T
A high-performance and high-reliability MOSFET can be obtained because a source / drain composed of a single semiconductor region having excellent hot carrier resistance can be obtained by being able to have a structure similar to a MOSFET having a structure.
Semiconductor integrated circuit device having the following.

In the semiconductor region 7 as the source / drain of the MOSFET according to the first embodiment, a thick silicon oxide film 6 having a thickness of 0.1 μm or more is deposited, and a sidewall is formed on the sidewall of the gate electrode 4. A silicon oxide film 6 having a silicon oxide film is formed, and then arsenic as an impurity is ion-implanted into the semiconductor substrate 1 through the silicon oxide film 6 at an energy of 100 keV or more by 5 ×.
It is formed by ion implantation with an ion implantation amount of 10 ¹⁵ cm ^-2 . As a result, the MOSFE of the first embodiment
The semiconductor region 7 as a source / drain of T is formed by using a single ion implantation method.
Is formed, a simple manufacturing process can be realized.

(Embodiment 2) FIGS. 12 to 20 are schematic sectional views showing the steps of manufacturing a semiconductor integrated circuit device according to Embodiment 2 of the present invention. The semiconductor integrated circuit device according to the second embodiment and a method for manufacturing the same will be described with reference to FIG.

First, a semiconductor substrate 1 made of, for example, p-type single crystal silicon is prepared, and a selective region on the surface of the semiconductor substrate 1 is subjected to thermal oxidation treatment to form an element isolation made of a silicon oxide film. The field insulating film 2 is formed (FIG. 12).

Next, after a gate insulating film 3 made of a silicon oxide film is formed on the surface of the semiconductor substrate 1 by using a thermal oxidation process, the gate insulating film 3 is formed on the semiconductor substrate 1 by using a CVD method.
A gate electrode 4 made of a polycrystalline silicon film containing, for example, phosphorus as an impurity is formed. Then, after a resist film 5 is applied on the semiconductor substrate 1, a patterned resist film 5 as an etching mask for forming a pattern of the gate electrode 4 and the gate insulating film 3 is formed by using a lithography technique. To form In this case, before the gate insulating film 3 is formed, if necessary, a MOSF
In order to adjust the threshold voltage of ET, the semiconductor substrate 1
A mode in which a p-type impurity such as boron is ion-implanted by using an ion implantation method can be employed.

Next, using the resist film 5 as an etching mask, the peripheral portion of the gate electrode 4 is formed as an inclined pattern by a selective etching technique such as anisotropic etching. Thereafter, using the gate electrode 4 as an etching mask, a pattern of the gate insulating film 3 is formed by a selective etching technique such as dry etching (FIG. 1).
3).

In this case, the peripheral portion of the gate electrode 4 is formed as a slanted pattern, so that L
When a semiconductor region as a source / drain having a structure similar to the DD structure is formed by using an impurity ion implantation method, a semiconductor region having a specific shape can be formed.

Next, after removing the unnecessary resist film 5, a thick silicon oxide film 6 is deposited on the semiconductor substrate 1 by using the CVD method, and a side wall is formed on the side wall of the gate electrode 4. A silicon oxide film 6 including a silicon oxide film is formed (FIG. 14).

In this case, the thickness of the silicon oxide film 6 is set to 0.
1 μm or more, and in the case of the second embodiment, 0.1 μm.
m. Therefore, the silicon oxide film 6 according to the second embodiment has a larger thickness than the conventional sidewall silicon oxide film because the thickness of the sidewall silicon oxide film in the conventional MOSFET having the LDD structure is about 0.01 μm. It is a silicon film 6.

Further, since the peripheral portion of the gate electrode 4 has an inclined pattern, the state of the silicon oxide film 6 deposited in that region corresponds to the inclined pattern of the peripheral portion of the gate electrode 4. The silicon oxide film 6 can be inclined.

Next, a resist and a film 1 are formed on the semiconductor substrate 1.
1 is applied, using a lithography technique and a selective etching technique, a side wall silicon oxide film 6a on the side wall of the gate electrode 4 and a thin silicon oxide film 6 on the semiconductor substrate 1.
b is formed (FIG. 15).

Then, after removing the unnecessary resist and the film 11, the semiconductor substrate 1 is passed through the silicon oxide film 6.
Then, using arsenic as an impurity by ion implantation,
Ion implantation is performed with an energy of 00 keV and an ion implantation amount of 5 × 10 ¹⁵ cm ⁻² . After that, annealing is performed to diffuse the ion-implanted arsenic,
An n-type semiconductor region 7 as a drain is formed (FIG. 1).
6).

As another mode of this manufacturing process, arsenic as an impurity is implanted into the semiconductor substrate 1 through the silicon oxide film 6 in the state of the silicon oxide film 6 shown in FIG. Energy of 5 × 1
The ion implantation may be performed at an ion implantation amount of 0 ¹⁵ cm ^-2 .

By the above-described manufacturing process, the gate electrode 4
Substrate 1 under sidewall silicon oxide film 6a
In this region, an n-type semiconductor region 7 having a pattern similar to that of the conventional MOSFET having the LDD structure can be formed.

Further, since the peripheral portion of the gate electrode 4 is inclined, the variation in the thickness of the side wall silicon oxide film 6a on the side wall of the gate electrode 4 can be reduced during mass production of the semiconductor integrated circuit device. Moreover, when the semiconductor region 7 similar to the LDD structure is formed, the semiconductor region 7 can be automatically formed in a state of being self-aligned with the pattern of the gate electrode 4.

Further, since the peripheral portion of the gate electrode 4 is inclined, the semiconductor region 7 is formed below the sidewall silicon oxide film 6a on the side wall of the gate electrode 4 and below the peripheral portion of the gate electrode 4. Can be an excellent LDD
A semiconductor region 7 having a similar structure can be obtained.

When the semiconductor region 7 as the source / drain is formed, similarly to the first embodiment,
By implanting arsenic with an energy of 200 keV, hot carrier resistance can be improved.

Next, an insulating film 8 made of, for example, a silicon oxide film is formed on the semiconductor substrate 1 by using the same manufacturing process as in the first embodiment (FIG. 17). Then, the surface of the insulating film 8 is planarized by removing the insulating film 8 in the surface layer portion by using a polishing technique such as a CMP method (FIG. 18).

Thereafter, using a manufacturing process similar to that of the first embodiment described above, a connection hole is formed in a selective region of the insulating film 8, and a plug 9 is formed in the connection hole (FIG. 1).
9).

Next, the wiring layer 10 is formed on the semiconductor substrate 1 by using the same manufacturing steps as in the first embodiment (FIG. 20).

Thereafter, an interlayer insulating film and a wiring layer are laminated on the semiconductor substrate 1 as necessary using a manufacturing process of the interlayer insulating film and the wiring layer, and then a passivation film is formed. Thereby, the manufacturing process of the semiconductor integrated circuit device is completed.

According to the semiconductor integrated circuit device and the method of manufacturing the same according to the second embodiment, since the peripheral portion of gate electrode 4 is formed as an inclined pattern, the silicon oxide deposited on that region is formed. The state of the film 6 can be a graded silicon oxide film 6 corresponding to the graded pattern at the periphery of the gate electrode 4.

Therefore, an n-type semiconductor region 7 having a pattern similar to that of a conventional MOSFET having an LDD structure can be formed in the region of the semiconductor substrate 1 below the side wall silicon oxide film 6a on the side wall of the gate electrode 4.

Since the peripheral portion of the gate electrode 4 is inclined, the variation in the thickness of the side wall silicon oxide film 6a on the side wall of the gate electrode 4 can be reduced during mass production of the semiconductor integrated circuit device. Moreover, when the semiconductor region 7 similar to the LDD structure is formed, the semiconductor region 7 can be automatically formed in a state of being self-aligned with the pattern of the gate electrode 4.

Further, since the peripheral portion of the gate electrode 4 is inclined, the semiconductor region 7 is formed below the sidewall silicon oxide film 6a on the side wall of the gate electrode 4 and below the peripheral portion of the gate electrode 4. Can be an excellent LDD
A semiconductor region 7 having a similar structure can be obtained.

The semiconductor region 7 as the source / drain of the MOSFET according to the second embodiment has a source / drain composed of a single semiconductor region having excellent hot carrier resistance, as in the first embodiment. High performance and high reliability MOS
A semiconductor integrated circuit device having an FET can be obtained.

Further, the semiconductor region 7 as the source / drain of the MOSFET according to the second embodiment is similar to the semiconductor region 7 as the source / drain of the MOSFET according to the first embodiment. By using the method to form the semiconductor region 7 as the source / drain having a structure similar to the MOSFET having the LDD structure, a simple manufacturing process can be achieved.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, according to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, when forming an n-type semiconductor region as an impurity for forming a semiconductor region as a source / drain, an n-type An impurity can be used, and a p-type impurity such as boron can be used when forming a p-type semiconductor region.

Further, the present invention relates to a MOSFET, a CMOS,
A semiconductor integrated circuit device in which various semiconductor elements such as an FET and a bipolar transistor are combined and a method for manufacturing the same can be provided.

Further, the present invention relates to a MOSFET, a CMO
D composed of SFET, BiCMOSFET, etc.
RAM (Dynamic Random Access Memory), SRAM
(Static Random Access Memory) or various semiconductor integrated circuit devices having a logic system or the like and a method of manufacturing the same.

[0064]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, the semiconductor region as the source / drain of the MOSFET is a MOSFET having an LDD structure.
A semiconductor integrated circuit device having a high-performance and high-reliability MOSFET can be formed as a source / drain composed of a single semiconductor region having excellent hot carrier resistance by having a structure similar to that described above. It can be.

(2). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, a semiconductor region as a source / drain of a MOSFET is formed as a source / drain having a structure similar to a MOSFET of an LDD structure by using a single ion implantation method. By forming the semiconductor region described above, a simple manufacturing process can be achieved.

(3). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, since the peripheral portion of the gate electrode is formed as an inclined pattern, the state of the silicon oxide film deposited in that region can be changed to the peripheral portion of the gate electrode. It can be a graded silicon oxide film corresponding to the graded pattern of the part.

Therefore, the conventional LDD is formed in the region of the semiconductor substrate below the side wall silicon oxide film on the side wall of the gate electrode.
A semiconductor region having a pattern similar to that of a MOSFET having a structure can be formed.

Further, since the peripheral portion of the gate electrode is inclined, when mass-producing the semiconductor integrated circuit device,
Variations in the thickness of the side wall silicon oxide film on the side wall of the gate electrode can be reduced, and when a semiconductor region similar to an LDD structure is formed, it is automatically formed in a state of being self-aligned with the gate electrode pattern. be able to.

Further, since the peripheral portion of the gate electrode is inclined, a semiconductor region can be formed below the side wall silicon oxide film on the side wall of the gate electrode and below the peripheral portion of the gate electrode. Semiconductor region similar to the LDD structure.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 3 is a schematic sectional view showing a manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 4 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 5 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 7 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 8 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 10 is a graph showing the results examined by the present inventor. In the arsenic ion implantation, the thickness of the silicon oxide film corresponding to the silicon oxide film in this embodiment and the semiconductor region as a source / drain are shown. FIG. 7 is a graph showing a relationship between a semiconductor region and a distance in a lateral direction or a depth direction corresponding to FIG.

FIG. 11 is a graph showing the results examined by the present inventor. In the arsenic ion implantation, the lateral distance of the semiconductor region corresponding to the semiconductor region as the source / drain below the sidewall silicon oxide film, and FIG. 4 is a graph showing a relationship between a semiconductor region as a source / drain and a lateral impurity concentration of the semiconductor region corresponding to the semiconductor region;

FIG. 12 is a schematic cross-sectional view showing a manufacturing step of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 13 is a schematic cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 14 is a schematic cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 15 is a schematic sectional view showing a manufacturing step of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 16 is a schematic sectional view showing a manufacturing step of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 17 is a schematic sectional view showing a manufacturing step of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 18 is a schematic sectional view showing a manufacturing step of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 19 is a schematic sectional view showing a manufacturing step of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 20 is a schematic sectional view showing a manufacturing step of a semiconductor integrated circuit device according to another embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 field insulating film 3 gate insulating film 4 gate electrode 5 resist film 6 silicon oxide film 6a sidewall silicon oxide film 6b silicon oxide film 7 semiconductor region 8 insulating film 9 plug 10 wiring layer 11 resist film

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hitoko Aoyama 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd.

Claims (8)

[Claims] A semiconductor region serving as a source / drain is formed on a semiconductor substrate below a silicon oxide film on a side wall of a gate electrode with a structure similar to an LDD structure, and the semiconductor region is formed of the silicon oxide. A semiconductor integrated circuit device formed by using an impurity ion implantation method after a film is formed. 2. The semiconductor integrated circuit device according to claim 1, wherein said semiconductor region contains arsenic as an impurity.
A semiconductor integrated circuit device formed by ion implantation with energy of keV or more. 3. The semiconductor integrated circuit device according to claim 1, wherein said semiconductor region is a single semiconductor region having hot carrier resistance. Forming a gate insulating film on the semiconductor substrate and a gate electrode thereon; depositing a thick silicon oxide film on the semiconductor substrate; Forming a sidewall silicon oxide film made of a silicon film, and ion-implanting impurities into the semiconductor substrate through the silicon oxide film using an ion implantation method;
Forming a semiconductor region as a source / drain by annealing to diffuse the ion-implanted impurity, thereby forming a semiconductor region as a source / drain. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein in the step of forming a gate insulating film on the semiconductor substrate and a gate electrode thereon, the peripheral portion of the gate electrode is inclined. A method for manufacturing a semiconductor integrated circuit device, wherein the method is formed as a patterned pattern. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein a thick silicon oxide film is deposited on said semiconductor substrate, and said silicon oxide film is formed on a side wall of said gate electrode. Forming a silicon oxide film on the side wall of the gate electrode using a lithography technique and a selective etching technique after depositing the silicon oxide film on the semiconductor substrate. And removing a surface layer of the silicon oxide film on the semiconductor substrate. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein impurities are implanted into said semiconductor substrate through said silicon oxide film by ion implantation. A semiconductor integrated circuit, wherein the thickness of the silicon oxide film is 0.1 μm or more at the time of ion implantation, arsenic is used as the impurity, and the energy in the ion implantation method is 100 keV or more. Device manufacturing method. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein an impurity is implanted into said semiconductor substrate through said silicon oxide film by ion implantation. A method for manufacturing a semiconductor integrated circuit device, wherein an n-type impurity such as phosphorus or a p-type impurity such as boron is used as the impurity during the ion implantation.