JPH09246535A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain a leakage current between source and drain regions by providing a semiconductor region whereto impurities whose conductivity is reverse to that of impurities introduced to a source region and a drain region between a source region and a drain region of an MIS transistor. SOLUTION: A semiconductor region 5a is formed in a position apart from a source region 4a and a drain region 4d below a channel region 4c in an nMOS 4. Furthermore, p<+> -type boron whose conductivity type is reverse to that of the source region 4s and the drain region 4d is incorporated in the semiconductor region 5a and its impurity concentration is about 1×10<18> to 1×10<19> /cm<3> , for example. A depth of the semiconductor region 5a is approximately equal to a depth of the source region 4s and the drain region 4d. A leakage current between the source region 4s and the drain region 4d can be restrained even if a gate length is short by providing such a semiconductor region 5a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and more particularly to a MIS (Metal In
sulator Semiconductor) The present invention relates to a technology effectively applied to a technology for suppressing a leak current between a source and a drain of a transistor.

[0002]

2. Description of the Related Art Since miniaturization of MIS transistors is effective for improving the degree of integration and driving capability of MIS transistors, miniaturization has been rapidly advanced in recent years.

However, while the MIS transistor is miniaturized, the power supply voltage is constant and the electric field strength inside the element is increased. As a result, various problems such as a short channel effect which adversely affect the element characteristics occur. are doing.

The short channel effect is such that as the channel length is shortened, the influence of the drain voltage also extends directly below the gate electrode, so that the potential on the surface of the semiconductor substrate is lowered, and the fluctuation (decrease) of the threshold voltage and the execution channel. This is a phenomenon that has various adverse effects such as a decrease in length.

When the short channel effect becomes more significant, there arises a problem that the drain current cannot be controlled by the gate voltage, that is, so-called punch through occurs, and the leak current between the source and the drain increases. This punch-through is performed, for example, by using a DRAM (Dynamic Random Access).
In the transfer gate of the memory, the storage retention is deteriorated.

A technique for avoiding such a problem is as follows.
For example, a technique is disclosed in which a semiconductor region having a high impurity concentration of the same conductivity type as an impurity of a channel is provided so as to overlap with the source region and the drain region at the channel-side ends of the source region and the drain region of the MIS transistor. Note that such a punch-through suppressing technique is described in, for example, Japanese Patent Application Laid-Open No. 5-136404.

[0007]

However, in the above technique, in which the semiconductor region for suppressing the leakage current is provided so as to overlap with the channel side ends of the source region and the drain region of the MIS transistor, the leakage current between the source and the drain is suppressed. The present inventor has found that it is effective but has the following problems.

That is, in the case of the above technique, since the source region and the drain region overlap with the leakage current suppressing semiconductor region, the depletion formed between the source region and the drain region and the leakage current suppressing semiconductor region. As a result of the narrow width of the layer, there is a problem that the diffusion capacitance increases and the improvement of the device operation speed is hindered.

It is an object of the present invention to provide a technique capable of suppressing a leak current between a source region and a drain region in a semiconductor integrated circuit device having a fine MIS transistor without causing an increase in capacitance. is there.

Another object of the present invention is to provide a technique capable of realizing a fine semiconductor integrated circuit device having a MIS transistor capable of stable operation at high speed.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In the semiconductor integrated circuit device of the present invention, between the source region and the drain region of the MIS transistor provided on the semiconductor substrate, a position separated from the source region, the drain region and the channel region above the semiconductor substrate is provided. In order to prevent a leak current from flowing between the source region and the drain region, a semiconductor region in which an impurity having a conductivity type opposite to that of the impurity introduced in the source region and the drain region is introduced is provided.

Further, in the semiconductor integrated circuit device of the present invention, the semiconductor region is provided at a central position between the source region and the drain region.

Further, in the semiconductor integrated circuit device of the present invention, the semiconductor region is provided at a position displaced from the central position between the source region and the drain region toward the drain region side.

The method for manufacturing a semiconductor integrated circuit device of the present invention includes the following steps in the manufacturing process for the semiconductor integrated circuit device.

(A) A step of forming a gate electrode of a MIS transistor on a semiconductor substrate.

(B) A step of forming a source region and a drain region by introducing an impurity of a predetermined conductivity type into the semiconductor substrate.

(C) After exposing the formation region of the source region and the formation region of the drain region, a source electrode and a drain electrode made of a conductive film having an inclined surface on the gate electrode side are formed on the formation region. Forming process.

(D) What is the conductivity type of impurities in the source and drain regions using the gate electrode, the source electrode and the drain electrode as a mask in order to form a semiconductor region between the source region and the drain region of the MIS transistor? A step of implanting impurities of opposite conductivity type into the main surface of the semiconductor substrate from an oblique direction.

In the method of manufacturing a semiconductor integrated circuit device of the present invention, in the manufacturing process of the semiconductor integrated circuit device,
In the ion implantation process from the oblique direction for forming the semiconductor region, the implantation angle is set to an angle at which channeling occurs.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the manufacturing process of the semiconductor integrated circuit device,
The source region and the drain region are formed by impurity diffusion from the source electrode and the drain electrode.

The method for manufacturing a semiconductor integrated circuit device of the present invention includes the following steps in the manufacturing process for the semiconductor integrated circuit device.

(A) Before forming the gate electrode of the MIS transistor, after ion-implanting an impurity having a conductivity type opposite to that of the impurities in the source region and the drain region perpendicularly to the main surface of the semiconductor substrate, A step of forming a semiconductor layer for forming the semiconductor region at a predetermined depth position of the semiconductor substrate by subjecting the semiconductor substrate to heat treatment.

(B) A step of forming a gate electrode of a MIS transistor on a semiconductor substrate.

(C) Impurities having a conductivity type opposite to that of the semiconductor layer are ion-implanted into the semiconductor substrate so that the conductivity type of the semiconductor layer is canceled by using the gate electrode as a mask, whereby the semiconductor substrate below the gate electrode. Forming the semiconductor region.

(D) A step of forming a source region and a drain region by introducing an impurity of a predetermined conductivity type into the semiconductor substrate.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings (note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments. , The repeated explanation is omitted).

(Embodiment 1) FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2A shows a case where a semiconductor region for suppressing a leak current is provided. A graph showing the relationship between the gate length and the threshold voltage,
2B is a graph showing the relationship between the gate length and the threshold voltage when the semiconductor region for suppressing the leak current is not provided, and FIG. 3 is a graph showing the impurity concentration distribution in the depth direction of the semiconductor substrate, 4 to 7 are cross-sectional views of essential parts in the manufacturing process of the semiconductor integrated circuit device of FIG. 1, and FIG. 8 is an explanatory diagram of an application example of the semiconductor integrated circuit device of FIG.

The semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

The semiconductor substrate 1 is made of, for example, p ⁻ -type silicon (Si) single crystal, and has an impurity concentration of, for example, 1
It is about 10 ¹⁵ / cm ³ . A p well 2p is formed in the upper layer of the semiconductor substrate 1. The p well 2p contains, for example, p-type impurity boron, and the impurity concentration thereof is, for example, about 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ .

A field insulating film 3 for element isolation is selectively formed on the semiconductor substrate 1. The field insulating film 3 is made of, for example, silicon dioxide (SiO ₂ ).
The element forming region surrounded by the
Channel type MOS ・ FET (Metal Oxide Semiconducer)
A tor field effect transistor (hereinafter referred to as nMOS) 4 is formed.

The nMOS 4 includes a source region 4s and a drain region 4d formed on the semiconductor substrate 1,
It has a channel region 4c formed between them, a gate insulating film 4i formed on the semiconductor substrate 1, and a gate electrode 4g formed thereon.

Source region 4s and drain region 4d
Is a low concentration region 4s1 formed on the side of the channel region 4c.
4d1 and high concentration regions 4s2, 4d provided outside thereof
And 2.

Both the low concentration regions 4s1 and 4d1 and the high concentration regions 4s2 and 4d2 contain, for example, n-type impurities such as phosphorus or arsenic (As). Low concentration area 4s
The impurity concentration of 1.4d1 is, for example, 1 × 10 ¹⁸ to 1 × 10
It is about ¹⁹ / cm ³ . The impurity concentration of the high concentration regions 4s2 and 4d2 is, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . The depth (center of Gaussian distribution) of the high concentration regions 4s2, 4d2 is, for example, about 0.15 μm.

Source region 4s and drain region 4d
Are the source electrode 4st and the drain electrode 4d, respectively.
It is electrically connected to t. The source electrode 4st and the drain electrode 4dt are made of, for example, low resistance polysilicon, and the side surface on the side of the gate electrode is inclined.

The channel region 4c is provided between the source region 4s and the drain region 4d, is a conductive path of carriers flowing between the source region 4s and the drain region 4d, and applies a predetermined voltage to the gate electrode 4g. It is formed. The gate length (Lg) is, for example, 0.2 μm
It is about 0.4 μm.

The gate insulating film 4i is made of, for example, SiO ₂ . The gate electrode 4g is made of low resistance polysilicon, for example. However, the structure of the gate electrode 4g is not limited to the single-layer structure of low-resistance polysilicon and can be variously modified. For example, a single-layer gate structure of only tungsten may be used, or for example, a low-resistance polysilicon film may be formed. A polycide structure formed by depositing a tungsten silicide film may be used.

Sidewalls 4sw for forming the LDD structure are formed on the side surfaces of the gate electrode 4g. The sidewall 4sw is made of, for example, SiO ₂ .

By the way, in the first embodiment, a leakage current flows between the source region 4s and the drain region 4d at a position below the channel region 4c in the nMOS 4 and apart from the source region 4s and the drain region 4d. The semiconductor region 5 for suppressing the leakage current is formed to suppress the leakage current.

This semiconductor region 5 contains p + -type boron having a conductivity type opposite to that of the source region 4s and the drain region 4d, and the impurity concentration thereof is, for example, 1
It is about × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ . In addition, the depth of the semiconductor region 5 (center of Gaussian distribution) is equal to that of the source region 4.
s and depth of drain region 4d (center of Gaussian distribution)
Is approximately equal to, for example, about 0.15 μm.

By providing such a semiconductor region 5, even if the gate length (Lg) becomes short, the source region 4s
Since the leak current between the drain region 4d and the drain region 4d can be suppressed, it is possible to suppress the change in the threshold voltage of the nMOS 4 caused by the leak current.

2A and 2B show the relationship between the threshold voltage and the gate length when the semiconductor region 5 is provided (this embodiment) and when it is not provided.
In the present embodiment ((a) in the figure), the threshold voltage is substantially constant. On the other hand, in the case of the technology in which the semiconductor region for suppressing the leakage current is not provided ((b) in the same figure), it can be seen that the threshold voltage becomes extremely low when the gate length becomes short.

Further, the semiconductor region 5 for preventing leakage current
Is provided at a position separated from the source region 4s and the drain region 4d, the width of the depletion layer between the source region 4s and the drain region 4d and the leakage current preventing semiconductor region 5 can be widened. , The source region 4s and the drain region 4 without increasing the diffusion capacitance.
It is possible to suppress the leak current between d.

The difference in diffusion capacitance between the present embodiment and the case where the leakage current suppressing semiconductor region is provided so as to overlap the source region and the drain region will be described with reference to FIG.
The solid line in the figure shows the present embodiment, and the chain double-dashed line shows the case where a semiconductor region for leak current suppression is overlapped with the source region or the like.
The solid line and the chain double-dashed line show the impurity distribution at the same position on the semiconductor substrate.

In the case of the chain double-dashed line, the width d0 of the depletion layer is narrow.
That is, since the diffusion capacitance is inversely proportional to the width of the depletion layer, it can be seen that the diffusion capacitance increases. On the other hand, in the case of the solid line (the present embodiment), the width d1 of the depletion layer is wide, so that it can be seen that the diffusion capacitance becomes small.

Such an nMOS 4 and source electrode 4st
As shown in FIG. 1, the drain electrode 4dt is covered with an interlayer insulating film 6a made of, for example, BPSG (Boro Phospho Silicate Glass). Interlayer insulation film 6
The upper surface of a is flattened.

On the interlayer insulating film 6a, a first layer wiring 7a made of, for example, aluminum (Al) -Si-copper (Cu) alloy or tungsten is formed. The first layer wiring 7a is formed by connecting the source electrode 4st and the drain electrode 4 through the connection hole 8a formed at a predetermined position of the interlayer insulating film 6a.
It is electrically connected to dt.

On the interlayer insulating film 6a, for example, Si
An interlayer insulating film 6b made of O ₂ is deposited, which covers the first layer wiring 7a. A second layer wiring 7b made of, for example, an Al-Si-Cu alloy or tungsten is formed on the upper surface of the interlayer insulating film 6b. On the interlayer insulating film 6b, for example, SiO ₂
A surface protective film 9 made of is deposited and covers the second layer wiring 7b.

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

[0051] First, as shown in FIG. 4, p ^- by boron p-type impurity into the nMOS formation region in the form of the semiconductor substrate 1 is introduced by ion implantation or the like, p-well 2p
To form

The dose of impurities at this time is, for example, 1 ×.
The implantation energy is about 10 ¹³ / cm ² , and the implantation energy is about 60 keV, for example. The heat treatment temperature for forming the p well 2p is, for example, about 1200 ° C., and the treatment time is
For example, it is about 3 hours.

Then, in the element isolation region of the semiconductor substrate 1,
For example, the field insulating film 3 made of SiO _{2 is} formed by LOCO
After being selectively formed by the S (Local Oxidation of Silicon) method or the like, the gate insulating film 4i is formed in the element formation region surrounded by the field insulating films 3 and 3 on the semiconductor substrate 1.
Is formed by a thermal oxidation method or the like.

After that, a conductor film made of, for example, low-resistance polysilicon is formed on the semiconductor substrate 1 by the CVD method or the like, and then the conductor film is patterned by the photolithography technique, the dry etching method or the like, whereby the gate insulating film is formed. A gate electrode 4g is formed on 4i.

Then, using the gate electrode 4g as a mask, in order to form the low-concentration regions 4s1 and 4d1 of the source region and the drain region in the nMOS formation region, for example, n-type impurity phosphorus or As is ion-implanted. Introduce. The dose amount of impurities at this time is, for example, 1 × 1.
The implantation energy is, for example, about 0 ¹³ / cm ² , and the implantation energy is, for example, about 40 keV.

Subsequently, for example, SiO 2 is formed on the semiconductor substrate 1.
After depositing an insulating film made of ₂ by the CVD method or the like, the insulating film is etched back by the dry etching method or the like to form the sidewall 4sw on the side wall of the gate electrode 4g as shown in FIG.

Then, using the gate electrode 4g and the sidewall 4sw as a mask, an nMOS formation region is formed.
High concentration regions 4s2 and 4d of the source region and the drain region
To form 2, for example, the n-type impurity phosphorus or A
s is introduced by an ion implantation method or the like. The dose amount of impurities at this time is, for example, about 1 × 10 ¹⁵ / cm ² ,
The implantation energy is, for example, about 50 keV.

Then, as shown in FIG.
After removing the insulating film on the drain region 4d and the drain region 4d, a source electrode 4st and a drain electrode 4dt made of low-resistance polysilicon having a film thickness of about 100 nm are formed on the source region 4s and the drain region 4d by an epitaxial growth method or the like. To do.

At this time, an inclination is formed on the side surfaces of the source electrode 4st and the drain electrode 4dt. The conditions during this epitaxial growth are as follows, for example. That is, the processing temperature is, for example, 75
0 ° C to 850 ° C, the processing time is, for example, 1 minute to 5 minutes, and the processing gas is, for example, dichlorosilane (SiH ₂ Cl).
₂ ) It is gas.

Subsequently, as shown in FIG. 7, the semiconductor substrate 1
In order to form the semiconductor region 5 for suppressing the leak current,
Gate electrode 4g, sidewall 4sw, source electrode 4
Using the st and drain electrodes 4dt as a mask, p-type impurity boron is introduced into the semiconductor substrate 1 from an oblique direction by an ion implantation method or the like. At this time, the dose amount of impurities is, for example, about 1 × 10 ¹³ / cm ² , and the implantation energy is, for example, about 100 KeV.

In this way, the leakage current suppressing semiconductor region 5 is formed in the center position of the source region 4s and the drain region 4d of the semiconductor substrate 1 in a self-aligned manner.

As a result, it becomes possible to make the formation position, size, etc. of the semiconductor region 5 highly accurate, and therefore n
It becomes possible to form the semiconductor region 5 for preventing the leak current in a state close to the design so as not to adversely affect the other components of the MOS 4. That is, the leak current can be suppressed without deteriorating other characteristics of the nMOS 4.

Further, since the side surfaces of the source electrode 4st and the drain electrode 4dt are inclined, it is easy to implant impurities. Further, since the semiconductor region 5 may be formed at the center of the source region 4s and the drain region 4d, its position can be easily set and its formation can be easily controlled.

Further, at the time of ion implantation at this time, the ion implantation angle may be set so that channeling occurs in the semiconductor substrate 1. By doing so, the semiconductor region 5 can be formed in a wide region at a deep position. This makes it possible to improve the leak current suppressing capability between the source region 4s and the drain region 4d of the nMOS 4.

To cause channeling in the semiconductor substrate 1, for example, the following may be performed. That is, for example, when the main surface of the semiconductor substrate 1 is the (100) plane, the implantation angle of the impurity ions with respect to the main surface of the semiconductor substrate 1 may be set to, for example, about 45 degrees.

After that, the semiconductor integrated circuit device is manufactured according to the usual process of MOS • FET.

That is, as shown in FIG. 1, after the interlayer insulating film 6a made of, for example, BPSG is deposited on the semiconductor substrate 1 by the CVD method or the like, its upper surface is flattened by the reflow method or the etch back method. To do.

Subsequently, a connection hole 8a is formed at a predetermined position of the interlayer insulating film 6a by the photolithography technique and the dry etching technique so that the source region 4s and the drain region 4d are partially exposed.

Then, on the semiconductor substrate 1, for example, Al--
After depositing a conductor film made of a Si—Cu alloy by a sputtering method or the like, the conductor film is patterned by a photolithography technique and a dry etching technique to form the first layer wiring 7a.

Then, for example, Si is formed on the interlayer insulating film 6a.
An interlayer insulating film 6b made of O ₂ is deposited by a CVD method or the like to cover the first layer wiring 7a, and then a connection hole is formed at a predetermined position on the interlayer insulating film 6b.

Then, on the semiconductor substrate 1, for example, Al--
After depositing a conductor film made of a Si—Cu alloy by a sputtering method or the like, the conductor film is patterned by a photolithography technique and a dry etching technique to form the second layer wiring 7b.

Then, for example, Si is formed on the interlayer insulating film 6b.
The second layer wiring 7b is covered by depositing the surface protection film 9 made of O ₂ by the CVD method or the like.

Next, a one-chip microcomputer (hereinafter, simply referred to as one-chip microcomputer) which is an application example of the semiconductor integrated circuit device having the nMOS 4 as described above.
Is shown in FIG.

The one-chip microcomputer 10 has a memory (M) and an interrupt controller INTC (In) centered on a CPU (Cemtral Processor Unit) in one semiconductor chip.
terrupt controller), an input / output port I / O, a timer T, and various peripheral circuits such as an analog / digital converter A / D.

The CPU is a main circuit for performing arithmetic processing.
The memory M is a circuit for storing a program, and has a relatively large capacity DRAM or flash memory (EEPRO).
M; Electrically Erasable Programmabl Read Only Me
mory) etc. are used.

The interrupt controller INTC is a circuit for executing another program while the program is being executed.
The input / output port I / O is a circuit that connects to external peripheral devices, reads data, and transmits operation results and the like to the outside.

The timer T is a circuit for generating a timing signal for synchronizing the operations and measuring the passage of time. Analog-to-digital converter A / D
Is a circuit for converting between an analog signal and a digital signal.

As described above, according to the first embodiment, the following effects can be obtained.

(1). Even if the gate length (Lg) is reduced by providing the semiconductor region 5a for suppressing the leak current at the central position between the source region 4s and the drain region 4d of the nMOS 4, the source region 4s and the drain region 4d are reduced. Since the leak current between the drain regions 4d can be suppressed, it is possible to suppress the variation of the threshold voltage of the nMOS 4 caused by the leak current. Therefore, it is possible to improve the operational stability of the fine nMOS 4.

(2) Since the semiconductor region 5a for suppressing leakage current is provided at a position separated from the source region 4s and the drain region 4d of the nMOS 4, the source region 4s and the drain region 4d and the leakage current suppressing semiconductor region are provided. Since the width of the depletion layer between 5a and 5a can be widened,
It is possible to suppress the leak current between the source region 4s and the drain region 4d without increasing the diffusion capacitance. That is, a fine nMOS capable of stable operation at high speed
4 can be realized.

(3) Since the semiconductor region 5a for suppressing the leak current is provided at the center position of the source region 4s and the drain region 4d of the nMOS 4, the controllability of the threshold voltage when applying the substrate bias voltage is good. It becomes possible to Therefore, it becomes possible to improve the operational reliability of the fine nMOS 4.

(4) Since the semiconductor region 5a for suppressing the leak current is provided at the center position of the source region 4s and the drain region 4d of the nMOS 4, the formation of the semiconductor region 5a for suppressing the leak current can be facilitated. It will be possible.

(5). When the semiconductor region 5a for suppressing the leak current is formed by ion implantation, the impurity ions for forming the semiconductor region 5a are supplied to the source electrode 4st and the drain whose side faces on the gate electrode 4g side are inclined. Electrode 4d
By using t as a mask, the semiconductor region 5a is formed obliquely to the main surface of the semiconductor substrate 1 and the semiconductor region 5a is formed in a self-aligned manner, whereby the formation position, size, etc. of the semiconductor region 5a can be made highly accurate. It will be possible. For this reason,
The leakage current suppressing semiconductor region 5a can be formed in a state close to the design so as not to adversely affect other components of the nMOS 4. That is, the leak current can be suppressed without deteriorating other characteristics of the nMOS 4. Therefore, it becomes possible to improve the operational reliability of the fine nMOS 4.

(6). In the ion implantation process from an oblique direction for forming the leakage current suppressing semiconductor region 5a, the implantation angle is set to an angle at which channeling occurs, so that the leakage current suppressing semiconductor region is formed. 5a
Can be formed in a wide area in a deep position of the semiconductor substrate 1. As a result, it becomes possible to improve the capability of suppressing the leak current between the source region 4s and the drain region 4d of the fine nMOS 4.

(Embodiment 2) FIG. 9 is a cross-sectional view of essential parts of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the second embodiment, as shown in FIG. 9, the leakage current suppressing semiconductor region 5a is provided at a position displaced from the central position of the source region 4s and the drain region 4d to the drain region 4d side. ing.

This is an arrangement considering the substrate bias effect. The substrate bias effect is a phenomenon in which the threshold voltage rises and the short channel effect is improved in the nMOS when the substrate bias voltage is lowered.

Here, depending on how the semiconductor region 5 is arranged, the potential under the channel region 4c increases, which is equivalent to raising the substrate bias voltage, which lowers the threshold voltage and deteriorates the short channel effect. However, in the case of the second embodiment, since the potential under the channel region 4c is not increased, it is possible to suppress the decrease in the threshold voltage due to the increase in the potential, and the short channel effect is obtained. Can be suppressed.

As described above, according to the second embodiment, in addition to (1), (2), (5), and (6) obtained in the first embodiment, the following effects can be obtained. Is possible.

That is, since the potential under the channel region 4c does not increase due to the provision of the semiconductor region 5 for suppressing the leak current, it is possible to suppress the decrease in the threshold voltage due to the increase in the potential. Therefore, the short channel effect can be suppressed. Therefore, it becomes possible to improve the operational reliability of the fine nMOS 4.

(Third Embodiment) FIG. 10 is a cross-sectional view of essential parts of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the third embodiment, the present invention is CM.
A case of application to an OS (Complementary MOS.FET) circuit will be described with reference to FIG. Note that nMOS4
Regarding the above, the description is omitted because it is the same as in the first embodiment.

In the upper layer of the semiconductor substrate 1, a p-channel type MOS • FET (hereinafter, simply referred to as pMOS) formation region surrounded by the field insulating film 3 is provided with an n well 2n.
Are formed.

The impurity concentration of the n well 2 is, for example, 1
It is about × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . Further, the dose amount, the ion implantation energy and the heat treatment condition when forming the n-well 2 are the p-well 2p of the first embodiment.
Is the same as

A pMOS 11 is formed on the n well 2n. The pMOS 11 includes a source region 11s and a drain region 11d formed on the semiconductor substrate 1, and a channel region 11c formed between them.
And the gate insulating film 11i formed on the semiconductor substrate 1.
And a gate electrode 11g formed thereon.

Source region 11s and drain region 11
d is the low-concentration region 1 formed on the channel region 11c side
1s1, 11d1 and high concentration region 1 provided outside
It has 1s2 and 11d2.

In both the low concentration regions 11s1 and 11d1 and the high concentration regions 11s2 and 11d2, for example, p-type impurity boron is introduced. Low concentration area 11s1,11
The impurity concentration of d1 is, for example, 1 × 10 ¹⁸ to 1 × 10 ¹⁹ /
cm ³ .

The impurity concentration of the high-concentration regions 11s2 and 11d2 is, for example, about 1 × 10 ²¹ / cm ³ , and the depth (center of Gaussian distribution) is, for example, about 0.15 μm. The dose amount and the implantation energy at the time of forming the low concentration regions 11s1, 11d2 and the high concentration regions 11s2, 11d2 are the same as the low concentration regions 4s1, 4d2 and the high concentration regions 4s2, 4d2 of the nMOS 4 of the first embodiment.
Is the same as

Source region 11s and drain region 11
d is electrically connected to the source electrode 11st and the drain electrode 11dt, respectively. This source electrode 1
The 1st and drain electrodes 11dt are made of, for example, low-resistance polysilicon, and a side surface on the gate electrode side thereof has an inclination.

The channel region 11c is the source region 11s.
And a drain region 11d, which is a conductive path of carriers flowing between the source region 11s and the drain region 11d, and is formed by applying a predetermined voltage to the gate electrode 11g. The gate length is, for example, 0.2μ
It is about m to 0.4 μm.

The gate insulating film 11i is made of, for example, SiO ₂ . The gate electrode 11g is made of low resistance polysilicon, for example. However, the structure of the gate electrode 11g is not limited to the single-layer structure of low-resistance polysilicon and can be variously modified. For example, a single-layer gate structure of only tungsten may be used, or for example, a low-resistance polysilicon film may be formed. A polycide structure formed by depositing a tungsten silicide film may be used.

Side walls 11sw for forming an LDD structure are formed on the side surfaces of the gate electrode 11g. The sidewall 11sw is made of, for example, SiO ₂ .

By the way, in the third embodiment, the source region 11s and the drain region 1 are located below the channel region 11c in the pMOS 11 at positions separated from the source region 11s and the drain region 11d.
A semiconductor region 5b for suppressing a leak current is formed for suppressing a leak current from flowing between 1d.

The source region 11 is formed in the semiconductor region 5b.
n of the conductivity type opposite to that of s and the drain region 11d.
Contains phosphorus or As, which are + type impurities,
The impurity concentration is, for example, 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / c.
It is about m ³ . The depth of the semiconductor region 5b (the center of the Gaussian distribution) is almost equal to the depth of the source region 11s and the drain region 11d (the center of the Gaussian distribution), and is about 0.15 μm, for example.

By providing the semiconductor region 5b as described above, even if the gate length (Lg) is reduced, the source region 1
Since the leak current between the 1s and the drain region 11d can be suppressed, the pMO caused by the leak current is reduced.
It is possible to suppress the variation of the threshold voltage of S11.

Further, the semiconductor region 5b for preventing the leak current is provided.
Is provided at a position apart from the source region 11s and the drain region 11d, the source region 11s and the drain region 11d and the leakage current preventing semiconductor region 5 are provided.
Since the width of the depletion layer between b and b can be widened, it is possible to suppress the leak current between the source region 11s and the drain region 11d without increasing the diffusion capacitance.

As described above, in the third embodiment,
It is possible to realize high-speed stable operation of the CMOS circuit configured by the fine nMOS 4 and pMOS 11.

(Embodiment 4) FIGS. 11 to 14 are cross-sectional views of essential parts in a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the fourth embodiment, another example of the method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIGS.

[0110] First, as shown in FIG. 11, p ^- p-well 2p by boron p-type impurity into the nMOS formation region in the form of the semiconductor substrate 1 is introduced by ion implantation or the like
To form The impurity dose amount and implantation energy at this time are the same as those in the first embodiment.

Then, in the element isolation region of the semiconductor substrate 1,
For example, the field insulating film 3 made of SiO _{2 is} formed by LOCO
After being selectively formed by the S method or the like, the gate insulating film 4i is formed on the semiconductor substrate 1 in the element formation region surrounded by the field insulating film 3 by the thermal oxidation method or the like.

After that, a conductor film made of, for example, low-resistance polysilicon is formed on the semiconductor substrate 1 by the CVD method or the like, and then the conductor film is patterned by the photolithography technique or the dry etching method. A gate electrode 4g is formed on 4i.

Then, using the gate electrode 4g as a mask, in order to form the low-concentration regions 4s1 and 4d1 of the source region and the drain region in the nMOS formation region, for example, n-type impurity phosphorus or As is ion-implanted. Introduce.

Then, on the semiconductor substrate 1, for example, SiO 2 is formed.
After depositing an insulating film made of ₂ by the CVD method or the like, the insulating film is etched back by the dry etching method or the like, and as shown in FIG.
A side wall 4sw is formed on the side wall of the.

After removing the insulating film on the source region and the drain region, the source electrode 4st and the drain electrode 4d made of low-resistance polysilicon having a film thickness of, for example, about 100 nm are formed on the source region and the drain region.
t is formed by an epitaxial growth method or the like. The source electrode 4st and the drain electrode 4dt contain, for example, n-type impurity phosphorus or As.

At this time, the side surfaces of the source electrode 4st and the drain electrode 4dt are inclined. The conditions during the epitaxial growth are as follows, for example. That is, the processing temperature is, for example, 75
0 degrees to 850 degrees, the processing time is, for example, about 1 minute to 5 minutes,
The processing gas is, for example, SiH ₂ Cl ₂ gas.

Then, heat treatment is applied to the semiconductor substrate 1 to diffuse the impurities in the source electrode 4st and the drain electrode 4dt into the semiconductor substrate 1, so that the source region 4s and the drain region of the nMOS 4 are formed as shown in FIG. 4d high-concentration regions 4s2 and 4d2 are formed.

Then, as shown in FIG. 14, in order to form the semiconductor region 5a for suppressing the leak current in the semiconductor substrate 1, the gate electrode 4g, the sidewall 4sw, the source electrode 4st and the drain electrode 4dt are used as a mask. Boron, which is a p-type impurity, is introduced into the semiconductor substrate 1 from an oblique direction by an ion implantation method or the like.

Thus, the semiconductor region 5a for suppressing the leak current is provided at the central position of the source region 4s and the drain region 4d of the semiconductor substrate 1 so as to be separated from the channel region 4c, the source region 4s and the drain region 4d. Are formed in a self-aligned manner. The dose amount of impurities at this time is, for example, about 1 × 10 ¹³ / cm ² , and the implantation energy is, for example, about 100 KeV.

Further, the ion implantation angle may be set so that channeling occurs in the semiconductor substrate 1 at the time of ion implantation at this time. By doing so, the semiconductor region 5a can be formed at a deep position in a wide region. This makes it possible to improve the leak current suppressing capability between the source region 4s and the drain region 4d of the nMOS 4.

To cause channeling in the semiconductor substrate 1, as in the first embodiment, for example, when the main surface of the semiconductor substrate 1 is the (100) plane, impurity ions are implanted into the main surface of the semiconductor substrate 1. The angle may be set to about 45 degrees, for example.

If a large amount of heat treatment is performed in the subsequent steps,
After forming the semiconductor region 5a for suppressing the leak current, the source electrode 4st and the drain region 4dt described above may be removed by an etching process. Thereby, it is possible to prevent impurities from being diffused from the source electrode 4st and the drain electrode 4dt to the semiconductor substrate 1 side by the subsequent heat treatment.

The subsequent steps are the same as those in the first embodiment.
Therefore, the description is omitted.

In the fourth embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.

That is, the high-concentration regions 4s2 and 4d2 of the source region 4s and the drain region 4d of the nMOS 4 are formed by impurity diffusion from the source electrode 4st and the drain electrode 4dt.
Since the connection depth of 2,4d2 can be made shallow, nM
It is possible to reduce the size of the OS4.

(Embodiment 5) FIGS. 15 to 18 are cross-sectional views of a main part during a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the fifth embodiment, another example of the method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIGS.

First, a p-type well 2p is formed by introducing a p-type impurity boron into the nMOS formation region of the p ^{− type} semiconductor substrate 1 by an ion implantation method or the like. At this time, the dose amount of impurities is, for example, about 5 × 10 ¹² / cm ² , and the implantation energy is, for example, about 200 KeV.

Then, in the element isolation region of the semiconductor substrate 1,
For example, the field insulating film 3 made of SiO _{2 is} formed by LOCO
After being selectively formed by the S method or the like, in order to form the semiconductor region 5a for suppressing the leak current, for example, p-type impurity boron is introduced into the semiconductor substrate 1 by the ion implantation method or the like. The dose amount of impurities at this time is, for example, 1
It is about × 10 ¹³ / cm ² , and the implantation energy is
For example, it is about 100 KeV. At this time, as in the first embodiment, the ion implantation may be performed under the condition that channeling occurs.

After that, as shown in FIG. 16, a gate insulating film 4i is formed on the semiconductor substrate 1 in the element forming region surrounded by the field insulating film 3 by a thermal oxidation method or the like.

Next, a conductor film made of, for example, low-resistance polysilicon is formed on the semiconductor substrate 1 by the CVD method or the like, and then the conductor film is patterned by the photolithography technique or the dry etching method or the like to form the gate insulating film 4i. A gate electrode 4g is formed on top.

Then, using the gate electrode 4g as a mask, phosphorus or As, which is an n-type impurity, is introduced into the nMOS formation region by an ion implantation method or the like. At this time, the dose amount of impurities is, for example, about 1 × 10 ¹³ / cm ² , and the implantation energy is, for example, about 100 KeV.

At this time, the isolation region 12 is formed by introducing an n-type impurity so as to cancel the conductivity type of the semiconductor region 5a on both sides of the gate electrode 4g. As a result, the semiconductor region 5a for suppressing the leak current is left below the channel region 4c.

Then, in order to form the low-concentration regions, for example, phosphorus or As, which is an n-type impurity, is introduced by an ion implantation method or the like, and as shown in FIG.
Form 1

After that, for example, SiO 2 is formed on the semiconductor substrate 1.
After depositing an insulating film consisting of ₂ by the CVD method or the like, the insulating film is etched back by the dry etching method or the like, and as shown in FIG.
A side wall 4sw is formed on the side wall of the.

Then, using the gate electrode 4g and the sidewalls 4sw as a mask, an nMOS forming region is formed.
In order to form the source region 4s2 and the drain region 4d2, for example, n-type impurity phosphorus or As is introduced by an ion implantation method or the like. At this time, the dose amount of impurities is, for example, about 1 × 10 ¹⁵ / cm ² , and the implantation energy is, for example, about 60 KeV.

Then, as shown in FIG. 18, an interlayer insulating film 6a made of, for example, BPSG is formed on the semiconductor substrate 1 by C.
After being deposited by the VD method or the like, the upper surface of the interlayer insulating film 6a is flattened by the reflow method or the etch back method.

Subsequently, a connection hole 8a is formed at a predetermined position of the interlayer insulating film 6a by the photolithography technique and the dry etching technique so that the source region 4s and the drain region 4d are partially exposed.

Then, on the semiconductor substrate 1, for example, Al--
After depositing a conductor film made of a Si—Cu alloy by a sputtering method or the like, the conductor film is patterned by a photolithography technique and a dry etching technique to form the first layer wiring 7a.

After that, as in the first embodiment, the MO
A semiconductor integrated circuit device is manufactured in accordance with a normal S-FET process.

As described above, according to the fifth embodiment, in addition to the effects (1) to (4) obtained in the first embodiment, the semiconductor region 5a for suppressing the leak current can be relatively easily formed. The effect that it can be formed is obtained.

(Sixth Embodiment) FIGS. 19 to 22 are cross-sectional views of essential parts in a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the sixth embodiment, another example of the method of manufacturing the semiconductor integrated circuit device described above will be described with reference to FIGS.

[0144] First, as shown in FIG. 19, p ^- boron p-type impurity into the nMOS formation region in the form of the semiconductor substrate 1 by introducing by ion implantation or the like, p-well 2
Form p. At this time, the dose amount, the implantation energy and the heat treatment conditions when forming the p well 2p are the same as those in the first embodiment.

Then, in the element isolation region of the semiconductor substrate 1,
For example, the field insulating film 3 made of SiO _{2 is} formed by LOCO
After being selectively formed by the S method or the like, the gate insulating film 4i is formed on the semiconductor substrate 1 surrounded by the field insulating film 3 by the thermal oxidation method or the like.

Then, on the semiconductor substrate 1, a photoresist pattern 13a exposing the channel region 4c is formed.
Is formed by a photolithography technique, and then the photoresist pattern 13a is used as a mask to form a semiconductor region 5a for suppressing a leakage current, for example, p
Boron, which is a shape impurity, is introduced by an ion implantation method or the like.

Then, as shown in FIG. 20, the conductor film 1 made of, for example, low resistance polysilicon is formed on the semiconductor substrate 1 with the photoresist pattern 13a left as it is.
4 is deposited by the CVD method or the like.

Then, the photoresist pattern 13 is formed.
a is removed. By doing so, the conductor film 14 on the photoresist pattern 13a becomes the photoresist pattern 1
3a and the conductor film 1 on the gate insulating film 4i removed together
Only 4 will remain. In this way, as shown in FIG. 21, the gate electrode 4g made of a conductor film is formed.

Then, as shown in FIG. 22, using the gate electrode 4g as a mask, the low concentration regions 4s1 and 4s of the source region 4s and the drain region 4d are formed in the nMOS formation region.
To form d1, for example, n-type impurity phosphorus or As is introduced by an ion implantation method or the like.

Then, for example, SiO 2 is formed on the semiconductor substrate 1.
After depositing an insulating film made of ₂ by the CVD method or the like, the insulating film is etched back by the dry etching method or the like to form the sidewall 4sw on the side wall of the gate electrode 4g.

Then, using the gate electrode 4g and the sidewalls 4sw as a mask, for example, phosphorus or As of an n-type impurity is introduced by an ion implantation method or the like, whereby high concentration regions of the source region 4s and the drain region 4d of the nMOS 4 are introduced. 4s2 and 4d2 are formed.

Then, for example, BPS is formed on the semiconductor substrate 1.
After the interlayer insulating film 6a made of G or the like is deposited by the CVD method or the like, the upper surface of the interlayer insulating film 6a is flattened by the reflow method or the etch back method.

Then, a connection hole 8a is formed at a predetermined position of the interlayer insulating film 6a by the photolithography technique and the dry etching technique so that a part of the source region 4s and the drain region 4d is exposed.

Then, on the semiconductor substrate 1, for example, Al--
After depositing a conductor film made of a Si—Cu alloy by a sputtering method or the like, the conductor film is patterned by a photolithography technique and a dry etching technique to form the first layer wiring 7a.

After that, as in the first embodiment, the MO
A semiconductor integrated circuit device is manufactured in accordance with a normal S-FET process.

As described above, according to the sixth embodiment, the following effects can be obtained.

(1). The photolithography process for patterning the gate electrode is unnecessary by forming the gate electrode 4g by lift-off using the photoresist pattern 13a for forming the semiconductor region 5a for suppressing the leak current. Therefore, the manufacturing process of the semiconductor integrated circuit device can be reduced and the manufacturing time thereof can be shortened.

(2). Semiconductor region 5a for suppressing leakage current
By forming the gate electrode 4g by lift-off using the photoresist pattern 13a for forming
Since the formation alignment accuracy of the gate electrode 4g can be improved, the characteristics of the nMOS 4 can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the first to sixth embodiments and does not depart from the scope of the invention. It goes without saying that various changes can be made.

For example, the semiconductor region for suppressing the leak current is
It is not limited to the center or the drain side of the source region and the drain region, but may be provided at a position displaced to the source region 4s side as shown in FIG.

Further, in the first embodiment and the like, channeling occurs in the semiconductor substrate for forming the semiconductor region for suppressing the leak current at a deep position, but the present invention is not limited to this, and for example, leakage may occur. When forming the semiconductor region for current suppression, the semiconductor region 5 may be formed at a deep position by performing a process of implanting impurity ions with low energy and a process of implanting with high energy.

The impurity introducing process for forming the semiconductor region for suppressing the leak current is not limited to the ion implantation method. For example, the impurity for forming the semiconductor region for suppressing the leak current is changed to the focus ion beam. May be used to introduce into the semiconductor substrate. In this case, since a photolithography process for forming a mask at the time of ion implantation is not necessary, the manufacturing process of the semiconductor integrated circuit device can be reduced,
It is possible to reduce the manufacturing time of the semiconductor integrated circuit device.

In the first to sixth embodiments, the case where only the p-type impurity or the n-type impurity is introduced when forming the semiconductor region for suppressing the leak current has been described, but the present invention is not limited to this. However, germanium (Ge) may be introduced together with the p-type impurity or the n-type impurity for forming the semiconductor region for suppressing the leak current.

This is because Ge has the property of preventing the diffusion of impurities without affecting the device characteristics.
By introducing Ge together, it is possible to prevent impurities in the leakage current suppressing semiconductor region from diffusing to other than a specific place. Therefore, the device characteristics are not deteriorated by providing the semiconductor region for suppressing the leak current.

Although the case where the leakage current suppressing region is formed of the semiconductor region has been described, the present invention is not limited to this. For example, the leakage current suppressing region is formed of an insulating region such as SiO ₂ or silicon nitride. May be. In order to form this SiO ₂ region, oxygen ions may be implanted into the semiconductor substrate and heat treatment may be performed. Further, in order to form the silicon nitride region, nitrogen ions may be implanted into the semiconductor substrate and heat treatment may be performed.

Further, in the first to fourth embodiments,
Although the case where the source electrode and the drain electrode are formed of only low resistance polysilicon has been described, the present invention is not limited to this. For example, a silicide layer is provided on the upper layer portion of the low resistance polysilicon forming the source electrode and the drain electrode. May be. As a result, the resistance of the source region and the drain region can be reduced, and the operating speed of the semiconductor integrated circuit device can be improved.

In the fifth and sixth embodiments, the MOS is
The case where the source region and the drain region of the FET are formed of only the semiconductor region has been described, but the present invention is not limited to this. For example, a silicide layer may be provided above the source region and the drain region. As a result, the resistance of the source region and the drain region can be reduced, and the operating speed of the semiconductor integrated circuit device can be improved.

In the fourth embodiment, the case where the impurities are thermally diffused from the source electrode and the drain electrode formed by epitaxial growth has been described.
For example, a source electrode and a drain electrode made of low resistance polysilicon formed by a CVD method may be provided, and impurities may be thermally diffused into the semiconductor substrate from the source electrode and the drain electrode.

In the above description, the case where the invention made by the present inventor is mainly applied to the one-chip microcomputer which is the field of application which is the background of the invention has been described, but the invention is not limited thereto and various applications are possible. For example, microprocessor, DRAM, SRAM (Staic RAM)
Alternatively, it can be applied to a flash memory (EEPROM) or the like. The present invention can be applied to at least a semiconductor integrated circuit device having a MOS.FET structure.

[0170]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the semiconductor integrated circuit device of the present invention, since the semiconductor region for suppressing the leak current is provided at a position separated from the source region and the drain region of the MIS transistor, the source region and the drain region are provided. Since the width of the depletion layer between the semiconductor layer and the leakage current suppressing semiconductor region can be widened, the leakage current between the source region and the drain region can be suppressed without increasing the diffusion capacitance. That is, it becomes possible to realize a semiconductor integrated circuit device having a MIS transistor which is fine and capable of stable operation at high speed.

(2) According to the semiconductor integrated circuit device of the present invention, the semiconductor region for suppressing the leak current is provided at the central position of the source region and the drain region of the MIS transistor, so that the diffusion capacitance is not increased. It is possible to suppress the leak current between the source region and the drain region and to improve the controllability of the threshold voltage when the substrate bias voltage is applied. Therefore, it is possible to improve the operational reliability of the fine MIS transistor.

(3) According to the semiconductor integrated circuit device of the present invention, the leakage current suppressing semiconductor region is provided at the center position of the source region and the drain region of the MIS transistor. Can be easily formed.

(4) According to the semiconductor integrated circuit device of the present invention, the leakage current suppressing semiconductor region is provided at the position displaced to the drain region side of the MIS transistor, so that the source capacitance can be increased without increasing the diffusion capacitance. A leak current between the region and the drain region can be suppressed, and the substrate bias effect is not impaired. Therefore, it is possible to improve the operational reliability of the fine MIS transistor.

(5) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, when the semiconductor region for leak current suppression is formed by ion implantation, the impurity ions for forming the semiconductor region are Using the source electrode and the drain electrode having a slope on the side surface on the electrode side as a mask, implantation is performed obliquely to the main surface of the semiconductor substrate,
By forming the semiconductor region in a self-aligned manner, it becomes possible to make the formation position, size, etc. of the semiconductor region highly accurate. Therefore, it is possible to form the semiconductor region for suppressing the leak current in a state close to the design so as not to adversely affect the other components of the MIS transistor, and the desired effect of the semiconductor region can be exhibited well. Is possible. Therefore, it is possible to improve the operational reliability of the fine MIS transistor.

(6) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, in the step of implanting ions from an oblique direction for forming the semiconductor region, the implanting angle is set to an angle at which channeling occurs. Thus, it becomes possible to form a semiconductor region for suppressing the leak current in a wide area at a deep position of the semiconductor substrate. As a result, fine M
It is possible to improve the ability of suppressing the leak current between the source region and the drain region of the OS • FET.

(7) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, the source region and the drain region of the MIS transistor are formed by impurity diffusion from the source electrode and the drain electrode, and thus the source region and the drain are formed. Since the connection depth of the region can be reduced, the size of the MIS transistor can be reduced.

(8). According to the method of manufacturing a semiconductor integrated circuit device of the present invention, after a semiconductor layer for suppressing a leak current is formed at a predetermined depth position of a semiconductor substrate, the semiconductor layer is formed using the gate electrode as a mask. Is an impurity of opposite conductivity type, so that the semiconductor layers at both sides of the gate electrode are canceled and a semiconductor region for suppressing leakage current is formed below the channel, so that a semiconductor region for suppressing leakage current can be relatively easily formed. Can be formed.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention;

FIG. 2A is a graph showing a relationship between a gate length and a threshold voltage when a semiconductor region for suppressing leakage current is provided, and FIG. 2B is a case where a semiconductor region for suppressing leakage current is not provided. 4 is a graph showing the relationship between the gate length and the threshold voltage in FIG.

FIG. 3 is a graph showing an impurity concentration distribution in the depth direction of a semiconductor substrate.

4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;

5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 4;

6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 5;

7 is a main-portion cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during the manufacturing process following that of FIG. 6;

8 is an explanatory diagram of an application example of the semiconductor integrated circuit device of FIG.

FIG. 9 is a cross-sectional view of essential parts of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 11 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of another embodiment of the present invention during the manufacturing step following that of FIG. 11;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to another embodiment of the present invention during the manufacturing step following FIG. 12;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of another embodiment of the present invention during the manufacturing step following that of FIG. 13;

FIG. 15 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 16 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of another embodiment of the present invention during the manufacturing step following that of FIG. 15;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step following that of FIG. 16;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of another embodiment of the present invention during the manufacturing step following that of FIG. 17;

FIG. 19 is a fragmentary cross-sectional view during a manufacturing step of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 20 is a cross-sectional view of essential parts in the manufacturing process following FIG. 19 of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 21 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to another embodiment of the present invention during the manufacturing step following FIG. 20;

22 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step following FIG. 21;

FIG. 23 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2p p well 2n n well 3 field insulating film 4 n channel type MOS • FET 4c channel region 4s source region 4s1 low concentration region 4s2 high concentration region 4st source electrode 4d drain region 4d1 low concentration region 4d2 high concentration region 4dt Drain electrode 4i Gate insulating film 4g Gate electrode 4sw Side wall 5a, 5b Semiconductor region 6a, 6b Interlayer insulating film 7a First layer wiring 7b Second layer wiring 8a Connection hole 9 Surface protective film 10 One-chip microcomputer 11 p-channel type MOS-FET 11c Channel region 11s Source region 11s1 Low concentration region 11s2 High concentration region 11st Source electrode 11d Drain region 11d1 Low concentration region 11d2 High concentration region 11dt Drain electrode 11i Gate insulating film 11g Gate electrode 11sw sidewall 12 isolation regions 13a photoresist pattern

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsumi Tsuneno 2326 Imai, Ome City, Tokyo, Hitachi, Ltd. Device Development Center (72) Inventor Takahide Nakamura 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development (72) Inventor Hisako Sato 2326 Imai, Ome City, Tokyo, Hitachi Device Development Center (72) Inventor Hiroo Masuda 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center

Claims (10)

[Claims] 1. A semiconductor integrated circuit device having a MIS transistor on a semiconductor substrate, wherein the source region and the drain region of the MIS transistor are separated from the source region, the drain region, and the channel region above the semiconductor substrate. A semiconductor region in which an impurity having a conductivity type opposite to that of the impurity introduced in the source region and the drain region is introduced in order to suppress a leak current from flowing between the source region and the drain region. A semiconductor integrated circuit device provided. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor region is provided at a central position between the source region and the drain region. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor region is provided at a position displaced toward a drain region side from a central position between the source region and the drain region. apparatus. 4. The semiconductor integrated circuit device according to claim 1, wherein the MIS transistor is an n-channel type MIS transistor, and the semiconductor region is p.
A semiconductor integrated circuit device characterized by being a semiconductor region of the shape. 5. A semiconductor integrated circuit device having a MIS transistor on a semiconductor substrate, the source region and the drain region of the MIS transistor being separated from the source region, the drain region and the channel region above the semiconductor substrate. In the semiconductor integrated circuit device, an insulating region is provided at a position to prevent a leak current from flowing between the source region and the drain region. 6. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a one-chip microcomputer having a logic circuit section configured by the MIS transistor. Semiconductor integrated circuit device. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step (a) forms a gate electrode of the MIS transistor on the semiconductor substrate. b) a step of forming the source region and the drain region by introducing an impurity of a predetermined conductivity type into the semiconductor substrate, and (c) exposing the formation region of the source region and the formation region of the drain region, Forming a source electrode and a drain electrode made of a conductive film having an inclined surface on the side of the gate electrode on these formation regions; and (d) between the source region and the drain region of the MIS transistor. Conduction of impurities in the source region and the drain region using the gate electrode, the source electrode, and the drain electrode as a mask to form a semiconductor region. And a step of ion-implanting an impurity of a conductivity type opposite to that of the semiconductor substrate to the main surface of the semiconductor substrate from an oblique direction. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein in the step of implanting ions from an oblique direction for forming the semiconductor region, the implanting angle is set to an angle at which channeling occurs. And method for manufacturing a semiconductor integrated circuit device. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the source region and the drain region are formed by impurity diffusion from the source electrode and the drain electrode. Device manufacturing method. 10. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein (a) the M
Before forming the gate electrode of the IS transistor, an impurity having a conductivity type opposite to that of the impurities in the source region and the drain region is ion-implanted perpendicularly to the main surface of the semiconductor substrate, Forming a semiconductor layer for forming the semiconductor region at a predetermined depth position of the semiconductor substrate by performing heat treatment by
(B) a step of forming a gate electrode of the MIS transistor on the semiconductor substrate, and (c) an impurity having a conductivity type opposite to that of the impurities of the semiconductor layer, with the gate electrode as a mask, and the conductivity type of the semiconductor layer. Forming a semiconductor region in the semiconductor substrate below the gate electrode by ion-implanting the semiconductor substrate so as to cancel the above; and (d) by introducing an impurity of a predetermined conductivity type into the semiconductor substrate, A step of forming a source region and a drain region, a method for manufacturing a semiconductor integrated circuit device.