JPH09246537A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the punch through between a source region and a drain region without incurring the increase of capacity, in a semiconductor integrated circuit device which has a fine MIS transistor. SOLUTION: Heavily doped regions 4ns2, 4ps2, 4nd2, and 4pd2 are made to separate from semiconductor regions 5p and 5n for punch through control by thinning the heavily doped regions 4ns2, 4ps2, 4nd2, and 4pd2 in the source regions 4ns and 4pd and the drain regions 4nd and 4pd of an n-channel type of MOS.FET4n and a p-channel type of MOS.FET4p.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and more particularly to a MIS (Metal In
sulator Semiconductor) The present invention relates to a technology effectively applied to a technology for suppressing a leak current between a source and a drain of a transistor.

[0002]

2. Description of the Related Art Since miniaturization of MIS transistors is effective for improving the degree of integration and driving capability of MIS transistors, miniaturization has been rapidly advanced in recent years.

However, while the MIS transistor is miniaturized, the power supply voltage is constant and the electric field strength inside the element is increased. As a result, various problems such as a short channel effect which adversely affect the element characteristics occur. are doing.

The short channel effect is such that as the channel length is shortened, the influence of the drain voltage also extends directly below the gate electrode, so that the potential on the surface of the semiconductor substrate is lowered, and the fluctuation (decrease) of the threshold voltage and the execution channel. This is a phenomenon that has various adverse effects such as a decrease in length.

When the short channel effect becomes more significant, the drain current cannot be controlled by the gate voltage, so-called punch-through occurs, and the leak current between the source and the drain increases. This punch-through is performed, for example, by using a DRAM (Dynamic Random Access).
In the transfer gate of the memory, the storage retention is deteriorated.

A technique for avoiding such a problem is as follows.
For example, a technique is disclosed in which a semiconductor region having a high impurity concentration of the same conductivity type as an impurity of a channel is provided so as to overlap with the source region and the drain region at the channel-side ends of the source region and the drain region of the MIS transistor. Such a technique for suppressing punch-through is described in, for example, Japanese Patent Application Laid-Open No. 5-136404.

[0007]

However, in the above technique in which the semiconductor region for suppressing the leak current is provided so as to overlap the channel side end of the source region and the drain region of the MIS transistor, the leak current between the source and the drain is suppressed. The present inventor has found that it is effective but has the following problems.

That is, in the case of the above technique, since the source / drain region and the semiconductor region for suppressing the leakage current overlap, the depletion layer formed between the source / drain region and the semiconductor region for suppressing the leakage current is formed. As a result of the narrower width,
There is a problem that the diffusion capacitance increases and the improvement of the device operation speed is hindered.

It is an object of the present invention to provide a technique capable of suppressing punch-through between a source region and a drain region in a semiconductor integrated circuit device having a fine MIS transistor without causing an increase in capacitance. is there.

Another object of the present invention is to provide a technique capable of realizing a fine semiconductor integrated circuit device having a MIS transistor capable of stable operation at high speed.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a MIS transistor on a semiconductor substrate, wherein the source region and the drain region are formed below the source region, the drain region and the channel region of the MIS transistor. A semiconductor region for punch-through suppression is provided at a position apart from.

Also, in the semiconductor integrated circuit device of the present invention, the source region and the drain region are constituted by a semiconductor region formed on the semiconductor substrate and a conductor film provided on the semiconductor region. Is.

In the semiconductor integrated circuit device of the present invention, a compound layer with a predetermined conductor material is formed on the upper layer portion of the conductor film forming the source region and the drain region.

Further, a method of manufacturing a semiconductor integrated circuit device according to the present invention is a method of manufacturing a semiconductor integrated circuit device having a MIS transistor on a semiconductor substrate, wherein (a) punch-through is suppressed on the entire surface of the semiconductor substrate. Introducing an impurity for forming a semiconductor region, (b) forming a gate insulating film and a gate electrode of the MIS transistor on the semiconductor substrate, and (c) forming an insulating film around the gate electrode. A step of covering, (d) a step of exposing a semiconductor substrate around the gate electrode and then forming a semiconductor film on the exposed surface of the semiconductor substrate, and (e) a semiconductor after forming the semiconductor film A step of introducing impurities into the substrate obliquely with respect to the main surface thereof; and (f) punching through the impurities in the semiconductor film after introducing the impurities into the semiconductor film. By diffusing into the semiconductor substrate side so as not to overlap the semiconductor region for braking, and has a step of forming a semiconductor region constituting the source and drain regions of the MIS transistor.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings (note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments. , The repeated explanation is omitted).

(Embodiment 1) FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device according to a first embodiment, and FIGS. 2 to 7 are sectional views of a main part of a semiconductor integrated circuit device shown in FIG. It is a figure.

[0019] The semiconductor substrate 1 is, for example, p ^- made form of silicon (Si) single crystal, the impurity concentration, for example 1
It is about 10 ¹⁵ / cm ³ . A p well 2p and an n well 2n are formed on the semiconductor substrate 1.

The p-well 2p contains, for example, p-type impurity boron. The n well 2n contains, for example, phosphorus or arsenic (As) which is an n-type impurity. p
The impurity concentration of the well 2p and the n well 2n is, for example, about 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ .

A field insulating film 3 for element isolation is selectively formed on the semiconductor substrate 1. The field insulating film 3 is made of, for example, silicon dioxide (SiO ₂ ).
On the p-well 2p and the n-well 2n surrounded by, for example, an n-channel type MOS.F.
ET (Metal Oxide Semiconductor Field Effect Tran
sistor; hereinafter referred to as nMOS) 4n and p-channel type MOS-FET (hereinafter referred to simply as pMOS) 4p
Are formed. Then, the nMOS 4n and p
CMOS (Complimentary MOS F)
ET) circuit is formed.

This nMOS 4n includes a pair of source regions 4
ns and drain region 4nd and channel region 4nc
And a gate insulating film 4ni and a gate electrode 4ng.

Source region 4ns and drain region 4n
d is a low concentration region 4n formed on the semiconductor substrate 1
It has s1,4nd1 and high concentration regions 4ns2,4nd2 and conductor films (conductor films) 4ns3,4nd3 formed on the high concentration regions 4ns2,4nd2.

The low-concentration regions 4ns1 and 4nd1 are formed on the side of the channel region 4nc, and are formed in such a state that one end of the low-concentration regions 4ns1 and 4nd1 extends slightly over the end of the gate electrode 4ng.

The low concentration regions 4ns1 and 4nd1 contain, for example, n-type impurities such as phosphorus or arsenic (As), and the impurity concentration is, for example, 3 × 10 ¹⁸ to 1 × 10.
It is about ²⁰ / cm ³ . This low concentration area 4ns1, 4nd
The depth of 1 (center of Gaussian distribution) is, for example, about 0.15 μm.

The high concentration regions 4ns2 and 4nd2 are formed outside the low concentration regions 4ns1 and 4nd1. The high-concentration regions 4ns2 and 4nd2 contain, for example, n-type impurity phosphorus or As, and the impurity concentration thereof is, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ .

The depth (center of Gaussian distribution) of the high-concentration regions 4ns2 and 4nd2 is very thin, for example, 0.1 μm or less. This is the high concentration region 4ns2,4n
Since the conductor films 4ns3 and 4nd3 stacked on the upper layer of d2 also function as the source region 4ns and the drain region 4nd, the semiconductor regions for the source / drain regions that must be formed above the semiconductor substrate 1 are correspondingly formed. Because it can be thin. This conductor film 4ns3, 4nd3
Is made of, for example, n-type Si single crystal, and the side surface on the gate electrode 4ng side is inclined.

The channel region 4nc is the source region 4ns.
And low concentration regions 4ns1 and 4nd of the drain region 4nd
It is provided between 1 and 2. The channel region 4nc is a conductive path of carriers flowing between the source region 4ns and the drain region 4nd, and is formed by applying a predetermined voltage to the gate electrode 4ng. The gate length (Lg)
Is, for example, about 0.2 μm to 0.4 μm.

The gate insulating film 4ni is made of, for example, SiO ₂ . The gate electrode 4g is made of low resistance polysilicon, for example. However, the structure of the gate electrode 4g is not limited to the single-layer structure of low-resistance polysilicon and can be variously modified. For example, a single-layer gate structure of only tungsten may be used, or for example, a low-resistance polysilicon film may be formed. A polycide structure formed by depositing a tungsten silicide film may be used.

A side wall 4sw and a cap insulating film 4c made of, for example, SiO ₂ are formed on the side surface and the upper surface of the gate electrode 4g, respectively.

By the way, in the first embodiment, below the channel region 4nc in the nMOS 4n,
A semiconductor region 5p for suppressing a leak current from flowing between the source region 4ns and the drain region 4nd is formed in the p-well 2p in a state of extending in the lateral direction of FIG.

By providing such a semiconductor region 5p, even if the gate length (Lg) becomes short, the source region 4
Since the leak current between the drain region 4d and the drain region 4d can be suppressed, the nMOS 4 caused by the leak current can be suppressed.
It is possible to suppress the fluctuation of the threshold voltage of n.

In the semiconductor region 5p, the source region 4n
p of the conductivity type opposite to that of s and the drain region 4nd
It contains + type boron, and the impurity concentration thereof is, for example, about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ .

The depth of the semiconductor region 5p (the center of the Gaussian distribution) is the source region 4ns and the drain region 4n.
The depth (the center of the Gaussian distribution) of the low concentration regions 4ns1 and 4nd1 of d is approximately equal to, for example, about 0.15 μm. In the first embodiment, the lower portions of the low concentration regions 4ns1 and 4nd1 are in contact with the semiconductor region 5p.

However, in the first embodiment, the semiconductor region 5p includes the source region 4ns and the drain region 4n.
It is formed apart from the high concentration regions 4ns2 and 4nd2 of d. Thereby, the semiconductor region 5p and the source region 4ns
Since the width of the depletion layer between the drain region 4nd and the drain region 4nd can be widened, the diffusion capacitance can be reduced. Therefore, it is possible to improve the operating speed of the nMOS 4n. For example, the operation speed can be improved by 5 to 10% as compared with the structure in which the semiconductor region for punch-through suppression overlaps the source / drain region.

The semiconductor region 5p is formed so as to extend below the field insulating film 3. As a result, the semiconductor region 5p also functions as a region that enhances the element isolation function.

On the other hand, the pMOS 4p includes a pair of source region 4ps and drain region 4pd and a channel region 4p.
c, a gate insulating film 4pi, and a gate electrode 4pg.

The source region 4ps and the drain region 4pd are low-concentration regions 4ps1 and 4pd1 and high-concentration regions 4ps2 and 4pd2 formed on the semiconductor substrate 1.
And a conductor film (conductor film) 4ps3, 4pd3 formed on the high-concentration regions 4ps2, 4pd2.

The low-concentration regions 4ps1 and 4pd1 are formed on the side of the channel region 4pc, and one end of the low-concentration regions 4ps1 and 4pd1 is formed to extend slightly over the end of the gate electrode 4pg.

The low concentration regions 4ps1 and 4pd1 contain, for example, p-type impurity boron, and the impurity concentration is, for example, about 3 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ . The depth (center of Gaussian distribution) of the low concentration regions 4ps1 and 4pd1 is, for example, about 0.15 μm.

The high concentration regions 4ps2 and 4pd2 are formed outside the low concentration regions 4ps1 and 4pd1. The high-concentration regions 4ps2 and 4pd2 contain, for example, p-type impurity boron, and the impurity concentration is, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ .

The depth of the high-concentration regions 4ps2 and 4pd2 (the center of the Gaussian distribution) is extremely thin, for example, 0.1 μm or less. This is the high concentration area 4ps2,4p
Since the conductor films 4ps3 and 4pd3 stacked on the upper layer of d2 also function as the source region 4ps and the drain region 4pd, the semiconductor regions for the source / drain regions that must be formed above the semiconductor substrate 1 are correspondingly formed. Because it can be thin. This conductor film 4ps3, 4pd3
Is made of, for example, p-type Si single crystal, and the side surface of the gate electrode 4pg side is inclined.

The channel region 4pc is the source region 4ps.
And low concentration regions 4ps1 and 4pd of the drain region 4pd
It is provided between 1 and 2. The channel region 4pc is a conductive path of carriers flowing between the source region 4ps and the drain region 4pd, and is formed by applying a predetermined voltage to the gate electrode 4pg. The gate length (Lg)
Is, for example, about 0.2 μm to 0.4 μm.

The gate insulating film 4pi is made of, for example, SiO ₂ . The gate electrode 4pg is made of, for example, low resistance polysilicon. However, the structure of the gate electrode 4pg is not limited to the single-layer structure of low-resistance polysilicon and can be variously modified. For example, a single-layer gate structure of only tungsten may be used, or for example, a low-resistance polysilicon film may be formed. A polycide structure formed by depositing a tungsten silicide film may be used.

A side wall 4sw made of, for example, SiO ₂ is provided on each of the side surface and the upper surface of the gate electrode 4pg.
And the cap insulating film 4c is formed.

By the way, in the first embodiment, below the channel region 4pc in the pMOS 4p,
A semiconductor region 5n for suppressing a leak current from flowing between the source region 4ps and the drain region 4pd is formed in the n well 2n so as to extend in the lateral direction of FIG.

By providing such a semiconductor region 5n, even if the gate length (Lg) is shortened, the source region 4 is formed.
Since the leak current between the ps and the drain region 4pd can be suppressed, the pMO caused by the leak current is reduced.
It is possible to suppress the variation of the threshold voltage of S4p.

In the semiconductor region 5n, the source region 4p
n of the conductivity type opposite to that of s and the drain region 4pd
^It contains ⁺ -form phosphorus or As, and the impurity concentration thereof is, for example, about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ .

The depth of the semiconductor region 5n (center of Gaussian distribution) is the source region 4ps and the drain region 4p.
The depth (the center of the Gaussian distribution) of the low-concentration regions 4ps1 and 4pd1 of d is approximately equal to, for example, about 0.15 μm. In the first embodiment, the lower portions of the low concentration regions 4ps1 and 4pd1 are in contact with the semiconductor region 5n.

However, in the first embodiment, the semiconductor region 5n includes the source region 4ps and the drain region 4p.
It is formed apart from the high concentration regions 4ps2 and 4pd2 of d.

As a result, the width of the depletion layer between the semiconductor region 5n and the source region 4ps and the drain region 4pd can be widened, so that the diffusion capacitance can be reduced. Therefore, it is possible to improve the operation speed of the pMOS 4p. For example, the operation speed can be improved by 5 to 10% as compared with the structure in which the semiconductor region for punch-through suppression overlaps the source / drain region.

The semiconductor region 5n is formed so as to extend below the field insulating film 3. As a result, the semiconductor region 5n also functions as a region for enhancing the element isolation function.

Such nMOS 4n and pMOS 4
p is, for example, BPSG (Boron Phospholous Silicate G)
It is covered with an interlayer insulating film 6a made of lass) or the like. The upper surface of the interlayer insulating film 6a is flattened.

First layer wirings 7a1 to 7a3 made of, for example, an aluminum (Al) -Si-copper (Cu) alloy or tungsten are formed on the interlayer insulating film 6a.

The first layer wiring 7a1 is formed on the conductor film 4ns3 through the connection hole 8a formed at a predetermined position of the interlayer insulating film 6a.
Is electrically connected to Also, the first layer wiring 7a2
Is a connection hole 8a formed at a predetermined position of the interlayer insulating film 6a.
Is electrically connected to the conductor films 4ps3 and 4nd3 through. Further, the first-layer wiring 7a3 is formed on the conductor film 4pd through the connection hole 8a formed at a predetermined position of the interlayer insulating film 6a.
Electrically connected to 3.

On the interlayer insulating film 6a, for example, Si
An interlayer insulating film 6b made of O ₂ is deposited, which covers the first layer wirings 7a1 to 7a3. On the upper surface of the interlayer insulating film 6b, for example, Al-Si-Cu is formed.
Second layer wiring 7b made of an alloy, tungsten or the like is formed. The second layer wiring 7b is formed by the interlayer insulating film 6b.
Is electrically connected to the first-layer wiring 7a2 through a connection hole 8b drilled at a predetermined position.

On the interlayer insulating film 6b, for example, Si
An interlayer insulating film 6c made of O ₂ is deposited, which covers the first layer wiring 7b. On the upper surface of this interlayer insulating film 6c, a third layer wiring 7c made of, for example, an Al-Si-Cu alloy or tungsten is formed. The third layer wiring 7c is electrically connected to the second layer wiring 7b through a connection hole 8c formed at a predetermined position of the interlayer insulating film 6c.

A surface protective film 9 made of, for example, SiO ₂ is deposited on the interlayer insulating film 6c to cover the third layer wiring 7c. The surface protective film 9 is formed by laminating protective films 9a and 9b in order from the lower layer.

The lower protective film 9a is made of, for example, SiO ₂ . The upper protective film 9b is made of, for example, silicon nitride. An opening 10 is formed in the surface protective film 9, and the bonding pad portion BP of the third-layer wiring 7c is exposed from the opening 10.

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 2, p-type impurity boron and n-type impurity phosphorus or As are separately implanted into an nMOS formation region and a pMOS formation region of a p ^{− type} semiconductor substrate 1 by an ion implantation method or the like. After the introduction, heat treatment is applied to p well 2p and n well 2
form n.

The impurity dose at this time is, for example, 1 ×.
The implantation energy is about 10 ¹³ / cm ² , and the implantation energy is about 60 keV, for example. The heat treatment temperature at the time of forming the p well 2p and the n well 2n is, for example, 1
The temperature is about 200 ° C., and the processing time is, for example, about 3 hours.

Then, in the element isolation region of the semiconductor substrate 1,
For example, the field insulating film 3 made of SiO _{2 is} formed by LOCO
It is selectively formed by the S (Local Oxidation of Silicon) method or the like.

After that, a photoresist pattern 11a exposing the nMOS formation region is formed on the semiconductor substrate 1 by a photolithography technique, and then the semiconductor substrate 1 is used as a mask.
In order to form a semiconductor region for suppressing punch through, boron, which is a p-type impurity, is introduced by an ion implantation method or the like.

Next, after removing the photoresist pattern 11a, as shown in FIG. 3, a photoresist pattern 11b which exposes the pMOS formation region is formed by a photolithography technique, and the photoresist pattern 11b is used as a mask. In order to form a punch-through suppressing semiconductor region in the semiconductor substrate 1, for example, n-type impurity phosphorus or As is introduced by an ion implantation method or the like.

As described above, in the first embodiment,
When forming the semiconductor region for punch-through suppression, the impurity may be ion-implanted over the entire main surface of the semiconductor substrate 1, so that the step of introducing the impurity for forming the semiconductor region is facilitated.

Then, after removing the photoresist pattern 11b, the semiconductor substrate 1 is heat-treated to form punch-through suppressing semiconductor regions 5p and 5n as shown in FIG.

Then, on the semiconductor substrate 1, gate insulating films 4ni and 4pi are formed in the element forming region surrounded by the field insulating films 3 and 3 by a thermal oxidation method or the like.

Next, a conductor film made of, for example, low-resistance polysilicon is formed on the semiconductor substrate 1 by the CVD method or the like, and an insulating film made of, for example, SiO ₂ is deposited on the conductor film by the CVD method or the like. The gate electrode 4 is formed by patterning the conductor film and the insulating film by a photolithography technique, a dry etching method, or the like.
ng, 4 pg and the cap insulating film 4c are formed.

Subsequently, an insulating film made of, for example, SiO ₂ is deposited on the semiconductor substrate 1 by the CVD method or the like, and then the insulating film is etched back to form the gate electrodes 4ng and 4pg and the cap insulating film. Sidewalls 4sw are formed on the side surfaces of 4c.

After that, the insulating film between the sidewalls 4sw and the field insulating film 3 is removed to expose a part of the upper surface of the semiconductor substrate 1, and then the exposed surface of the semiconductor substrate 1 is exposed as shown in FIG. As shown, the semiconductor film 12 made of, for example, Si single crystal is formed by the selective epitaxial growth method or the like. At this time, the gate electrode 4ng of the semiconductor film 12
An inclination is formed on the side surface on the 4 pg side.

Conditions for this epitaxial growth are, for example, as follows. That is, the processing temperature is
For example, about 750 ° C to 850 ° C, and the processing time is, for example, 1
Min-5 min, the processing gas is, for example, dichlorosilane (S
iH ₂ Cl ₂ ) gas.

Next, as shown in FIG. 6, the semiconductor substrate 1
After forming a photoresist pattern 11c covering the pMOS formation region, an n-type impurity such as phosphorus or As is implanted by an ion implantation method or the like from a direction oblique to the main surface of the semiconductor substrate 1. This allows
In the semiconductor substrate 1, n-type impurities are introduced below the sidewalls 4sw and into the conductor film 12. The dose amount of impurities at this time is, for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁵ / cm ^2.
And the driving energy is, for example, 150 ke
About V.

Then, the photoresist pattern 11
After removing c, a photoresist pattern 11d is formed on the semiconductor substrate 1 so as to cover the nMOS formation region.

Subsequently, as shown in FIG. 7, the semiconductor substrate 1
For example, p-type impurity boron is implanted by an ion implantation method or the like from a direction oblique to the main surface of the. This allows
In the semiconductor substrate 1, p-type impurities are introduced below the sidewalls 4sw and into the conductor film 12. The dose amount of impurities at this time is, for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁵ / cm ^2.
And the driving energy is, for example, 150 ke
About V.

Then, after removing the photoresist pattern 11d, the semiconductor substrate 1 is heat-treated. As a result, the impurities introduced into the semiconductor substrate 1 and the conductor film 12 are activated, and the impurities contained in the conductor film 12 are diffused toward the semiconductor substrate 1 side, so that the low concentration regions 4ns1 and 4nd1 shown in FIG. , 4ps1,4pd1, high concentration area 4ns
2,4nd2,4ps1,4pd1 and conductor film 4ns3,4p
form s3.

After that, the semiconductor integrated circuit device is manufactured according to the usual process of MOS • FET.

That is, as shown in FIG. 1, after the interlayer insulating film 6a made of, for example, BPSG is deposited on the semiconductor substrate 1 by the CVD method or the like, its upper surface is flattened by the reflow method or the etch back method. To do.

Subsequently, the source regions 4ns and 4ps and the drain regions 4nd and 4ns are formed at predetermined positions of the interlayer insulating film 6a.
A connection hole 8a that exposes part of 4 pd is formed by photolithography and dry etching.

Then, on the semiconductor substrate 1, for example, Al--
After depositing a conductor film made of a Si--Cu alloy by a sputtering method or the like, the conductor film is patterned by a photolithography technique and a dry etching technique to form first layer wirings 7a1 to 7a3.

Then, for example, Si is formed on the interlayer insulating film 6a.
After covering the first layer wirings 7a1 to 7a3 by depositing an interlayer insulating film 6b made of O ₂ by the CVD method or the like, the first layer wiring 7a2 is formed at a predetermined position on the interlayer insulating film 6b.
The connection hole 8b is bored so that a part of it is exposed.

Then, on the semiconductor substrate 1, for example, Al--
After depositing a conductor film made of a Si—Cu alloy by a sputtering method or the like, the conductor film is patterned by a photolithography technique and a dry etching technique to form the second layer wiring 7b.

Then, for example, Si is formed on the interlayer insulating film 6b.
After the second layer wiring 7b is covered by depositing the interlayer insulating film 6c made of O ₂ by the CVD method or the like, a part of the second layer wiring 7b is exposed at a predetermined position of the interlayer insulating film 6c. The connection hole 8c is drilled.

Then, on the semiconductor substrate 1, for example, Al--
After depositing a conductor film made of a Si—Cu alloy by a sputtering method or the like, the conductor film is patterned by a photolithography technique and a dry etching technique to form a third layer wiring 7c.

Then, for example, Si is formed on the interlayer insulating film 6c.
A surface protective film 9 is formed by sequentially depositing a protective film 9a made of O ₂ and a protective film 9b made of silicon nitride from the lower layers by a CVD method or the like, and covers the third layer wiring 7c.

After that, the opening 10 is formed in the surface protective film 9 so that the bonding pad portion BP of the third layer wiring 7c is exposed.
To form In this way, the semiconductor integrated circuit device shown in FIG. 1 is manufactured.

As described above, according to the first embodiment, the following effects can be obtained.

(1). Semiconductor region 5 for punch-through suppression
By providing p and 5n, nMOS 4n and pM
In the OS 4p, the leak current between the source regions 4ns and 4ps and the drain regions 4nd and 4pd can be suppressed.

(2) Due to the above (1), it is possible to improve the electrical characteristics of the nMOS 4n and the pMOS 4p.

(3). Since the channel length of the nMOS 4n and the pMOS 4p can be shortened by the above (1), the nMOS 4n and the pMOS 4p can be miniaturized.

(4). Source regions 4ns and 4ps and drain regions 4nd and 4p of nMOS 4n and pMOS 4p
d is a low concentration region 4ns formed on the semiconductor substrate 1
1, 4ps1, 4nd1, 4pd1 and high concentration region 4ns2,
4ps2, 4nd2, 4pd2 and the conductor film 4ns3, 4ps3, 4nd3, 4pd3 formed on the upper layer thereof to thin the high-concentration regions 4ns2, 4ps2, 4nd2, 4pd2 formed on the semiconductor substrate 1 side. Is possible.

(5). Due to the above (4), miniaturization of the nMOS 4n and the pMOS 4p can be promoted.

(6). By the above (4), the source regions 4ns, 4
ps and drain regions 4nd and 4pd, the high-concentration regions 4ns2, 4ps2, 4nd2 and 4pd2 and the punch-through suppressing semiconductor regions 5p and 5n can be widened. It is possible to reduce the capacitance of the regions 4nd and 4pd. As a result, nMOS4n and pMOS4p
It is possible to improve the operating speed of.

(7). The punch-through suppressing semiconductor region 5p, is formed over almost the entire lower layer of the nMOS 4n and pMOS 4p.
By providing 5n, it is possible to suppress the noise generated inside the semiconductor substrate 1 from adversely affecting the nMOS 4n and the pMOS 4p. Therefore, nMO
It is possible to improve the operational reliability of S4n and pMOS4p.

(8). Punch-through suppressing semiconductor region 5
By providing n and 5p also in the lower layer of the field insulating film 3, it becomes possible to improve the element isolation capability.

(9). Due to the above (1) to (8), it is possible to realize a semiconductor integrated circuit device having a CMOS circuit which is fine and capable of stable operation at high speed.

(10). Punch-through suppressing semiconductor region 5
By introducing the impurities for forming p, 5n to the entire surface of the semiconductor substrate 1, it becomes possible to facilitate the step of introducing the impurities for forming the semiconductor regions 5p, 5n.

(Embodiment 2) FIG. 8 is a cross-sectional view of essential parts of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the second embodiment, as shown in FIG. 8, the conductor films 4ns3, 4nd3, 4ps3, 4pd3 for forming the source / drain of the nMOS 4n and pMOS 4p.
A silicide layer (compound layer) 13 made of, for example, tungsten silicide is formed on the upper part of the. Other than this, the structure is the same as that of the first embodiment.

The silicide layer 13 is not limited to tungsten silicide but can be variously modified, and may be molybdenum silicide or titanium silicide, for example. To form the silicide layer 13, for example, after forming the semiconductor film 12 (see FIG. 5), a metal film made of, for example, tungsten is deposited on the semiconductor substrate 1, and then heat treatment is performed to form the metal film and the semiconductor. It may be formed by silicidizing the contact portion with the film 12.

In the second embodiment, in addition to the effects obtained in the first embodiment, the following effects can be obtained. That is, since the resistance of the conductor films 4ns3, 4nd3, 4ps3, 4pd3 can be lowered, the nMOS 4n and pMO can be reduced.
It is possible to improve the operation speed of S4p.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned Embodiments 1 and 2, and does not depart from the gist of the invention. It goes without saying that various changes can be made.

For example, in the first and second embodiments, the case where the conductor film forming the source region and the drain region is made of Si single crystal of a predetermined conductivity type has been described.
The present invention is not limited to this, and various changes can be made. For example, low resistance polysilicon may be used.

In the above description, the invention made by the present inventor is the field of application which is the background of the invention.
The case where the present invention is applied to the semiconductor integrated circuit device having the S circuit has been described, but the present invention is not limited to this, and the present invention can also be applied to, for example, a semiconductor integrated circuit device having a BiCMOS (Bipolor CMOS) circuit, a DRAM or an SRAM.

[0105]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1). According to the semiconductor integrated circuit device of the present invention, by providing the punch-through suppressing semiconductor region, M
Since the IS transistor can be miniaturized, and the punch-through suppressing semiconductor region is provided separately from the source region and the drain region, the punch-through suppressing semiconductor region and the source region and the drain region are separated from each other. Since the width of the depletion layer between them can be widened, it is possible to suppress an increase in the capacitance of the source region and the drain region. Therefore, it is possible to realize a fine semiconductor integrated circuit device having a MIS transistor capable of stable operation at high speed.

(2) According to the semiconductor integrated circuit device of the present invention, by forming a punch-through suppressing semiconductor region in the lower layer of the source region, drain region and channel region of the MIS transistor, almost all of the MIS transistor is formed. Since the punch-through suppressing semiconductor layer is arranged over the region, it is possible to suppress the noise generated inside the semiconductor substrate from adversely affecting the MIS transistor. Therefore, it is possible to improve the operational reliability of the MIS transistor.

(3) According to the semiconductor integrated circuit device of the present invention, the source region and the drain region of the MIS transistor are constituted by the semiconductor region formed on the semiconductor substrate and the conductor film formed on the semiconductor region. By
The semiconductor region for forming the source / drain regions formed on the semiconductor substrate side can be thinned. For this reason,
It becomes possible to promote miniaturization of the MIS transistor. Further, since the distance between the semiconductor region for forming the source / drain region and the semiconductor region for suppressing punch through can be widened, it is possible to further reduce the capacitance of the source region and the drain region. With these, it becomes possible to realize a fine semiconductor integrated circuit device having a MIS transistor capable of stable operation at high speed.

(4). According to the semiconductor integrated circuit device of the present invention, by forming a compound layer with a predetermined conductor material on the upper layer portion of the conductor film forming the source region and the drain region of the MIS transistor, Since the resistance of the conductor film for the source / drain structure can be reduced, the operating speed of the semiconductor integrated circuit device can be improved.

(5). According to the method for manufacturing a semiconductor integrated circuit device of the present invention, impurities for forming the punch-through suppressing semiconductor region are introduced into the entire surface of the semiconductor substrate to thereby form the semiconductor region. It becomes possible to facilitate the step of introducing impurities for forming.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention;

2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;

3 is a main-portion cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during the manufacturing process following that of FIG. 2;

FIG. 4 is a cross-sectional view of essential parts in the manufacturing process of the semiconductor integrated circuit device of FIG. 1 subsequent to FIG. 3;

5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 4;

6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 5;

7 is a main-portion cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during the manufacturing process following that of FIG. 6;

FIG. 8 is a cross-sectional view of essential parts of a semiconductor integrated circuit device according to another embodiment of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2p p well 2n n well 3 field insulating film 4n n channel type MOS / FET 4p p channel type MOS / FET 4nc, 4pc channel region 4ns, 4ps source region 4ns1, 4ps1 low concentration region 4ns2, 4ps2 high concentration Region 4ns3,4p s3 Conductor film 4nd, 4pd Drain region 4nd1, 4pd1 Low concentration region 4nd2, 4pd2 High concentration region 4nd3, 4p d3 Conductor film 4ni, 4pi Gate insulating film 4ng, 4pg Gate insulating film 4c Side electrode 4sw 5p Semiconductor region 6a to 6c Interlayer insulating film 7a1 to 7a3 First layer wiring 7b Second layer wiring 7c Third layer wiring 8a to 8c Connection hole 9 Surface protective film 9a, 9b Protective film 10 Opening 11a to 11d Photoresist pattern 12 Semiconductor film 13 Silicide layer (compound Layer)

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Katsumi Tsuneno 2326 Imai, Ome City, Tokyo, Hitachi, Ltd. Device Development Center (72) Inko Inahiko 2326, Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Hisaaki Kunitomo Device Development Center, Hitachi, Ltd. 2326 Imai, Ome City, Tokyo

Claims (5)

[Claims] 1. A semiconductor integrated circuit device having a MIS transistor on a semiconductor substrate, wherein a punch is provided at a position apart from the source region and the drain region in a lower layer of the source region, the drain region and the channel region of the MIS transistor. A semiconductor integrated circuit device having a semiconductor region for suppressing slew. 2. The semiconductor integrated circuit device according to claim 1, wherein the source region and the drain region are constituted by a semiconductor region formed on the semiconductor substrate and a conductor film provided on the semiconductor region. A semiconductor integrated circuit device characterized by the above. 3. The semiconductor integrated circuit device according to claim 2, wherein a compound layer with a predetermined conductor material is formed on an upper layer portion of the conductor film forming the source region and the drain region. apparatus. 4. The semiconductor integrated circuit device according to claim 2, wherein a channel side end of the semiconductor region forming the source region and the drain region is formed to be deeper than other portions. Semiconductor integrated circuit device. 5. A method of manufacturing a semiconductor integrated circuit device having a MIS transistor on a semiconductor substrate, comprising: (a) introducing an impurity for forming a punch-through suppressing semiconductor region on the entire surface of the semiconductor substrate. And (b) forming a gate insulating film and a gate electrode of the MIS transistor on the semiconductor substrate, (c) covering the periphery of the gate electrode with an insulating film, and (d) forming the gate electrode. A step of forming a semiconductor film on the exposed surface of the semiconductor substrate after exposing the surrounding semiconductor substrate; and (e) forming a semiconductor film on the exposed surface of the semiconductor substrate from an oblique direction with respect to the main surface thereof. A step of introducing impurities, and (f) after introducing impurities into the semiconductor film, the impurities in the semiconductor film are prevented from overlapping the semiconductor region for punch-through suppression on the semiconductor substrate side. To the MI,
And a step of forming a semiconductor region forming a source region and a drain region of the S transistor.