JPH1098186A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a sufficiently high resistance with less area and without increase the manufacturing processes by forming a resistor at the same time as when an LDD area of MOS transistor is formed, and using a diffusion area of a high resistance value wherein a mask is formed on its surface at the same when a side wall is formed as a resistor. SOLUTION: In this device, a diffusion area 23 of low concentration and shallow junction depth is formed in succession to a diffusion area 41. The diffusion area 23 is formed at the same time when an LDD area of a transistor is formed, and in the process thereafter, an insulating film 32 prevents formation of a silicide layer on the surface or additional ion implantation, thus a high resistance value is kept. With the diffusion area 23 used as a parasitic resistance of a transistor, a high resistance is formed with less area. The formation of diffusion area 23 makes the insulating film 32 remain in a specified area, so a single process of PEP for forming a resist mask 25 is only added. Thus, with less area, the increase in the manufacturing processes is made small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a semiconductor device suitable for miniaturization having a diffusion resistance and a parasitic resistance and a method of manufacturing the semiconductor device.

[0002]

2. Description of the Related Art Conventionally, advances have been made in miniaturization techniques and low resistance techniques for semiconductor devices. The technology for lowering resistance is represented by, for example, a reduction in parasitic resistance of a transistor formed in an integrated circuit, a reduction in contact resistance of a wiring layer, and the like.
Also, the diffusion resistance to be formed in the semiconductor substrate has become easier to form a resistance having a low resistance value due to the progress of silicide technology and the like. With the advancement of these miniaturization and low resistance technologies, high speed semiconductor devices have been achieved.

Conventionally, the diffusion resistance in the process of manufacturing an integrated circuit has a low resistance (hereinafter referred to as low resistance).
Is formed, a diffusion layer having a high concentration and a deep junction depth is formed, and a resistor having a high resistance value (hereinafter, referred to as a high resistance) is formed.
In the formation of a diffusion layer, a diffusion layer having a low concentration and a small junction depth is generally formed.

[0004] By the way, an integrated circuit is required to perform a variety of operations depending on the product, and in some cases, a resistance element having a certain high resistance value is required. For example, in an input / output circuit in an integrated circuit, the surge voltage does not destroy the gate oxide film of the transistor.
It is necessary to use a high resistance for the input section. Many of the elements used for the input / output unit use a transistor and a parasitic resistance added to a diffusion region of the transistor. The manufacturing method will be briefly described below.

First, as shown in FIG. 3A, a semiconductor substrate 111 is prepared, an element isolation insulating film 112 is formed in an element isolation region on the surface thereof, and a gate insulating film 113 is formed on the surface of the substrate 111. I do. Next, a conductive film such as polycrystalline silicon is formed on the entire surface, a resist pattern (not shown) is formed on the surface thereof, and etching is performed using the resist pattern as a mask to form a gate electrode 114.

Subsequently, as shown in FIG. 3B, using the gate electrode 114 and the like as a mask, the LDD (Li
In order to form a gthly doped drain (region), impurities of the opposite conductivity type to the substrate 111 are ion-implanted to form low concentration diffusion regions (source or drain regions) 121 and 122. Next, an insulating film is deposited on the entire surface of the substrate 111 and is anisotropically etched to form a sidewall 123 on the side surface of the gate electrode 114.

Subsequently, as shown in FIG. 3C, the gate electrode 114, the sidewall 123 and the like are used as masks.
Diffusion regions 131 and 132 are formed by ion-implanting impurities of a conductivity type opposite to that of the substrate 111. Next, an interlayer insulating film 133 is formed over the entire surface of the substrate 111. Next, a contact hole 134 reaching the diffusion regions 131 and 132 is formed in the interlayer insulating film 133, and a wiring layer 135 is formed using a conductive film such as Al. Through the above steps, a transistor with added parasitic resistance can be formed. Here, the parasitic resistance is formed inside the diffusion region 131, and its equivalent circuit is as shown in FIG. FIG. 4 is a top view of the transistor in the vicinity of the cross section in FIG. Here, the same portions are denoted by the same reference numerals. In FIG. 4, reference numeral 141 denotes an input / output pad.

As shown in FIGS. 3C and 4, the parasitic resistance added to the diffusion region 131 of the transistor uses the diffusion region for forming the source and drain regions of the transistor. The parasitic resistance has the same junction depth and impurity concentration as those of the source and drain regions. In order to make the transistor operate at higher speed, the diffusion region of the transistor is increasingly formed with a high impurity concentration. Therefore, in the above manufacturing method, it is becoming difficult to obtain a sufficiently high resistance especially as a parasitic resistance of a transistor used for an input / output circuit. Further, in forming transistors, silicide technology has come to be used particularly for the purpose of reducing contact resistance. When silicide technology is used in the above manufacturing method,
Since a low-resistance salicide is also formed on the surface of the diffusion region, a sufficiently high resistance cannot be obtained.

Therefore, in order to increase the resistance value of the parasitic resistance, it is necessary to provide a sufficient distance between the gate electrode 114 and the contact hole 134 to increase the area of the diffusion region. The area occupied by the transistor increases.

The resistance element can be formed not as a parasitic resistance but as a diffusion resistance in a region different from the transistor formation region. In this case, however, salicide is not formed on the surface of the region. In addition, it is necessary to take measures such as peeling off the salicide once formed or applying a mask so that the salicide is not formed. Further, in this case, a region for forming an element isolation insulating film for isolating the diffusion resistance is required, which increases the number of steps and is not suitable for miniaturization.

[0011]

As described above, in the conventional semiconductor device, the speed of element operation has been increased by the progress of the miniaturization technology and the technology of reducing the resistance. However, some integrated circuits, such as input / output circuits, need to have a high resistance.

Conventionally, as a resistor element used in an integrated circuit, a parasitic resistor which is formed adjacent to a MOS transistor and at the same time as its source or drain region and has a high concentration and a deep junction depth is used, or is separated from the transistor. The diffusion resistance is formed by adding a diffusion resistor having a low concentration and a shallow junction depth to the region. However, in order to increase the resistance value, there are problems in that the number of manufacturing steps increases and the area required for the resistance increases.
In particular, when a low resistance technology such as salicide technology is used, a large occupation area is required for forming a high resistance element,
In some cases, miniaturization is hindered due to an increase in the number of steps. This problem is particularly acute in input / output circuits in integrated circuits that require high resistance.

In view of the above situation, according to the present invention, in the manufacture of a transistor using the salicide technique, there is little increase in the number of manufacturing steps, and a semiconductor device occupying less area of a resistance element and a method of manufacturing a semiconductor device as compared with the prior art. I will provide a.

[0014]

The present invention employs the following means to solve the above problems. That is, in the semiconductor device of the present invention, the first conductivity type semiconductor substrate, the electrode formed on the semiconductor substrate via the insulating film, and the semiconductor substrate surface at both ends immediately below the electrode are formed separately from each other. First and second diffusion regions of a second conductivity type having a first concentration,
In the semiconductor device having the third and fourth diffusion regions of the second conductivity type having a higher concentration than the first concentration and electrically connected to each of the first and second diffusion regions, the semiconductor substrate surface A fifth diffusion region of the second conductivity type formed simultaneously with the first and second diffusion regions, and the fifth diffusion region is electrically connected to one of the third or fourth diffusion regions. It is characterized by the following. Further, in the method for manufacturing a semiconductor device of the present invention, a step of forming a gate insulating film on the surface of the first conductivity type semiconductor substrate, a step of forming a gate electrode on the surface of the gate insulating film, and using the gate electrode as a mask A step of introducing a first concentration of a second conductivity type impurity near the surface of the semiconductor substrate to form a low impurity concentration region; a step of forming an interlayer insulating film on the semiconductor substrate; and an etching mask on the interlayer insulating film. Forming, etching the interlayer insulating film using the etching mask as a mask, and leaving the interlayer insulating film only under the side surfaces of the gate electrode and the etching mask, and the remaining interlayer insulating film and the gate electrode. Forming a high impurity concentration region by introducing an impurity of a second conductivity type higher than the first concentration near the surface of the semiconductor substrate using To provide a method of manufacturing a semiconductor device characterized by having and. Alternatively, a step of forming a gate electrode in a partial region on the first conductivity type semiconductor substrate; a step of forming an LDD region and a low impurity concentration region of a MOS transistor using the gate electrode as a mask; Forming an insulating film, forming an etching mask on the interlayer insulating film on the low impurity concentration region, etching the interlayer insulating film using the etching mask as a mask, forming the side surface of the gate electrode and the etching mask A step of forming the source region and the drain region near the surface of the semiconductor substrate using the remaining interlayer insulating film and the gate electrode as a mask. .

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. FIG.
As shown in FIG. 1A, a semiconductor substrate 11 is prepared, an element isolation insulating film 12 is formed in an element isolation region on the surface thereof, and a gate insulating film 13 is formed on the surface of the substrate 11. Next, a conductive film such as polycrystalline silicon is formed on the entire surface, a resist pattern (not shown) is formed on the surface thereof, and etching is performed using the resist pattern as a mask to form the gate electrode 14.

Subsequently, as shown in FIG. 1B, the gate electrode 14 and the element isolation insulating film 12 are used as masks to form an LDD (Ligthly Doped Drain) region of the transistor. Diffusion regions (source or drain regions) 21 and 22 having a low concentration and a shallow junction depth are formed by ion-implanting conductive impurities. Here, a low concentration diffusion region 23 is also formed in the region where a high resistance is to be formed. When forming a PMOS transistor, B is dosed at 8 × 10E14 atoms · cm ⁻² and acceleration energy is about 15 keV. When forming an NMOS transistor, P or As is dosed at 8 × 10E14atoms · cm ⁻² , Acceleration energy 1
Perform ion implantation at about 5 keV. Next, L
P-CVD (Low Pressure-Chemical Vapor Depositio
An insulating film 24, for example, a silicon nitride film or a silicon oxide film is deposited by the method n). Next, a normal PEP (Photo Engraving Process) is formed on the substrate 11 in a region where a high resistance is to be formed.
To form a resist mask 25. The dimension of the resist mask 25 is about 10 to 20 μm, but the dimension can be appropriately selected according to the resistance value of the resistor to be formed.

Subsequently, as shown in FIG. 1C, the insulating film 24 is anisotropically etched using the resist mask 25 as a mask, a sidewall 31 is formed on the side surface of the gate electrode 14, and the substrate 11 in a region where a high resistance is to be formed. The insulating film 32 is left thereon. Next, the resist mask 25 is removed by ashing or the like.

Subsequently, as shown in FIG. 1D, impurities of the opposite conductivity type to that of the substrate 11 are ion-implanted by using the element isolation insulating film 12, the gate electrode 14, the sidewall 31, and the insulating film 32 as a mask and diffused. Regions 41, 42 and 43 are formed. In the operation of the transistor, the diffusion regions 41 and 42 function as source or drain regions. When forming a PMOS transistor, B is dosed at 3 × 10E15atoms.
・ Cm ^-2 , acceleration energy is about 30keV, and when forming NMOS transistor, As dose is 3 × 10E15ato
Ion implantation is performed at ms · cm ⁻² and acceleration energy of about 30 keV. Next, if necessary, a silicide layer may be selectively formed on the exposed surface of the substrate 11 by a salicide technique. With this salicide technique, the contact resistance of the diffusion regions 41 and 43 can be reduced. Since the insulating film 32 is formed on the surface of the region where the high resistance is to be formed, no silicide layer is formed. Next, an interlayer insulating film 44 is formed on the entire surface of the substrate 11. Next, a contact hole 45 reaching the diffusion regions 41 and 43 is formed in the interlayer insulating film 44, and a wiring layer 46 is formed using a conductive film such as Al. With the above steps, the manufacturing process according to the first embodiment of the present invention is completed.

In the semiconductor device manufactured according to the first embodiment of the present invention, a diffusion region 23 having a low concentration and a small junction depth is formed continuously to the diffusion region 31. This diffusion area 2
3 is formed at the same time as the formation of the LDD region of the transistor, and since the insulating film 32 is formed in the subsequent steps, a silicide layer is not formed on the surface or new ions are implanted. The value remains. Therefore, by using the diffusion region 23 having this high resistance value as the parasitic resistance of the transistor, it is possible to form a high resistance with a smaller area than in the conventional case. In order to leave 32 in a predetermined region, PEP for forming the resist mask 25 can be performed only by adding one step. Therefore, according to the present invention, it is possible to form a parasitic resistance having a sufficiently high resistance value with a smaller area and a smaller increase in the number of manufacturing steps as compared with the conventional manufacturing method.

In the above manufacturing method, the diffusion region 23 used as a high resistance is formed in a form continuous with the source or drain region of the MOS transistor.
Of course, it may be formed in another region independently of the source or drain region. Also in this case, by forming the diffusion resistance in the same step as the LDD region of the MOS transistor, it is possible to form a high resistance with a small increase in the number of manufacturing steps.

Next, a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, the parasitic resistance in the first embodiment is formed inside the LDD region of the MOS transistor.

As shown in FIG. 2A, the semiconductor substrate 51
Is formed, an element isolation insulating film 52 is formed in an element isolation region on the surface thereof, and a gate insulating film 5 is formed on the surface of the substrate 51.
Form 3 Next, a conductive film such as polycrystalline silicon is formed on the entire surface, a resist pattern (not shown) is formed on the surface thereof, and etching is performed using the resist pattern as a mask to form a gate electrode 54.

Subsequently, as shown in FIG. 2B, the gate electrode 54 and the element isolation insulating film 52 are used as masks to form an LDD (Ligthly Doped Drain) region of the transistor. Diffusion regions (source or drain regions) 61 and 62 having low concentration and shallow junction depth are formed by ion-implanting conductive impurities. The conditions for ion implantation are the same as in the first embodiment. Next, LP-CVD (Low Pressure-Chemical Vapo)
An insulating film 63, for example, a silicon nitride film or a silicon oxide film is deposited by a ur deposition method. Next, a normal PEP (Photo Engravin) is formed on the substrate 51 in a region where a high resistance is to be formed.
g Process) to form a resist mask 64. In the first embodiment, the high resistance is formed by using the region adjacent to the source or drain region of the transistor. In the second embodiment, by increasing the LDD region below the gate electrode, the parasitic resistance added to this region is increased. It is characterized in that the resistance is used as a high resistance. Therefore, the resist mask 6
4 is formed so as to cover a part on the gate electrode. Although the size of the resist mask 64 is about 10 to 20 μm,
The size can be appropriately selected according to the resistance value of the resistor to be formed.

Subsequently, as shown in FIG. 2C, the insulating film 63 is anisotropically etched using the resist mask 64 as a mask, and sidewalls 71 and 72 are formed on the side surfaces of the gate electrode 54.
To form At this time, the sidewall 72 on the side where the resist mask 64 is formed has a width corresponding to the resist mask 64 from the side surface of the gate electrode 54. Next, the resist mask 64 is removed by ashing or the like.

Subsequently, as shown in FIG. 2D, an element isolation insulating film 52, a gate electrode 54, sidewalls 71 and 7 are formed.
Using the mask 2 as a mask, impurities of the opposite conductivity type to the substrate 51 are ion-implanted to form diffusion regions 81 and 82. Here, no ions are implanted immediately below the sidewalls 72, so that a high parasitic resistance can be obtained in this LDD region. That is, the diffusion region 61 can be used as a parasitic resistance. The conditions for ion implantation are the same as in the first embodiment. Next, if necessary, a silicide layer may be selectively formed on the exposed surface of the substrate 51 by a salicide technique. With this salicide technique, the contact resistance of the diffusion regions 41 and 42 can be reduced. Note that a sidewall 72 is formed on the surface of the LDD region.
Is formed, no silicide layer is formed. Next, an interlayer insulating film 83 is formed on the entire surface of the substrate 51. Next, a contact hole 84 reaching the diffusion regions 81 and 82 is formed in the interlayer insulating film 83, and a wiring layer 85 is formed using a conductive film such as Al. With the above steps, the manufacturing process according to the second embodiment of the present invention is completed.

The semiconductor device manufactured according to the second embodiment of the present invention is characterized in that the LDD region is formed longer and is used as a parasitic resistance. The effects are the same as in the first embodiment, and a description thereof will be omitted.

[0027]

According to the present invention, a resistor is formed at the same time as the formation of the LDD region of the MOS transistor, a mask is formed on the surface thereof at the same time as the formation of the sidewall, and further, ion implantation is performed. Prevents the formation of a silicide layer on the substrate. By using the diffusion region having this high resistance value as a resistor, it is possible to form a sufficiently high resistance with a smaller area as compared with the related art and with a small increase in the number of manufacturing steps.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view of a semiconductor device illustrating a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view of a semiconductor device illustrating a second embodiment of the present invention.

FIG. 3 is a process cross-sectional view of a semiconductor device illustrating a conventional manufacturing method.

FIG. 4 is a top view of a semiconductor device illustrating a conventional problem.

FIG. 5 is an equivalent circuit of a semiconductor device.

[Explanation of symbols]

11, 51, 111 Semiconductor substrate 12, 52, 112 Element isolation insulating film 13, 53, 113 Gate insulating film 14, 54, 114 Gate electrode 14 21, 22, 23, 41, 42, 43, 61, 62, 8
Reference numerals 1, 82, 121, 122, 131, 132 Diffusion regions 24, 32, 63 Insulating films 25, 64 Resist masks 31, 71, 72, 123 Side walls 44, 83, 133 Interlayer insulating films 45, 84, 134 Contact holes 46 , 85, 135 Wiring layer 141 I / O pad

Claims (9)

[Claims] 1. A semiconductor substrate of a first conductivity type, an electrode formed on the semiconductor substrate via an insulating film, and a first concentration formed on a surface of the semiconductor substrate at both ends immediately below the electrode and separated from each other. The first and second diffusion regions of the second conductivity type having the first and second diffusion regions are electrically connected to each of the third and second diffusion regions and have a higher concentration than the first concentration. In the semiconductor device having four diffusion regions, the semiconductor substrate surface includes a fifth diffusion region of the second conductivity type formed simultaneously with the first and second diffusion regions, and the fifth diffusion region is the fifth diffusion region. A semiconductor device electrically connected to one of the third and fourth diffusion regions. 2. The semiconductor device according to claim 1, wherein said fifth diffusion region is formed in a region adjacent to any one of said first to fourth diffusion regions. 3. The semiconductor device according to claim 1, wherein said fifth diffusion region is formed in a region separated from any of said first to fourth diffusion regions. 4. The semiconductor device according to claim 1, wherein the fifth region is used as a diffusion resistor. 5. A step of forming a gate insulating film on the surface of the first conductivity type semiconductor substrate, a step of forming a gate electrode on the surface of the gate insulating film, and forming a gate electrode near the surface of the semiconductor substrate using the gate electrode as a mask. A step of forming a low impurity concentration region by introducing a first concentration of a second conductivity type impurity, a step of forming an interlayer insulating film on the semiconductor substrate, and a step of forming an etching mask on the interlayer insulating film; Etching the interlayer insulating film using the etching mask as a mask to leave the interlayer insulating film only on the side surfaces of the gate electrode and under the etching mask; and forming the semiconductor using the remaining interlayer insulating film and the gate electrode as a mask. Introducing a second-conductivity-type impurity higher in concentration than the first concentration in the vicinity of the substrate surface to form a high-impurity-concentration region. Manufacturing method of a semiconductor device. 6. A step of forming a gate electrode in a partial region on a semiconductor substrate of a first conductivity type;
Forming a DD region and a low impurity concentration region; forming an interlayer insulating film on the semiconductor substrate; forming an etching mask on the interlayer insulating film on the low impurity concentration region; Etching the interlayer insulating film using a mask as a mask to leave the interlayer insulating film only on the side surfaces of the gate electrode and under the etching mask; and using the remaining interlayer insulating film and the gate electrode as a mask, the surface of the semiconductor substrate. Forming a source region and a drain region near the semiconductor device. 7. The method according to claim 5, wherein the etching mask is formed so as to cover a part of the gate electrode. 8. The method according to claim 6, wherein the low-concentration impurity region is formed in a region adjacent to one of the source region, the drain region, and the LDD region. 9. The method according to claim 6, wherein the low-concentration impurity region is formed in a region separated from any of the source region, the drain region, and the LDD region.