JP3148227B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a MOS type semiconductor device and a method for manufacturing the same.

[Summary of the Invention]

When fabricating a general logic CMOS and a high voltage MOS transistor on a first conductivity type semiconductor substrate, a second conductivity type dopant is ionized using a first nitride film patterned near the surface of the semiconductor substrate as a mask. Implantation, depositing a second nitride film, performing anisotropic etching, forming sidewalls of the second nitride film on both sides of the first nitride film, and selectively oxidizing the field oxide film by thermal oxidation. Is formed, and at the same time, a second conductivity type impurity diffusion region is formed.
At this time, in order to selectively form a field oxide film using the second nitride film as an oxidation mask, a second conductivity type dopant is ion-implanted using the first nitride film as an implantation mask, and is diffused during thermal oxidation. Impurity diffusion region
It is formed larger than the field oxide film. Therefore, the on-resistance of the high voltage MOS transistor is reduced, and the electrostatic breakdown voltage is also improved.

[Conventional technology]

Conventionally, a step of depositing a nitride film 2 near the surface of the first conductivity type semiconductor substrate 1 as shown in FIG. 2 (a) and selectively removing it by etching, as shown in FIG. 2 (b) A step of ion-implanting a second conductivity type dopant using the patterned first photoresist 3 and nitride film 2 as a mask, and a second photo-pattern patterned as shown in FIG. 2 (c). A step of ion-implanting a first conductivity type dopant using the resist 7 and the nitride film 2 as a mask, and, as shown in FIG. 2 (d), a field oxide film 10 and a second conductivity type selectively by thermal oxidation. Forming the impurity diffusion region 9 and the impurity diffusion region 16 of the first conductivity type, and forming a gate oxide film as shown in FIG.
11 is formed, polysilicon is deposited, and a gate electrode 12 is formed by patterning.
By forming a step of forming the drain 14,
High voltage MOS transistors and CMOS circuits for general logic were formed.

[Problems to be solved by the invention]

However, the semiconductor device obtained by such a conventional technique has a problem that it is difficult to reduce the on-resistance of the high breakdown voltage MOS transistor and increase the electrostatic breakdown withstand voltage.

An object of the present invention is to provide a semiconductor device that solves the above-mentioned problem and a method for manufacturing the same.

[Means for solving the problem]

The present invention has been made to achieve the above object,
In the semiconductor device according to the present invention, a field oxide film is selectively provided near the surface of the first conductivity type semiconductor substrate, and extends from the first region surrounded by the field oxide film to a part on the field oxide film. A second gate electrode, which is larger than the field oxide film region, is provided below the field oxide film on the channel direction side surrounding the first region.
A low-concentration impurity diffusion region of a conductivity type is provided, and a high-concentration impurity diffusion region of a second conductivity type is provided in an active region without the gate electrode adjacent to the low-concentration impurity diffusion region of the second conductivity type. is there. On the other hand, the manufacturing method of the present invention provides a general logic CMOS near the surface of the first conductivity type semiconductor substrate.
Forming a first nitride film, selectively etching away the first nitride film, and forming a patterned first photoresist and the first nitride film. A step of ion-implanting a second conductivity type dopant using the film as a mask, a step of depositing a second nitride film after removing the first photoresist, and an anisotropic etching of the second nitride film Forming sidewalls of the second nitride film on both sides of the first nitride film, and forming the first photoresist using the patterned second photoresist and the first and second nitride films as masks. A step of ion-implanting a conductivity type dopant,
After removing the second photoresist, thermal oxidation is performed to selectively form a thick oxide film, and at the same time, the first conductivity type and the second conductivity type previously implanted below the thick oxide film. A step in which a dopant is diffused to form an impurity diffusion region, and a step in which the first and second nitride films are removed, a gate oxide film is formed by thermal oxidation, and polycrystalline silicon or aluminum is deposited. By selectively etching away, a gate electrode is formed,
Forming a source and a drain by selectively ion-implanting a second conductivity type dopant and forming an impurity region for substrate potential grounding by selectively ion-implanting a first conductivity type dopant; Depositing an insulating film, selectively forming a contact hole, depositing aluminum or the like, selectively etching away, forming a wiring layer, depositing a protective film over the entire surface, and selectively etching away. And a step of forming an opening for wiring.

[Action]

In the semiconductor device formed as described above, since the impurity region is formed deep under the bird's beak of the field oxide film, the on-resistance can be reduced and the electrostatic breakdown voltage due to thermal breakdown can be improved. Therefore, the characteristics of the high breakdown voltage transistor are improved.

〔Example〕

One embodiment of the present invention will be described in detail with reference to FIG.

1 (a) to 1 (h) are cross-sectional views in the channel direction of an embodiment of a high breakdown voltage MOS type semiconductor device according to the present invention. For example, in the step shown in FIG. 1A, a first nitride film 2 is deposited near the surface of the P-type substrate 1 and selectively removed by etching, and in the step shown in FIG. Using the first photoresist 3 and the nitride film 2 as masks, an impurity implantation region 4 is formed by ion implantation of a dopant P ⁺ or As ⁺ of a conductivity type opposite to that of the semiconductor substrate, as shown in FIG. 1C. In the process, a second nitride film 5 is deposited,
In the step shown in FIG. 2D, the second nitride film 5 is removed by anisotropic etching to form a nitride film sidewall 6 in contact with the end of the first nitride film 2. Here, the size of the nitride film sidewall 6 is about 0.3 to 1.0 μm. Next, in the step shown in FIG. 1E, the patterned second photoresist 7 and the first nitride film 2 are formed.
The dopant B ⁺ of the same conductivity type as that of the substrate is ion-implanted using the mask and the sidewall 6 of the nitride film as a mask to form a P-type impurity region 8 which will be a channel stopper for element isolation in the future. Although not shown, in a general CMOS logic circuit, the P-type impurity region 8 for element isolation is formed using the same mask as a nitride film serving as a mask for forming a field oxide film. Does not shorten the effective length.
Next, in the step shown in FIG. 1F, a field oxide film 10 is formed by thermal oxidation using the first nitride film 2 and the nitride film sidewall 6 as a mask. Are diffused to form a P-type impurity diffusion region 8 and an N-type impurity diffusion region 9, respectively. Here, n-type impurity diffusion region 9 is formed larger than field oxide film 10.
Therefore, an n-type region is formed deep below the bird's beak region, and local concentration of current density is reduced.

Next, in the step shown in FIG.
Is formed, polycrystalline silicon or aluminum is deposited, and a gate electrode 12 is formed by patterning.
Type Dobanto of P ⁺ or As ⁺ ions are implanted to form n-type source 13, n-type drain 14, a B ⁺ P type Dobanto ion implantation, P-type substrate 15 and P-type source and drain formed In the structure shown in FIG.
Is deposited, a contact hole is opened, and a wiring layer 17 is formed. Although not shown here, a protective film is formed and completed.

〔The invention's effect〕

According to the present invention, as described above, the width of the impurity diffusion region below the field oxide film and the width of the field oxide film are formed to have different sizes to reduce the on-resistance of the semiconductor device and improve the electrostatic breakdown withstand voltage. It is possible to provide an apparatus and a preferable manufacturing method thereof.

[Brief description of the drawings]

FIG. 1 is a sectional view of a high breakdown voltage MOS semiconductor device according to the present invention and its manufacturing process in order, and FIG. 2 is a sectional view of a conventional high breakdown voltage MOS semiconductor device in its manufacturing process. DESCRIPTION OF SYMBOLS 1 ... P-type semiconductor substrate 2 ... First nitride film 3 ... First photoresist 4 ... N-type impurity implantation region 5 ... Second nitride film 6 ... Nitride film sidewall 7 ... 2 Photoresist 8 P-type impurity implanted region 9 N-type impurity implanted region 10 Field oxide film 11 Gate oxide film 12 Gate electrode 13 N-type source 14 N-type drain 15 ... P-type substrate 16 ... Interlayer insulating film 17 ... Wiring layer

Claims (2)

(57) [Claims] A step of depositing a first nitride film on a semiconductor substrate of a first conductivity type, selectively etching away the first nitride film in at least two regions, and exposing a semiconductor surface; Ion-implanting a second conductivity type dopant using the first nitride film as a mask, depositing a second nitride film, and removing the second nitride film by anisotropic etching. A step of forming sidewalls of a second nitride film on both sides of an etched portion of the first nitride film, and a step of thermally oxidizing a portion where the first nitride film and the second nitride film are removed. Forming a thick oxide film, forming the gate oxide film by thermal oxidation after removing the first and second nitride films, depositing a conductor film, and selectively etching. Formed by removing Forming a source electrode and a drain by selectively ion-implanting a second conductive type dopant by forming a gate electrode so as to straddle two thick oxide films and a region therebetween. Production method. 2. A step of depositing a first nitride film on a semiconductor substrate of a first conductivity type, selectively exposing the first nitride film in at least three regions, and exposing a semiconductor surface; Forming a first photoresist covering at least one exposed semiconductor surface; ion-implanting a second conductivity type dopant using the photoresist and the first nitride film as a mask; Removing the photoresist, and depositing a second nitride film, and anisotropically removing the second nitride film to form a second nitride film on both sides of the etched portion of the first nitride film.
Forming a sidewall of a nitride film, forming a second photoresist covering at least two remaining semiconductor surfaces not covered by the first photoresist, and forming a patterned second photoresist. A step of ion-implanting a first conductivity type dopant using a photoresist and the first and second nitride films as a mask; and, after removing the second photoresist, forming the first nitride film and the second nitride film. Forming a thick oxide film selectively by thermally oxidizing the removed portion; and forming a gate oxide film by performing thermal oxidation after removing the first and second nitride films. By depositing a conductor film and selectively removing it by etching, a gate electrode is formed so as to straddle the two thick oxide films that have been formed, and the second conductivity type dopant is selectively formed. Method of manufacturing a MOS semiconductor device characterized by comprising a step of forming source and drain by ion implantation.