JP2000091440A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce contact resistance in the impurity diffused region of a MOSFET by forming an etching stopper film after selectively removing the sidewall spacers formed on the side surfaces of its gate electrode. SOLUTION: After selectively removing the sidewall spacers formed on the side surfaces of a gate electrode 5, an etching stopper film 10 is formed. As a result, when by applying an anisotropic etching to an interlayer insulating film 11 and the etching stopper film 10, a contact hole 12 for diffused regions is formed on a heavily-doped diffused region 9 present between the gate electrode 5 and an element isolation region 3 of a semiconductor substrate 1, and the distance between the etching stopper film 10 remaining on the side surface of the gate electrode 5 and the element isolation region 3 of the semiconductor substrate 1 can be made large. Therefore, the bottom area of the contact hole 12 for diffused regions can be increased to reduce the contact resistance in the heavily-doped diffused region 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device.
In particular, LDD (LightlyDopedDrain) structure
MISFET (MetalInsulatorSemiconductor
FieldEffectTsemiconductor integrated circuit with ransistor)
The present invention relates to technology that is effective when applied to an apparatus.

[0002]

2. Description of the Related Art MOS integrated in a semiconductor integrated circuit device
FET (M etal O xide S emiconductor F ield E ffec
t T ransistor) is refined with high integration, in particular, in the MOSFET of gate length reaches submicron channel forming region side portion of the drain region is lower impurity concentration than the impurity concentration of the other portion Adoption of the set LDD structure is an essential requirement. In the MOSFET having the LDD structure, the amount of diffusion of the drain region toward the channel forming region can be reduced, and the channel length can be secured.
Generation of the short channel effect can be suppressed. Also, L
In the MOSFET having the DD structure, the gradient of the impurity concentration distribution at the pn junction formed between the drain region and the channel forming region can be reduced, and the electric field intensity generated in this region can be reduced. Can be suppressed.

[0003] By the way, high integration of semiconductor integrated circuit devices
In order to achieve this, it is necessary to make
Distance between each structure, such as "distance between electrode and contact hole"
It is necessary to reduce the size of the alignment. Currently, SAC (Self
AlignedCMOSFET using ontact hole) technology
Above the impurity diffusion regions that will be the source and drain regions
And forming a contact hole by self-alignment on the gate electrode,
Element isolation region of semiconductor substrate and gate electrode of MOSFET
To reduce the margin of contact hole alignment
You.

[0004] Regarding the SAC technology, for example, IEDM 93 [IEDM93, p441, A No.
vel Borderless Contact / Interconnect Technolog
y Using Aluminum Oxide Etch Stop for High P
erformance SRAM and Logic].

[0005]

SUMMARY OF THE INVENTION MOSF having LDD structure
Problems in the case of forming a contact hole by using the SAC technique after forming the ET will be described with reference to FIGS. 18 to 22 (cross-sectional views for explaining a manufacturing method).

First, a groove 22 is formed in an element isolation region on the main surface of a silicon substrate 21, and an element isolation insulating film 23 made of a silicon oxide film is buried in the groove 22. The formation regions are electrically separated.

Next, as shown in FIG. 18, the MOSFET-Q4 having the LDD structure is formed in the element formation region of the silicon substrate 21.
And the MOSFET-Q5 having the LDD structure is formed. MO
Each of the SFETs Q4 and Q5 mainly serves as a silicon substrate 21 used as a channel forming region, a gate insulating film 24 made of a silicon oxide film, a gate electrode 25 made of a polycrystalline silicon film, and a source region and a drain region. The structure includes a pair of low-concentration impurity diffusion regions 27 and a pair of high-concentration impurity diffusion regions 29 serving as a source region and a drain region. The gate electrode 25 is covered on its upper surface with a cap insulating film 26 made of a silicon oxide film,
The side surface (side wall) is covered with a side wall spacer (side wall insulating film) 28 made of a silicon oxide film. The pair of low-concentration impurity diffusion regions 27 are formed in self-alignment with the gate electrode 25, and the pair of high-concentration impurity diffusion regions 29 are formed in self-alignment with the sidewall spacer 28. The gate electrodes 25 of the MOSFETs Q4 and Q5 are arranged in parallel. One high concentration impurity diffusion region 29 of MOSFET Q4 is shared with one high concentration impurity diffusion region 29 of MOSFET Q5.

Next, as shown in FIG. 19, an etching stopper film 30 is formed on the entire surface of the silicon substrate 21 so as to cover the cap insulating film 26 and the sidewall spacers 28. The etching stopper film 30 is a film having selectivity with respect to silicon oxide such as the element isolation insulating film 23, the cap insulating film 26, the sidewall spacer 28, and silicon such as the silicon substrate 21 (a film that can be selectively etched). ), For example, a silicon nitride film.

Next, an interlayer insulating film 31 is formed on the etching stopper film 30. The interlayer insulating film 31 is formed of a film having selectivity with respect to the etching stopper film 30 (a film that can be selectively etched), for example, a silicon oxide film.

Next, a resist mask M3 for forming a contact hole for the diffusion region on each of the high-concentration impurity diffusion regions 29 of the MOSFETs Q4 and Q5 is formed on the interlayer insulating film 31 by using a photolithography technique.

Next, using the resist mask M3 as an etching mask, as shown in FIG. 20, the interlayer insulating film 31 is subjected to anisotropic etching under the condition that a selectivity with respect to the etching stopper film 30 can be obtained. The etching stopper film 30 is different from the etching stopper film 30 under a condition that a selection ratio can be obtained with respect to silicon oxide such as the element isolation insulating film 23, the cap insulating film 26, the sidewall spacer 28, and the silicon such as the silicon substrate 21 as the base of the etching stopper film 30. By performing anisotropic etching, as shown in FIG. 21, a contact hole 32 for a diffusion region reaching from the surface of the interlayer insulating film 31 to the high concentration impurity diffusion region 29 is formed.

Next, the resist mask M3 is removed, and then, although not shown, a gate contact reaching the gate electrode 25 from the surface of the interlayer insulating film 31 by using the same method as the contact hole 32 for the diffusion region. Form a hole.

Next, a conductive material such as a metal is filled in the contact hole 32 for the diffusion region and the contact hole for the gate to form the conductive plug 14, and thereafter, the wiring 15 is formed. So, MOSFET Q4, Q
5 are electrically connected to the upper wiring 15.

By using the above-described method, the contact hole 32 for the diffusion region can be formed without affecting the side wall spacer 28 and the insulating film 23 for element isolation, so that the gate electrode 25 and the contact hole for the diffusion region can be formed. 32 can be reduced.

However, the side wall spacer 2
In the case where the etching stopper film 30 is formed in a portion perpendicular to the silicon substrate 31 as shown in FIG. 8, since the film thickness appears to be effectively thick as anisotropic etching, as shown in FIG. By the anisotropic etching when forming the contact hole 32, the etching stopper film 30 is left thickly in the shape of a side wall beside the side wall spacer. For this reason, the low area (the exposed area of the high concentration impurity diffusion region) of the contact hole 32 for the diffusion region is reduced, and the silicon substrate 2
The problem that the contact resistance in the high concentration impurity diffusion region 29 between the first element isolation region (element isolation insulating film 23) and the gate electrode 25 and the contact resistance in the high concentration impurity diffusion region 29 between the gate electrode 25 increases. There is.

A problem in forming a gate contact hole on an element formation region of a silicon substrate will be described with reference to FIG. 23 (a cross-sectional view for explaining a manufacturing method).

A resist mask M4 for forming a gate contact hole on the gate electrode 25 of the MOSFET Q6 is formed by using a photolithography technique to form an interlayer insulating film 31.
Form on top.

Next, using the resist mask M4 as an etching mask, the interlayer insulating film 31 is subjected to anisotropic etching under the condition that the selectivity to the etching stopper film 30 can be obtained. Anisotropic etching is performed on the etching stopper film 30 under the condition that the selectivity can be obtained with respect to the spacer 28, and then, the anisotropic etching is performed on the cap insulating film 26 with the condition that the selectivity can be obtained with respect to the gate electrode 25. ,
A gate contact hole 33 reaching the gate electrode 25 from the upper surface of the interlayer insulating film 31 can be formed on the element formation region of the silicon substrate 21.

If the above-described method is used, the cap insulating film 2
6, the amount of over-etching at the time of etching is set to be equal to or less than the thickness of the gate electrode 25.
Even when the gate contact hole 33 protrudes from 5, the gate contact hole 33 can be formed without exposing the low concentration impurity diffusion region 27 and the high concentration impurity diffusion region 29.

However, since the allowable amount of over-etching is only equivalent to the thickness of the gate electrode 25, the over-etching occurs through the conductive material (a part of the conductive plug or wiring) filled in the gate contact hole 33. In addition, the margin for the short circuit between the gate electrode and the impurity diffusion region is small.

An object of the present invention is to provide a technique capable of reducing contact resistance in an impurity diffusion region of a MISFET.

Another object of the present invention is to provide a technique capable of increasing a margin for a short circuit between a gate electrode of a MISFET and an impurity diffusion region.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0024]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) MIS is formed in an element formation region of a semiconductor substrate.
A gate electrode having an upper surface covered with a cap insulating film and a side surface covered with a sidewall spacer, a low-concentration impurity diffusion region formed in self-alignment with the gate electrode, A method for manufacturing a semiconductor integrated circuit device having a configuration having a high-concentration impurity diffusion region formed in self-alignment with the sidewall spacer, wherein the sidewall spacer is selectively removed, and Forming an etching stopper film having selectivity with respect to a base on the semiconductor substrate so as to cover the cap insulating film, and thereafter, forming an interlayer insulating film having selectivity with respect to the etching stopper film on the etching stopper film; And performing anisotropic etching on the interlayer insulating film under conditions that allow a selectivity to the etching stopper film. , Comprising the step of the anisotropic etching may be performed under conditions selected ratio can take on that underlying the etching stopper film, to form a contact hole reaching the heavily doped region from the surface of the interlayer insulating film.

(2) The first M is formed in the element formation region of the semiconductor substrate.
Each of the first MISFET and the second MISFET has an upper surface covered with a cap insulating film and a side surface covered with a side wall spacer, and A pair of low-concentration impurity diffusion regions formed in a self-aligned manner, and a pair of high-concentration impurity diffusion regions formed in a self-aligned manner with respect to the side wall spacer. Each gate electrode of the second MISFET is arranged in parallel, and one high-concentration impurity diffusion region of the first MISFET is shared between the gate electrodes and one high-concentration impurity diffusion region of the second MISFET. A method for manufacturing a semiconductor integrated circuit device, comprising: selectively removing the sidewall spacer; Forming an etching stopper film having selectivity with respect to a base on the semiconductor substrate so as to cover the insulating film, and thereafter forming an interlayer insulating film having selectivity with respect to the etching stopper film on the etching stopper film And performing anisotropic etching on the interlayer insulating film under a condition that a selectivity can be obtained with respect to the etching stopper film, and then performing anisotropic etching on the etching stopper film under a condition that a selectivity can be obtained with respect to the base. Give
Forming a contact hole reaching the high-concentration impurity diffusion region from the surface of the interlayer insulating film.

(3) The MIS is formed in the element formation region of the semiconductor substrate.
A gate electrode having an upper surface covered with a cap insulating film and a side surface covered with a sidewall spacer, a low-concentration impurity diffusion region formed in self-alignment with the gate electrode, A method for manufacturing a semiconductor integrated circuit device having a configuration having a high-concentration impurity diffusion region formed in self-alignment with the sidewall spacer, wherein the sidewall spacer is selectively removed, and Forming an etching stopper film having selectivity with respect to a base on the semiconductor substrate so as to cover the cap insulating film, and thereafter, forming an interlayer insulating film having selectivity with respect to the etching stopper film on the etching stopper film; And performing anisotropic etching on the interlayer insulating film under conditions that allow a selectivity to the etching stopper film. Performing anisotropic etching on the etching stopper film under the condition that a selection ratio can be obtained with respect to the base, and then performing anisotropic etching on the cap insulating film under the condition that the selection ratio can be obtained with respect to the gate electrode and the etching stopper film. Forming a contact hole reaching the gate electrode from the surface of the interlayer insulating film by performing reactive etching.

According to the above-mentioned means (1), the etching stopper film is formed after the side wall spacer formed on the side surface of the gate electrode is selectively removed, so that the interlayer insulating film and the etching stopper film can be formed. When anisotropic etching is performed to form a contact hole on a high-concentration impurity diffusion region between a gate electrode and a device isolation region of a semiconductor substrate, an etching stopper film remaining on a side surface of the gate electrode and a device of the semiconductor substrate Since the distance to the isolation region is increased, the bottom area of the contact hole between
(Exposed area of the high concentration impurity diffusion region) can be increased. As a result, the contact resistance in the high concentration impurity diffusion region of the MISFET can be reduced.

According to the above means (2), the etching stopper film is formed after the sidewall spacer formed on the side surface of the gate electrode is selectively removed, so that each of the interlayer insulating film and the etching stopper film is formed. When a contact hole is formed on the high concentration impurity diffusion region between gate electrodes by performing anisotropic etching, an etching stopper film remaining on the side surface of one gate electrode and an etching stopper remaining on the side surface of the other gate electrode Since the distance from the film is increased, the bottom area of the contact hole (the exposed area of the high-concentration impurity diffusion region) can be increased. As a result, the contact resistance in the high concentration impurity diffusion region of the MISFET can be reduced.

According to the above means (3), after selectively removing the sidewall spacer formed on the side surface of the gate electrode, an etching stopper film having selectivity with respect to the cap insulating film is formed. If the contact hole protrudes from the gate electrode, the allowable amount of over-etching when etching the cap insulating film is equivalent to the thickness of the gate electrode plus the cap insulating film. It is possible to increase a margin for a short circuit between the gate electrode of the MISFET and the impurity diffusion region, which is generated through the conductive material (a part of the conductive plug or the wiring) filled therein.

[0031]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) In this embodiment, an example in which the present invention is applied to a semiconductor integrated circuit device having two MOSFETs in an element formation region of a semiconductor substrate will be described.

FIGS. 1 to 10 are sectional views for explaining a method of manufacturing a semiconductor integrated circuit device according to the first embodiment of the present invention.

First, as shown in FIG. 2, a groove 2 is selectively formed in an element isolation region on a main surface of a semiconductor substrate 1 made of single crystal silicon, and then an element isolation made of a silicon oxide film is formed in the groove 2. The device insulating film 3 is buried to electrically isolate the element formation region on the main surface of the semiconductor substrate 1.

Next, the semiconductor substrate 1 is subjected to a thermal oxidation process.
The gate insulating film 4 made of, for example, a silicon oxide film having a thickness of about 4 [nm] is formed on the element formation region.

Next, on the entire surface of the semiconductor substrate 1 including the gate insulating film 4, for example, 150 [nm] serving as a gate electrode is formed.
CVD polycrystalline silicon film of the extent of film thickness (C hemical V
formed in apor D eposition) process. For example, phosphorus (P) is introduced into the polycrystalline silicon film as an impurity for reducing the resistance value.

Next, on the entire surface of the polycrystalline silicon film,
A silicon oxide film having a thickness of, for example, about 150 [nm] serving as a cap insulating film is formed by a CVD method.

Next, the silicon oxide film and the polycrystalline silicon film are sequentially subjected to anisotropic etching to form two gates each having an upper surface covered with a cap insulating film 6 on an element forming region of the semiconductor substrate 1. The electrode 5 is formed. Each of the two gate electrodes 5 is formed in parallel at a predetermined interval.

Next, a low-concentration impurity diffusion region 7 serving as a source region and a drain region is formed in the element formation region of the semiconductor substrate 1 by self-alignment with the gate electrode 5. The low-concentration impurity diffusion region 7 has an impurity such as arsenic (A
s) is formed by ion implantation. The steps so far are shown in FIG.

Next, on the entire surface of the semiconductor substrate 1 including the cap insulating film 6, silicon oxide such as the isolation insulating film 3, the gate insulating film 4, the cap insulating film 6, the semiconductor substrate 1, the gate electrode 5, etc. membrane having selectivity for silicon (film capable of selective etching), for example, a silicon nitride film formed by the CVD method, then, the silicon nitride film RIE (R eactive I on E tching ) such By performing anisotropic etching, sidewall spacers 8 are formed on the side surfaces of the gate electrode 5. The side wall spacers 8
It is formed so that the width (film thickness) in the gate length direction is, for example, about 100 [nm]. The steps so far are shown in FIG.

Next, a high-concentration impurity diffusion region 9 serving as a source region and a drain region is formed in the element formation region of the semiconductor substrate 1 by self-alignment with the sidewall spacer 8. This high concentration impurity diffusion region 9 is formed with a higher impurity concentration than the low concentration impurity diffusion region 7. The high concentration impurity diffusion region 9 is formed by introducing, for example, arsenic (As) as an impurity by an ion implantation method. By this step, in the element formation region of the semiconductor substrate 1, the portion of the drain region on the channel formation region side (low-concentration impurity diffusion region 7) has a lower impurity concentration than the other portion (high-concentration impurity diffusion region 9). An n-channel conductivity type MOSFET-Q1 having an LDD structure and an n-channel conductivity type MOSFET-Q2 having an LDD structure set to a concentration are formed. MOS
Each of the FETs Q1 and Q2 mainly serves as a semiconductor substrate 1 used as a channel forming region, a gate insulating film 4 made of a silicon oxide film, a gate electrode 5 made of a polycrystalline silicon film, and a source region and a drain region. The structure includes a pair of low-concentration impurity diffusion regions 7 and a pair of high-concentration impurity diffusion regions 9 serving as a source region and a drain region. The gate electrode 5 has a cap insulating film 6 on the upper surface.
, And the side surface is covered with the sidewall spacer 8. The pair of low-concentration impurity diffusion regions 7 is formed in self-alignment with the gate electrode 5, and the pair of high-concentration impurity diffusion regions 9 is formed in self-alignment with the sidewall spacer 8. The respective gate electrodes 5 of the MOSFETs Q1 and Q2 are arranged in parallel, and one high-concentration diffusion region 9 of the MOSFET Q1 is shared with one high-concentration diffusion region 9 of the MOSFET TQ2. The steps so far are shown in FIG.

Next, the sidewall spacers 8 are selectively removed. Since the sidewall spacers 8 are formed of a silicon nitride film, the semiconductor substrate 1, the element isolation insulating film 3, the gate insulating film 4, the gate electrode 5, the cap insulating material are formed by, for example, wet etching using phosphoric acid. The sidewall spacers 8 can be selectively removed without affecting the film 6 and the like. The steps so far are shown in FIG.

Next, an etching stopper film 10 is formed on the entire surface of the semiconductor substrate 1 so as to cover the cap insulating film 6.
Is formed by a CVD method. The etching stopper film 10
A film having a selectivity to silicon oxide such as the element isolation insulating film 3 and the cap insulating film 6 and silicon such as the semiconductor substrate 1 (a film that can be selectively etched), for example, a silicon nitride film. Also, the etching stopper film 10
Is the thickness of the sidewall spacer 8 in the gate length direction.
It is formed with a film thickness larger than (width). The steps up to this point are shown in FIG.
Shown in

Next, an interlayer insulating film 11 is formed on the etching stopper film 10. The interlayer insulating film 11 is formed of a film having selectivity to the etching stopper film 10 (a film that can be selectively etched), for example, a silicon oxide film. The steps so far are shown in FIG.

Next, a resist mask M1 for forming a contact hole for a diffusion region on each of the high-concentration impurity diffusion regions 9 of the MOSFETs Q1 and Q2 is formed on the interlayer insulating film 11 by using a photolithography technique.

Next, using the resist mask M1 as an etching mask, as shown in FIG.
1 is subjected to anisotropic etching, and thereafter, the etching stopper film 10 is differently etched under a condition that a selectivity can be obtained with respect to the semiconductor substrate 1, the element isolation insulating film 3, the cap insulating film 6, and the like. By performing anisotropic etching, as shown in FIG. 10, a contact hole 12 for a diffusion region reaching from the surface of the interlayer insulating film 11 to the high concentration impurity diffusion region 9 is formed.

In this step, the etching stopper film 10 is formed after the sidewall spacers 8 formed on the side surfaces of the gate electrode 5 are selectively removed.
Anisotropic etching is performed on each of the interlayer insulating film 11 and the etching stopper film 10 so that the gate electrode 5 and the semiconductor substrate 1 are etched.
When the diffusion region contact hole 12 is formed on the high concentration impurity diffusion region 9 between the device isolation region (device isolation insulating film 3) and the semiconductor device, the etching stopper film 10 remaining on the side surface of the gate electrode 5 and the semiconductor The distance between the substrate 1 and the element isolation region is increased. For example, the distance X between the gate electrode 5 and the element isolation region of the semiconductor substrate 1 is 0.5 [μm], and the width A of the sidewall spacer 8 in the gate length direction is 0.1 [μm].
m] and the thickness B of the etching stopper film 10 is set to 0.1 [μ
m], the width in which the contact hole for the diffusion region can be opened in the related art is distance X−width A−film thickness B = 0.3 [μ]
m], the sidewall spacer 8 replaces the etching stopper film 10 in the present embodiment.
-Film thickness B = 0.4 [μm].

Further, since the etching stopper film 10 is formed after the side wall spacer 8 formed on the side surface of the gate electrode 5 is selectively removed, the interlayer insulating film 1 is formed.
1. Anisotropic etching is performed on each of the etching stopper films 10 so that the high-concentration impurity diffusion regions 9 between the gate electrodes 5 are formed.
When the diffusion region contact hole 12 is formed thereon, the etching stopper film 1 remaining on the side surface of one of the gate electrodes 5 is formed.
The distance between 0 and the etching stopper film 10 remaining on the side surface of the other gate electrode 5 increases. For example, the distance Y between the gate electrodes 5 is 0.6 [μm], the width A of the sidewall spacer 8 in the gate length direction is 0.1 [μm], and the thickness B of the etching stopper film 10 is 0.1 [μm]. ] In the prior art, the width in which the contact hole for the diffusion region can be opened is the distance Y−width A × 2−film thickness B × 2 = 0.2 [μ]
m], on the other hand, in this embodiment, since the sidewall spacer 8 replaces the etching stopper film 10, the width over which the contact hole for the diffusion region can be opened is the distance Y
-Film thickness B × 2 = 0.4 [μm]

Next, the resist mask M1 is removed. Thereafter, although not shown, the gate electrode 5 is removed from the surface of the interlayer insulating film 11 by using the same method as that for the connection hole 12 for the diffusion region.
Is formed to reach the gate.

Next, a conductive material such as metal is filled in the connection hole 12 for the diffusion region and the connection hole for the gate to fill the conductive plug 14.
Is formed, and then, a wiring 15 is formed on the interlayer insulating film 11, thereby forming the MOSFET Q as shown in FIG.
The upper wiring 15 is electrically connected to each of Q1 and Q2.

As described above, according to the present embodiment, the following effects can be obtained.

(1) The etching stopper film 10 is formed after the sidewall spacers 8 formed on the side surfaces of the gate electrode 5 are selectively removed, so that the interlayer insulating film 11 and the etching stopper film 10 are anisotropically formed. To form a diffusion region contact hole 12 on the high-concentration impurity diffusion region 9 between the gate electrode 5 and the device isolation region (device isolation insulating film 3) of the semiconductor substrate 1 by performing the reactive etching.
Etching stopper film 1 remaining on side surface of gate electrode 5
Since the distance between the element region 0 and the element isolation region of the semiconductor substrate 1 is increased, the bottom area of the diffusion region contact hole 12 (the exposed area of the high-concentration impurity diffusion region 9) therebetween can be increased. As a result, the MOSFET (Q1, Q2)
Contact resistance in the high-concentration impurity diffusion region 9 can be reduced.

The bottom area (exposed area of the high concentration impurity diffusion region 9) of the diffusion region contact hole 12 between the etching stopper film 10 remaining on the side surface of the gate electrode 5 and the element isolation region of the semiconductor substrate 1 is determined. Since it can be increased, the size of the MOSFETs (Q1, Q2) can be reduced by an amount corresponding to the increase in the bottom area of the contact hole 12 for the diffusion region.

(2) By forming the etching stopper film 10 after selectively removing the side wall spacers 8 formed on the side surfaces of the gate electrode 5, the interlayer insulating film 11 and the etching stopper film 10 are anisotropically formed. When etching is performed to form a diffusion region contact hole 12 on the high concentration impurity diffusion region 9 between the gate electrodes 5, the etching stopper film 10 remaining on the side surface of one gate electrode 5 and the other gate electrode 5 Since the distance from the etching stopper film 10 remaining on the side surface of the diffusion region becomes large, the bottom area of the diffusion region contact hole 12 (the exposed area of the high-concentration impurity diffusion region 9) can be increased.
As a result, the contact resistance in the high-concentration impurity diffusion region 9 of the MOSFET (Q1, Q2) can be reduced.

The bottom area of the contact hole 12 for the diffusion region between the etching stopper film 10 remaining on the side surface of the one gate electrode 5 and the etching stopper film 10 remaining on the side surface of the other gate electrode (high-concentration impurity) Since the exposed area of the diffusion region 9 can be increased, the size of the MOSFET (Q1, Q2) can be reduced by an amount corresponding to the increase in the bottom area of the contact hole 12 for the diffusion region.

(3) By forming the etching stopper film 10 with a film thickness larger than the width (film thickness) of the side wall spacer 8 in the gate length direction, a low impurity diffusion Since exposure of the region 7 can be prevented, an increase in leakage current in the low impurity diffusion region 7 having a shallow junction can be suppressed.

(4) By making the amount of over-etching of the etching stopper film 10 equal to or less than the thickness of the cap insulating film 6, the contact hole 12 for the diffusion region
Even if the contact hole 12 climbs up, the contact hole 12 for the diffusion region can be formed without exposing the gate electrode 5.

In this embodiment, an example in which the etching stopper film 10 is formed of a silicon nitride film has been described. However, the etching stopper film 10 is limited to the silicon nitride film since it only needs to have selectivity with respect to a base. Not something.

(Embodiment 2) In this embodiment, an example in which a gate connection hole is formed on an element formation region of a semiconductor substrate will be described.

FIGS. 11 to 17 show Embodiment 2 of the present invention.
FIG. 9 is a cross-sectional view for illustrating the method for manufacturing the semiconductor integrated circuit device of FIG.

First, a groove 2 is selectively formed in an element isolation region on a main surface of a semiconductor substrate 1 made of single crystal silicon, and an insulating film 3 for element isolation made of a silicon oxide film is buried in the groove 2. The element formation regions on the main surface of the semiconductor substrate 1 are electrically separated.

Next, an n-channel MOSFET-Q3 having an LDD structure is formed in the element formation region of the semiconductor substrate 1 by using the same method as in the first embodiment, as shown in FIG. The MOSFET Q3 mainly includes a semiconductor substrate 1 used as a channel forming region, a gate insulating film 4 made of a silicon oxide film, a gate electrode 5 made of a polycrystalline silicon film, and a pair of low-concentration materials serving as a source region and a drain region. The structure has an impurity diffusion region 7 and a pair of high-concentration impurity diffusion regions 9 serving as a source region and a drain region. The gate electrode 5 has an upper surface covered with a cap insulating film 6 and a side surface covered with a sidewall spacer 8. The pair of low-concentration impurity diffusion regions 7 is
And a pair of high-concentration impurity diffusion regions 9 are formed in self-alignment with the sidewall spacers 8.

Next, the semiconductor substrate 1, the isolation insulating film 3, the gate insulating film 4, the gate electrode 5, the cap insulating film 6
As shown in FIG. 13, the sidewall spacers 8 are selectively removed without affecting the operation.

Next, an etching stopper film 10 is formed on the entire surface of the semiconductor substrate 1 so as to cover the cap insulating film 6.
Is formed by a CVD method. The etching stopper film 10
A film having a selectivity to silicon oxide such as the element isolation insulating film 3 and the cap insulating film 6 and silicon such as the semiconductor substrate 1 (a film that can be selectively etched), for example, a silicon nitride film. Also, the etching stopper film 10
Is formed with a thickness larger than the width (film thickness) of the sidewall spacer 8 in the gate length direction.

Next, as shown in FIG. 14, an interlayer insulating film 11 is formed on the etching stopper film 10. The interlayer insulating film 11 is formed of a film having selectivity to the etching stopper film 10 (a film that can be selectively etched), for example, a silicon oxide film.

Next, although not shown, a diffusion region contact hole reaching the high-concentration impurity diffusion region 9 from the surface of the interlayer insulating film 11 is formed by using the same method as in the first embodiment.

Next, a resist mask M2 for forming a gate contact hole on the gate electrode 5 is formed on the interlayer insulating film 11 by using a photolithography technique.

Next, using the resist mask M2 as an etching mask, as shown in FIG. 15, the interlayer insulating film 11 is subjected to anisotropic etching under the condition that a selectivity with respect to the etching stopper film 10 can be obtained. As shown in FIG. 16, the etching stopper film 10 is subjected to anisotropic etching under the condition that a selectivity can be obtained with respect to the cap insulating film 6, and thereafter, as shown in FIG. 17, the gate electrode 5 and the etching stopper film 10 are etched. The cap insulating film 6 is subjected to anisotropic etching under the condition that a selectivity can be obtained, thereby forming a gate contact hole 13 reaching the gate electrode 5 from the surface of the interlayer insulating film 11.

In this step, after the sidewall spacers 8 formed on the side surfaces of the gate electrode 5 are selectively removed, the etching stopper film 10 having selectivity with respect to the cap insulating film 6 is formed. When the gate contact hole 13 protrudes from the gate electrode 5, the allowable over-etching amount when etching the cap insulating film 6 is equivalent to the thickness of the gate electrode 5 plus the cap insulating film 6. Becomes For example, when the thickness of the gate electrode 5 is set to 150 [nm] and the thickness of the cap insulating film 6 is set to 150 [nm], the allowable amount of over-etching that can be tolerated in the related art is 150 [ On the other hand, in this embodiment, since the side surface of the gate electrode 5 is covered with the etching stopper film 10 having selectivity with respect to the cap insulating film 6, the allowable over-etching amount is Is about 300 [nm], which is equivalent to the sum of the thickness of the cap insulating film 6 and the thickness of the cap insulating film 6.

Next, the resist mask M2 is removed, and then a conductive material such as metal is filled in the connection holes for the diffusion region and the connection holes 13 for the gate to form a conductive plug 14, and then the interlayer insulating film is formed. By forming the wiring 15 on the wiring 11, the wiring 15 in the upper layer is electrically connected to the MOSFET Q3 as shown in FIG.

As described above, according to the present embodiment, the following effects can be obtained.

After selectively removing the sidewall spacers 8 formed on the side surfaces of the gate electrode 5, the etching stopper film 1 having selectivity with respect to the cap insulating film 6 is formed.
When the gate contact hole 13 protrudes from the gate electrode 5 by forming 0, the allowable over-etching amount when etching the cap insulating film 6 is obtained by adding the cap insulating film 6 to the thickness of the gate electrode 5. Therefore, the gate electrode 5 and the impurity diffusion region (7, 7) of the MOSFET Q3 are generated through the conductive material (conductive plug 14 or a part of the wiring) filled in the gate contact hole 13. 9) It is possible to increase the margin for short-circuiting with 9).

Further, a margin for a short circuit between the gate electrode 5 of the MOSFET Q3 and the impurity diffusion region (7, 9) can be increased, so that the gate contact hole 13 can be easily formed on the element formation region of the semiconductor substrate 1. The size of the MOSFET Q3 can be reduced.

In this embodiment, an example in which the etching stopper film 10 is formed of a silicon nitride film has been described. However, since the etching stopper film 10 only needs to have at least selectivity with respect to at least the cap insulating film and the gate electrode. The invention is not limited to the silicon nitride film.

In the first and second embodiments, the LDD in which the low-concentration impurity diffusion region is formed by ion implantation is used.
Although an example using a MOSFET having a structure has been described, an LDD structure in which a side wall spacer into which an impurity is introduced is formed on the side surface of a gate electrode, and the impurity is diffused from the side wall spacer to form a low concentration impurity diffusion region. It may be a MOSFET.

In the first and second embodiments, n
Although an example using a channel conductivity type MOSFET has been described, a p-channel conductivity type MOSFET may be used.

In Embodiments 1 and 2, M
Although an example using an OSFET has been described, the present invention is not limited to this, and an MISFET may be used.
The gate insulating film of the MISFET is, for example, a thermal oxide film formed of N.
Formed by Si-O-N film formed by oxidizing treatment in a ₂ O gas atmosphere. The MISFET using the gate insulating film made of the Si-ON film has, for example, improved hot carrier resistance.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

[0079]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

It is possible to reduce the contact resistance in the impurity diffusion region of the MISFET.

Further, it is possible to increase a margin for a short circuit between the gate electrode of the MISFET and the impurity diffusion region.

Further, the MISFET can be miniaturized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a method of manufacturing the semiconductor integrated circuit device.

FIG. 3 is a cross-sectional view for explaining a method for manufacturing the semiconductor integrated circuit device.

FIG. 4 is a cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 5 is a cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 7 is a cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 8 is a cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 9 is a cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 10 is a cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 11 is a sectional view for illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention.

FIG. 12 is a sectional view for illustrating the method for manufacturing the semiconductor integrated circuit device.

FIG. 13 is a sectional view for illustrating the method for manufacturing the semiconductor integrated circuit device.

FIG. 14 is a cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 15 is a cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 16 is a sectional view for illustrating the method for manufacturing the semiconductor integrated circuit device.

FIG. 17 is a cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 18 is a cross-sectional view for explaining a conventional technique.

FIG. 19 is a cross-sectional view for explaining a conventional technique.

FIG. 20 is a cross-sectional view for explaining a conventional technique.

FIG. 21 is a cross-sectional view for explaining a conventional technique.

FIG. 22 is a cross-sectional view for explaining a conventional technique.

FIG. 23 is a cross-sectional view for explaining a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Groove, 3 ... Element isolation insulating film, 4 ...
Gate insulating film, 5 gate electrode, 6 cap insulating film,
7 low concentration impurity diffusion region, 8 side wall spacer, 9 high concentration impurity diffusion region, 10 etching stopper film, 11 interlayer insulating film, 12 contact hole for diffusion region, 13 contact hole for gate, 14 ... Conductive plug, 15 ... Wiring, M1, M2 ... Resist mask, Q1,
Q2, Q3 ... MOSFET.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masaya Iida 3-16-6 Shinmachi, Ome-shi, Tokyo F-term in the Hitachi, Ltd. Device Development Center 5F040 DA10 DB03 DC01 EC07 EF02 EH08 EK05 FA07 FB02 FC11 FC21 5F048 AA01 AC03 BA01 BB06 BC06 BF15 BF16 BG14 DA19 DA27

Claims (5)

[Claims] An MISFE is formed in an element formation region of a semiconductor substrate.
T, the MISFET has a gate electrode whose upper surface is covered with a cap insulating film and whose side surfaces are covered with sidewall spacers, and a low-concentration impurity diffusion region formed in self-alignment with the gate electrode. A method of manufacturing a semiconductor integrated circuit device having a configuration having a high-concentration impurity diffusion region formed in a self-alignment manner with respect to the sidewall spacer, wherein the sidewall spacer is selectively removed, Forming an etching stopper film having selectivity with respect to a base on the semiconductor substrate so as to cover the cap insulating film, and thereafter, forming an interlayer insulating film having selectivity with respect to the etching stopper film on the etching stopper film; Performing anisotropic etching on the interlayer insulating film under a condition that a selectivity with respect to the etching stopper film can be obtained;
Forming a contact hole from the interlayer insulating film to the high-concentration impurity diffusion region by performing anisotropic etching on the etching stopper film under a condition that a selectivity with respect to the base can be obtained. Of manufacturing a semiconductor integrated circuit device. 2. The method according to claim 1, wherein the first MIS is formed in an element forming region of the semiconductor substrate.
FET and a second MISFET.
Each of the SFET and the second MISFET has a gate electrode whose top surface is covered with a cap insulating film and whose side surfaces are covered with a sidewall spacer, and a pair of low-concentration impurity diffusion regions formed in self-alignment with the gate electrode. And a pair of high-concentration impurity diffusion regions formed in a self-aligned manner with respect to the side wall spacers. The gate electrodes of the first MISFET and the second MISFET are arranged in parallel, One high concentration impurity diffusion region of the first MISFET is provided between the gate electrodes.
A method of manufacturing a semiconductor integrated circuit device shared with one of the high-concentration impurity diffusion regions of the second MISFET, wherein the sidewall spacer is selectively removed, and then the cap insulating film is covered. Forming an etching stopper film having selectivity with respect to a base on the semiconductor substrate, and thereafter forming an interlayer insulating film having selectivity with respect to the etching stopper film on the etching stopper film; Perform anisotropic etching under the condition that the selectivity can be obtained with respect to the etching stopper film.
Forming a contact hole from the interlayer insulating film to the high-concentration impurity diffusion region by performing anisotropic etching on the etching stopper film under a condition that a selectivity with respect to the base can be obtained. Of manufacturing a semiconductor integrated circuit device. 3. An MISFE in an element formation region of a semiconductor substrate.
T, the MISFET has a gate electrode whose upper surface is covered with a cap insulating film and whose side surfaces are covered with sidewall spacers, and a low-concentration impurity diffusion region formed in self-alignment with the gate electrode. A method of manufacturing a semiconductor integrated circuit device having a configuration having a high-concentration impurity diffusion region formed in a self-alignment manner with respect to the sidewall spacer, wherein the sidewall spacer is selectively removed, Forming an etching stopper film having selectivity with respect to a base on the semiconductor substrate so as to cover the cap insulating film, and thereafter, forming an interlayer insulating film having selectivity with respect to the etching stopper film on the etching stopper film; Performing anisotropic etching on the interlayer insulating film under a condition that a selectivity with respect to the etching stopper film can be obtained;
The etching stopper film is subjected to anisotropic etching under a condition that a selection ratio can be obtained with respect to the base, and then the cap insulating film has an anisotropy under the condition that a selection ratio can be obtained with respect to the gate electrode and the etching stopper film. Forming a contact hole reaching the gate electrode from the interlayer insulating film by etching. 4. The semiconductor integrated circuit device according to claim 1, wherein the etching stopper film is formed to have a thickness larger than a width of the sidewall spacer in a gate length direction. Method. 5. The semiconductor device according to claim 1, wherein the cap insulating film is formed of a silicon oxide film, and each of the sidewall spacer and the etching stopper film is formed of a silicon nitride film. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 1.