JP2596341B2 - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a MOS transistor, and more particularly to a gate, a source, and a semiconductor integrated circuit device.
The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, which reduce the number of manufacturing steps for each drain electrode.

[0002]

2. Description of the Related Art One example of a conventional method for manufacturing a MOS transistor formed in a semiconductor integrated circuit device is a P channel M transistor.
Description will be made using an OS transistor as an example. 7 to 9
3 is a cross-sectional view showing the manufacturing method in the order of steps. First, as shown in FIG. 7A, an N well 2 is formed in a P-type silicon substrate 21.
2. A P-well 23 is formed, and an element isolation oxide film 24 is formed on the boundary between the P-well 23 and an element region for forming a P-channel MOS transistor. Then, by implanting impurities for adjusting V _T (boron) in the main surface of the N-well 22, and a gate oxide film 25 on the main surface, further, the thickness of about 3000Å polysilicon 26 thereon To grow. Next, as shown in FIG. 7B, the polysilicon 26 is patterned by using a photoresist (not shown) as a mask to form a gate electrode 27. Subsequently, as shown in FIG. 7C, a photoresist 28 is formed, and a region where a P-channel MOS transistor is to be formed is opened by using a photolithography technique.
Is used as a mask, low-concentration boron is ion-implanted into the main surface of the N-well 22 using an ion implantation technique.

Next, as shown in FIG. 8A, a silicon oxide film 29 is grown on the entire surface as shown in FIG. Then, the silicon oxide film 29 is anisotropically etched to obtain FIG.
As shown in (b), a sidewall 30 of a silicon oxide film is formed on the side surface of the gate electrode 27. Then, a thin silicon oxide film 31 is formed on the entire surface, a photoresist 32 is formed, and a region where a P-channel MOS transistor is to be formed is opened by using a photolithography technique. Then, high-concentration boron is ion-implanted into the main surface of the N-well 22 using an ion implantation technique. Then, heat treatment is performed to activate the ion-implanted boron ions as shown in FIG. 8C, thereby forming a low-concentration source / drain region 33 and a high-concentration source / drain region 34.

Next, as shown in FIG. 9A, a 6000 ° interlayer insulating film 35 is formed on the entire surface as shown in FIG. Then, the interlayer insulating film 35 is selectively etched by using a photoresist (not shown) as a mask, thereby obtaining a structure shown in FIG.
A contact hole 36 is opened as shown in FIG. Then, after growing a metal film such as tungsten on the entire surface including the contact holes 36, the metal film is anisotropically etched so that only the metal film 37 is removed as shown in FIG. To form a contact. Thereafter, a wiring not shown is formed, and a high-concentration source / drain is electrically connected through a contact, whereby a P-channel MOS transistor is manufactured.

[0005]

In this conventional semiconductor integrated circuit device, a photolithography technique is required in each of a step of forming a gate electrode and a step of forming each electrode of a source and a drain. And a matching step is required. In particular, in the photomask alignment process, extremely high precision is required in accordance with recent miniaturization of MOS transistors, which makes production difficult. When forming the source and drain electrodes, the interlayer insulating film is selectively etched to form a contact hole, and the contact conductive material is buried. The aspect ratio also becomes large, making it difficult to embed the conductive material in a suitable manner, and also causes a problem that the reliability of the contact is reduced. To cope with this, measures to reduce the aspect ratio by reducing the thickness of the interlayer insulating film have been considered, but the wiring capacitance between the upper and lower wirings sandwiching the interlayer insulating film increases, making it difficult to increase the operation speed. Problem arises. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit device which simplifies the manufacture of source / drain electrodes of MOS transistors and their contacts, and enables miniaturization of each electrode and contacts, and a method of manufacturing the same.

[0006]

According to the present invention, there is provided a semiconductor integrated circuit device comprising a gate oxide film formed in a required region on a main surface of a semiconductor layer of a first conductivity type, and a semiconductor layer sandwiching the gate oxide film. A source / drain region of a second conductivity type formed on the main surface; and a gate electrode and a source / drain electrode formed of the same polycrystalline silicon on the gate oxide film and the source / drain region, respectively. The upper surface of each electrode is exposed from an interlayer insulating film formed on the entire surface .
The source / drain region is formed as an LDD structure having a low-concentration source / drain region partially extending to a position directly below the gate electrode under the gate oxide film.
You.

Further, according to the manufacturing method of the present invention, a step of selectively forming a gate insulating film wider than a gate electrode formation region on a main surface of a semiconductor layer of the first conductivity type, and a step of forming a polycrystalline silicon film on the entire surface Forming, introducing a second conductivity type impurity into the formed polycrystalline silicon, and selectively etching the polycrystalline silicon to form a gate electrode and source / drain electrodes; Semiconductor between these electrodes
Ion implantation of impurity of the second conductivity type into body layer at low concentration
To form LDD source / drain regions
Forming a source / drain region by diffusing the impurities of the second conductivity type from the formed source / drain electrodes into the semiconductor layer; and forming an interlayer insulating film over the entire surface so as to cover the electrodes. And etching the interlayer insulating film to expose upper surfaces of the gate electrode and the source / drain electrodes on the interlayer insulating film.

[0008]

Next, the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention, (a) is a plan view,
(B) is a sectional view. Here, an example in which the present invention is applied to a P-channel MOS transistor is shown. In FIG. 1, an element region is divided by an element isolation oxide film 4 formed on a main surface of a P-type silicon substrate 1, and an N well 2
And a P well 3 are formed. And here N
A gate oxide film 7 is formed substantially at the center of the main surface of well 2, and P-type high-concentration source / drain regions 14 and low-concentration source / drain regions 13 are formed on both sides of gate oxide film 7. Thus, a source / drain region having an LDD structure is formed. Further, an interlayer insulating film 15 is formed on the entire surface, and the gate electrode 10 and the source / drain electrodes 11 are formed of the same polycrystalline silicon between the interlayer insulating films. Gate electrode 10
Are formed on the gate oxide film 7, and the source / drain electrodes 11 are formed in contact with the high concentration source / drain regions 14, respectively.

FIGS. 2 to 4 are sectional views showing a method of manufacturing the MOS transistor in the order of steps. First, in FIG. 2, as shown in FIG.
Then, an N well 2 and a P well 3 are formed respectively, and an element isolation oxide film 4 is formed on the main surface of the silicon substrate 1 at the boundary between the wells by the LOCOS method. Then, after growing a silicon nitride film 5 over the entire surface by 500 °, a region of the photoresist 6 where a P-type channel MOS transistor is to be formed is opened wider than a predetermined gate electrode by photolithography, and this is used as a mask. implanting impurities (boron) for adjusting V _T in the element region Te. Next, as shown in FIG. 2B, the silicon nitride film 5 is selectively removed by etching using the photoresist 6 as a mask, and then the photoresist 6 is removed. Then, using the silicon nitride film 5 as a mask, the main surface of the N well 2 is selectively oxidized,
A gate oxide film 7 is formed in a substantially central region of the well 2. Thereafter, as shown in FIG. 2C, the entire surface of the silicon nitride film 5 is removed.

Next, in FIG. 3, as shown in FIG. 3A, a polycrystalline silicon 8 is grown to a thickness of 1 μm on the entire surface. Then, as shown in FIG. 3B, a photoresist 9 is formed, the photoresist 9 in the region where the P-channel MOS transistor is to be formed is opened by using the photolithography technique, and the photoresist 9 is used as a mask. High-concentration boron is ion-implanted into the N well 2 using an ion implantation technique. Next, the photoresist 9 is removed, and as shown in FIG. 3C, a photoresist 9A is formed in each of the gate, source, and drain electrode regions of the MOS transistor to be manufactured. By patterning the silicon 8, the gate electrode 10,
Source / drain electrodes 11 are formed.

Next, in FIG. 4, as shown in FIG. 4 (a), a photoresist 12 is formed, and a region for forming a P-channel MOS transistor is opened by using photolithography technology. Resist 12
Is ion-implanted into the N-well 2 by ion implantation using the mask as a mask. Then, thermal diffusion is performed to activate the low-concentration boron ions implanted as shown in FIG.
A drain region (LDD region) 13 is formed. At the same time, impurities are diffused from the polycrystalline silicon as the source / drain electrodes 11 to the main surface of the N well 2,
A high concentration source / drain region 14 is formed. Thereafter, as shown in FIG. 4C, a CVD oxide film is formed on the entire surface, and a coating film such as silica is further applied thereon to form a flattened interlayer insulating film 15 to a thickness of 1.5 μm. . Then, the gate electrode 10 and the source / drain electrodes 1
By etching back the interlayer insulating film 15 until the upper surface of the MOS transistor 1 is exposed, the P-channel MOS transistor shown in FIG. 1 is completed.

Therefore, in the semiconductor integrated circuit device having the MOS transistor of this configuration, the gate electrode 10 and the source / drain electrodes 11 can be manufactured by one photolithography technique using one photomask. For this reason, only one photomask alignment process is required, and the manufacturing process can be simplified. In particular, by reducing the alignment process, the positional accuracy between each electrode is increased, and the miniaturization of each electrode is achieved. High integration can be realized. Also, in forming a contact for connecting each electrode to the upper wiring, a step of opening a contact hole in the interlayer insulating film and a step of embedding a conductive material in the contact hole are not required, and the thickness of the interlayer insulating film is reduced. A highly reliable contact can be formed without being affected. Therefore, even if the MOS transistor is miniaturized, the interlayer insulating film can be formed to a required thickness, and an increase in the wiring capacitance between the upper and lower wirings can be prevented, and a MOS transistor capable of high-speed operation can be configured. Becomes

FIG. 5 is a sectional view of a second embodiment of the present invention. In the figure, parts equivalent to those of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. The second embodiment is characterized in that the gate electrode 10A and each of the source / drain electrodes 11A have a laminated structure of polycrystalline silicon 16 and a refractory metal silicide, here tungsten silicide 18.

A method of manufacturing the semiconductor integrated circuit device will be described with reference to FIGS. After performing the step of FIG. 2 of the first embodiment, as shown in FIG. 6A, a polycrystalline silicon 16 is grown to a thickness of 2000 ° over the entire surface. Then, as shown in FIG. 6B, a photoresist 17 is formed, a region of the photoresist 17 where a P-channel MOS transistor is to be formed is opened, and the photoresist 17 is used as a mask by ion implantation. High concentration boron is ion-implanted into the N well 2. Then, FIG.
As shown in FIG. 3C, a tungsten silicide 18 is formed on the entire surface by sputtering to a thickness of 8000.degree.
6 and a tungsten silicide 18 are formed. Thereafter, similarly to the first embodiment, the laminated structure of the polycrystalline silicon 16 and the tungsten silicide 18 is patterned, and the gate electrode 10A and the source / drain electrodes 1 are formed.
Form 1A. Further, a semiconductor integrated circuit device shown in FIG. 5 is formed by forming an interlayer insulating film and etching it back.

In the semiconductor integrated circuit device of the second embodiment, the gate electrode 10A and the source / drain electrodes 1
Polycrystalline silicon 16 in which the lower portion of 1A is doped with impurities
Particularly, in the source / drain electrode 11A, the impurity is directly diffused from the polycrystalline silicon 16 to the main surface of the N well 2 to form the high-concentration source / drain region 14. Therefore, as in the first embodiment, In addition, the source / drain electrodes are formed of thick polycrystalline silicon, and the diffusion distance can be reduced as compared with the method of diffusing impurities from the upper surface thereof, so that the formation of the high-concentration source / drain regions 14 is facilitated. Since the upper portions of the electrodes 10A and 11A are formed of a metal material, there is an advantage that the resistance can be reduced and high-speed operation can be performed.

Although each of the above embodiments is an example in which the present invention is applied to a P-channel MOS transistor, it goes without saying that the present invention can be similarly applied to an N-channel MOS transistor.

[0017]

As described above, in the semiconductor integrated circuit device of the present invention, the gate electrode and the source / drain electrodes are formed of the same polycrystalline silicon. Can be formed by selective etching, and there is no need to manufacture the gate electrode and the source / drain electrodes in separate photolithography steps. For this reason, a photomask for forming each electrode can be reduced, and alignment is not required, and a MOS transistor having an electrode with high positional accuracy can be manufactured while simplifying the manufacturing, which is suitable for high integration. A semiconductor integrated circuit device can be obtained. In addition, source / drain of LDD structure
The low-concentration region of the gate region is the gate under the gate oxide film.
Since it is formed extending to the position directly below the electrode,
To enhance the effect of electric field relaxation in the drain and drain regions.
It becomes possible.

Further, according to the manufacturing method of the present invention, after impurities are introduced into the same polycrystalline silicon, a gate electrode and source / drain electrodes are formed with the polycrystalline silicon, and a semiconductor layer between these electrodes is formed. Low impurity concentration
Since the source / drain regions are formed by injecting ON and further introducing impurities from the source / drain electrodes into the semiconductor layer, the gate electrode and the source / drain electrodes can be formed in one photolithography process. At the same time, the source and drain can be formed in a self-aligned manner, and a highly integrated MOS transistor can be easily manufactured. Further, since an interlayer insulating film is formed and the upper surface of each electrode is exposed from the interlayer insulating film, it is not necessary to form a contact hole for each electrode in the interlayer insulating film. A contact structure can be formed,
In addition to promoting high integration, there is an effect that high-speed operation can be realized by reducing wiring capacitance. In addition, Io
Low concentration of source / drain region of LDD structure
This low-concentration region is
Formed under the oxide film to the position directly below the gate electrode
Of source / drain regions with high electric field relaxation effect
Becomes possible.

[Brief description of the drawings]

FIG. 1 is a plan view and a sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a first sectional view showing the manufacturing method of the first embodiment in the order of steps;

FIG. 3 is a second sectional view illustrating the manufacturing method of the first embodiment in the order of steps;

FIG. 4 is a third sectional view showing the manufacturing method of the first embodiment in the order of steps;

FIG. 5 is a sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view showing part of the manufacturing method of the second embodiment in the order of steps.

FIG. 7 is a first sectional view illustrating an example of a conventional manufacturing method in the order of steps;

FIG. 8 is a second sectional view showing an example of the conventional manufacturing method in the order of steps.

FIG. 9 is a third sectional view showing an example of the conventional manufacturing method in the order of steps;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 N well 7 Gate oxide film 10 Gate electrode 11 Source / drain electrode 13 Low concentration source / drain region 14 High concentration source / drain region 15 Interlayer insulating film

Claims (2)

(57) [Claims] 1. A gate oxide film formed in a required region on a main surface of a semiconductor layer of a first conductivity type, and a source and a source material of a second conductivity type formed on a main surface of the semiconductor layer sandwiching the gate oxide film.
A drain region, and a gate electrode and a source / drain electrode formed of the same polycrystalline silicon on the gate oxide film and the source / drain region, respectively. Each electrode is formed of an interlayer insulating film formed on the entire surface. The top surface is exposed, and the source / drain regions are partially exposed to gate acid.
Low concentration extending to the position just below the gate electrode below the passivation film
LDD structure with multiple source / drain regions
A semiconductor integrated circuit device characterized by being formed . 2. A process for selectively forming a wide gate insulating film than the gate electrode formation region on a main surface of a first conductivity type semiconductor layer, and forming a polycrystalline silicon film on the entire surface,
Introducing a second conductivity type impurity into the polycrystalline silicon, and forming the electrodes of the gate electrode and the source-drain by selectively etching the polycrystalline silicon, the semiconductor layer between the electrodes On the other hand, impurities of the second conductivity type
Implanting a substance at a low concentration, diffusing the second conductivity type impurity from each of the source / drain electrodes into the semiconductor layer to form a high concentration source / drain region; Forming an interlayer insulating film over the entire surface so as to cover the gate electrode, and exposing the upper surface of each of the gate electrode and source / drain electrodes on the interlayer insulating film by etching the interlayer insulating film. A method for manufacturing a semiconductor integrated circuit device.