JPH05145023A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a fused-junction BiMOS transistor wherein the level of integration is improved, by forming a base electrode leading-out layer which serves as a drain, so as to extend from the inside of a well region to the inside of a base layer. CONSTITUTION:An N<-> type diffusion layer 19 formed to be adjacent to a low concentration diffusion layer 10 for LDD at a position on the side opposite to a source region 8 in reference to a gate electrode 12 of an NMOST 2 is formed so as to extend from the inside of a P well region 4 to the inside of an N well region 5, and serves as the drain region of the NMOST 2 and a base leading-out layer of a PNPTr 3. An electrode wiring layer 18e connected with the drain and the base electrode leading-out layer 19 via a contact hole formed in an interlayer insulating film 17 is formed. The drain region of the NMOST 2 and the base electrode leading-out layer of the PNPTr 3 are formed of the same diffusion layer 19. Hence a fused-junction BiMOS transistor is microminiaturized, and the high density integration and the high performance of a semiconductor device can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a fused bipolar MOS transistor.

[0002]

2. Description of the Related Art Recently, in order to meet the demand for improving the performance of industrial equipment such as computers, there has been an increasing trend to increase the speed of LSIs by using an embedded technology called bipolar CMOS (hereinafter BiCMOS). Figure 9 shows BiCMO
In the S device, especially NMOS transistor (hereinafter NM
FIG. 10 is an equivalent circuit diagram of a fused BiNMOS transistor in which a drain of an OST) and a base of a PNP bipolar transistor (hereinafter, referred to as PNPTr) are combined, and FIG. 10 shows a conventional structure of the fused BiNMOS transistor. It is sectional drawing shown.

In FIG. 10, 1 is a semiconductor substrate made of P-type silicon single crystal or the like (hereinafter referred to as a silicon substrate), 2 is an NMOST formed on the silicon substrate 1, 3
Is also a PNPTr formed in the silicon substrate 1, 4 is a P well embedded in the silicon substrate 1, and 5 is an N well similarly embedded in the silicon substrate 1 and serves as a base layer of PNPTr3. 6 is a field insulating film formed on the silicon substrate 1 for separating the elements, 7 is a channel stopper formed under the field insulating film 6 in the P well 4 region in which the NMOST 2 is formed, for separating the elements, 8 Is P
The source region of the NMOST2 formed in the well 4 region,
Reference numeral 9 is a drain region of the NMOST2, 10 is a low-concentration diffusion layer for LDD adjacent to the source / drain regions 8 and 9, 11 is a gate insulating film of the NMOST2, 12 is a gate electrode on the gate insulating film 11, and 13 is Gate electrode 12
Is a sidewall insulating film formed on the side surface of the. 14 is a base electrode take-out layer of PNPTr3 formed in the N well 5,
Reference numeral 15 is an emitter layer of PNPTr3 also formed in the N well 5, and 16 is PNPTr3 formed in the P well 2.
Is a collector electrode take-out layer of.

Reference numeral 17 denotes an interlayer insulating film formed on the silicon substrate 1 so as to cover the gate electrode 12 and the field insulating film 6, and 18 denotes an electrode wiring layer formed on the interlayer insulating film 17, which is an interlayer insulating film 17 Through the cottage hall of 1
Reference numeral 8a is connected to the drain region 9 of the NMOST2 and the base electrode extraction layer 14 of the PNPTr3 to connect them to each other.
8b, 18c, and 18d are NMOST2, respectively.
Is connected to the source region 8, the PNPTr3 emitter layer 15, and the collector electrode extraction layer 16. In this case, the channel stopper 7 and the emitter layer 15
And the collector electrode extraction layer 16 is a P ⁺ type, the LDD low-concentration diffusion layer 10 is an N ⁻ type, the source / drain region 8,
9 and the base electrode take-out layer 14 are formed in N ⁺ type, respectively.

[0005]

DISCLOSURE OF THE INVENTION Conventional fusion type BiNM
Since the OS transistor is configured as described above, the drain region 9 of the NMOST2 and the base electrode take-out layer 14 of the PNPTr3 are connected by the electrode wiring layer 18a, and these two N ⁺ type diffusion layers 9 and 14 are connected to the field. It is formed so as to be separated with the insulating film 6 interposed therebetween. For this reason, the device area becomes large, which hinders high-density integration.

The present invention has been made to solve the above-mentioned problems, and is a fusion type BiM having an improved degree of integration.
The purpose is to obtain an OS transistor.

[0007]

In a semiconductor device according to the present invention, a first conductivity type well region provided on a semiconductor substrate, a second conductivity type base layer, and a gate formed in the well region. An electrode, a second conductivity type source region, a first conductivity type collector electrode extraction layer, a first conductivity type emitter layer formed in the base layer, and a drain region and a base electrode extraction layer which are the same diffusion layer The second formed by
A drain / base electrode lead-out layer of a conductive type, and the drain / base electrode lead-out layer is formed so as to extend from inside the well region to inside the base layer.

[0008]

In the semiconductor device according to the present invention, the drain region in the well region and the base electrode in the base layer, which are conventionally formed separately with the field insulating film interposed therebetween, are the same in the well region and in the base layer. It is formed of a diffusion layer.
Therefore, the element area is reduced and the integration is improved.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Note that the description overlapping with the description of the conventional technique will be appropriately omitted. FIG. 1A shows a fused BiNMOS in a BiCMOS device according to an embodiment of the present invention.
2 is a plan view showing the structure of a transistor, and FIG.
FIG. 2 is a sectional view taken along line I-I of FIG. In the figure, 1-8, 10-13, 15-18, 18b, 18
c and 18d are the same as conventional ones, 19 is NM
An N ⁺ -type diffusion layer formed adjacent to the LDD low-concentration diffusion layer 10 at a position opposite to the source region 8 with respect to the gate electrode 12 of the OST 2 and extending from the P well region 4 to the N well region 5. It is formed and also serves as the drain region of the NMOST2 and the base electrode take-out layer of the PNPTr3. Reference numeral 18 e denotes a drain / base electrode take-out layer 1 through a contact hole provided in the interlayer insulating film 17.
Electrode wiring layer connected to 9, 20b, 20c, 20d,
Reference numerals 20e and 20f denote an electrode wiring layer 18, a source region 8, an emitter layer 15, and a collector electrode extraction layer 1 respectively.
6, a contact portion with the drain / base electrode take-out layer 19 and the gate electrode 12.

The BiNMOS transistor configured as described above is manufactured as follows. This will be described with reference to FIGS. First, a photoresist film 21 is formed on the entire surface of the P-type silicon substrate 1 and patterned by the photolithography technique. Using the resist pattern 21 as a mask, P-type boron ions, for example, are implanted from above the silicon substrate 1. Thereby, the P-type impurity region 4a
Is formed. Note that this implantation may use a high-energy ion implantation method in order to accurately control the concentration of impurities (FIG. 2). Next, after removing the photoresist film 21, a photoresist film 22 is formed again on the entire surface of the silicon substrate 1 and patterned by the photolithography technique. The resist pattern 22 is formed so as to serve as an inversion mask with respect to the resist pattern 21 used in the P-type ion implantation in the previous step. Using the resist pattern 22 as a mask, N-type phosphorus ions, for example, are implanted from above the silicon substrate 1. As a result, the N type impurity region 5a is formed. This ion implantation may also use the high energy ion implantation method (FIG. 3).

After removing the photoresist film 22, the silicon substrate 1 is heat-treated to activate the P-type and N-type impurity regions 4a and 5a to form the P-well 4 and the N-well 5. The N well 5 serves as a base layer of the PNPTr 3 and, in a BiCMOS device, a PMOS.
An N well of T (not shown) can be formed at the same time. Next, a thin silicon oxide film 23 is formed on the entire surface of the silicon substrate 1.
Then, a silicon nitride film 24 is sequentially formed on it. Subsequently, a photoresist film (not shown) is formed on the entire surface of the silicon nitride film 24 and is patterned by the photolithography technique. Using this resist pattern as a mask, the underlying silicon nitride film 24 is removed by etching. Then, after removing the photoresist film, a photoresist film (not shown) is formed on the entire surface of the silicon substrate 1 again and patterned. Using this resist pattern as a mask, boron (B) ions of P type, for example, are implanted into the silicon substrate 1 to form P type impurity regions 7a, and then the photoresist film is removed (FIG. 4).

Next, the silicon substrate 1 is oxidized to form the field insulating film 6 on the portion not covered with the silicon nitride film 24. At this time, the boron ions in the P-type impurity region 7a that have been implanted are diffused,
The stopper 7 is formed. Then, the silicon nitride film 24
Then, the silicon oxide film 23 is sequentially etched and removed (FIG. 5). Next, a silicon oxide film to be the gate insulating film 11 and the gate electrode 12 are formed on the entire surface of the silicon substrate 1.
A doped polysilicon film to be the above is sequentially deposited. Then, a photoresist film (not shown) is formed on the entire surface of the doped polysilicon film and patterned by the photolithography technique. After using this resist pattern as a mask to remove the underlying doped polysilicon film, the photoresist film is removed. As a result, a part of the doped polysilicon film remains in the P well 4 region to form the gate electrode 12. Next, a photoresist film (not shown) is formed on the entire surface of the silicon substrate 1 and patterned by photolithography so that only the NMOST2 active region is opened. Using the resist pattern and the gate electrode 12 as a mask, for example, phosphorus ions of N type are implanted into the NMOST2 formation region from above the silicon substrate 1 to form a low concentration N type impurity region 10a. After that, the photoresist film is removed (FIG. 6).

Next, a silicon oxide film is deposited on the entire surface of the silicon substrate 1, and then a sidewall insulating film 13 made of a silicon oxide film is formed on the side surface of the gate electrode 12 by the entire surface etchback method by dry etching. Next, a photoresist film (not shown) is formed on the entire surface of the silicon substrate 1,
It is patterned by the photolithography technique so as to partially open from the NMOST2 active region to the N well 5. Using this resist pattern, the gate electrode 12 and the side wall insulating film 13 as a mask, for example, N-type phosphorus ions are implanted from above the silicon substrate 1 to form high-concentration N-type impurity regions 8a and 19a. Then, heat treatment is applied to the silicon substrate 1, whereby N-type impurity regions 10a, 8a, 19 are formed.
The phosphorus ions of a are diffused to form the LDD low-concentration diffusion layer 10 and the source region 8 and the drain / base electrode extraction layer 19 adjacent thereto on the silicon substrate 1 on both sides of the gate electrode 12. At this time, the drain / base electrode extraction layer 19 is formed so as to extend from the inside of the NMOST2 active region in the P well 4 to the inside of the N well 5 serving as the base layer of the adjacent PNPTr3 (FIG. 7).

Next, a photoresist film 25 is formed on the entire surface of the silicon substrate 1 and patterned by the photolithography technique. Using this resist pattern 25 as a mask, for example, P-type boron ions are implanted from above the silicon substrate 1 to form high-concentration P-type impurity regions 15a and 16a (FIG. 8). Next, after removing the photoresist film 25, the silicon substrate 1 is subjected to a heat treatment to diffuse the boron ions in the P-type impurity regions 15a and 16a which have been implanted, so that the emitter layer 15 and the P-type impurity regions 15a and 16a in the N well 5 are diffused. A collector electrode extraction layer 16 is formed in the well 4. In the BiCMOS device, the source / drain regions of the PMOST (not shown) or the base electrode take-out layer of the NPNTr (not shown) can be formed at the same time.
Next, an interlayer insulating film 17 is formed on the entire surface of the silicon substrate 1, and a photoresist film (not shown) is formed on the entire surface thereof. This is patterned by a photolithography technique, and the underlying interlayer insulating film 17 is removed by etching using this resist pattern as a mask. As a result, contact holes are formed by exposing a part of the main surfaces of the source region 8, the drain / base electrode extraction layer 19, the emitter layer 15, and the collector electrode extraction layer 16. After that, the electrode wiring layer 18 made of aluminum is formed on the entire surface of the interlayer insulating film 17 so as to fill the contact hole.
Deposit. Thereafter, by patterning the electrode wiring layer 18, electrode wiring layers 18b connected to the source region 8, the drain / base electrode extraction layer 19, the emitter layer 15, and the collector electrode extraction layer 16 through the contact holes, 18e, 18c, 18d
Are formed (see FIG. 1B). Further, after this, predetermined processing is performed to complete the fused BiNMOS transistor.

A fused BiNMO having the above-described structure
The S transistor is connected to the drain region of the NMOST2 and PN
The base electrode extraction layer of PTr3 is formed of the same diffusion layer 19. Therefore, as in the conventional case, the drain region 9 and the base electrode take-out layer 14 are sandwiched with the field insulating film 6 interposed therebetween.
In contrast to the case where the two are separately formed, the field insulating film 6 between them is eliminated, and the two diffusion layers 9 and 14 are integrated into one, so that the element area is significantly reduced.

In the above embodiment, the base layer of the PNPTr3 is the N well 5 similar to the PMOST, and the emitter layer is a parasitic vertical PNP transistor which can be formed simultaneously with the source / drain regions of the PMOST. A normal PNP bipolar transistor in which an N type base layer is formed in a P substrate P well and a P type emitter layer is further formed therein may be used.

A BiPMOS in which the drain of the PMOST and the base of the NPN bipolar transistor are fused together
It can be a transistor.

[0018]

As described above, according to the present invention, the MOS
Since the drain region of the transistor and the base electrode take-out layer of the bipolar transistor are formed by the same diffusion layer, the fused BiMOS transistor can be miniaturized, and high-density integration and high performance of the semiconductor device can be promoted.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional view showing a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 9 is an equivalent circuit diagram of a fused BiNMOS transistor.

FIG. 10 is a cross-sectional view showing the structure of a conventional semiconductor device.

[Explanation of symbols]

 1 semiconductor substrate 4 P well 5 base layer 8 source region 12 gate electrode 15 emitter layer 16 collector electrode extraction layer 19 drain / base electrode extraction layer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiro Ishida 4-1-1 Mizuhara, Itami City Mitsubishi Electric Corp. LSI Research Institute

Claims (1)

[Claims] 1. A well region of a first conductivity type provided on a semiconductor substrate, a base layer of a second conductivity type, a gate electrode formed in the well region, a source region of a second conductivity type,
And a first conductivity type collector electrode extraction layer, a first conductivity type emitter layer formed in the base layer, and a second conductivity type drain in which the drain region and the base electrode extraction layer are formed of the same diffusion layer. A semiconductor device comprising: a base / electrode take-out layer, wherein the drain / base electrode take-out layer is formed extending from inside the well region to inside the base layer.