JP3845238B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a semiconductor device having a CMOS structure, and more particularly to a low-cost manufacturing method in which the number of masks is reduced and the process is simplified.
[0002]
[Prior art]
CMOS type semiconductor devices have become the mainstream of MOS type integrated circuits because of their low power consumption. At present, a twin well structure that can optimize the ion concentration of the substrate in the n-type MOS transistor region and the p-type MOS transistor region is usually used. In the manufacturing process for obtaining this structure, each of the conductive transistor forming processes requires a well forming process, a threshold voltage control process, and a source / drain forming process, and there is a problem that the process is long.
[0003]
For this reason, JP-A-7-222101 and JP-A-8-46058 require a mask for well region formation and high-concentration implantation of a conductivity type different from the well region when forming a CMOS type semiconductor device. A method for reducing the process by sharing a mask for forming a source / drain region is described. In applying such a simplified method, the key is a method of forming a well contact region that requires ion implantation at a high concentration of the same conductivity type as the well region.
[0004]
In Japanese Patent Laid-Open No. 7-222101, the following method is described as a method for forming the well contact region. First, a mask having an opening for forming a source / drain region and a small opening having a large aspect ratio for forming a well contact region is formed. Ion implantation for forming the well region is performed using oblique ion implantation at an angle that is not implanted into the small opening. The well contact region is formed by implanting only high-concentration ions without implanting ions for forming well regions of different conductivity types.
[0005]
  A schematic plan view of the semiconductor device of this publication is shown in FIG. In the figure, 4 is a gate electrode, 6 is P^-Well region, 7 is N⁺Source / drain region, 9 is N^-Well region, 10 is P⁺Source / drain regions, 20 is an N well contact region, 21 is a P well contact region, and 100 and 101 are dense contact portions. In the figure, the solid line is the boundary of the LOCOS element isolation region, and the dotted line isP ^-The border of the well region formation mask pattern, the thick lineN ^-It means the boundary of the well region forming mask pattern. 21 corresponds to FIGS. 1 to 3 in the above publication.
[0006]
Japanese Laid-Open Patent Publication No. 8-46058 describes a method in which contact is made with a channel stop layer below the LOCOS element isolation region, instead of using a well-implanted substrate as a well contact.
[0007]
[Problems to be solved by the invention]
However, in the case of the method using oblique ion implantation disclosed in Japanese Patent Application Laid-Open No. 7-222101, there is a problem that the throughput is lowered because the oblique implantation has a low processing capability. Further, since ions for forming the well region are obliquely implanted into the substrate, an opening region of a certain level or more is necessary, and there is a problem that the degree of freedom of circuit layout and miniaturization are limited.
[0008]
In Japanese Patent Application Laid-Open No. 8-46058, it is necessary to open a contact hole in the LOCOS element isolation region, and the contact etching must be performed more than a normal process. For this reason, there is a problem that the substrate is greatly dug at a thin portion of the LOCOS element isolation region, and junction leakage occurs in a fine process using a shallow junction.
[0009]
[Means for Solving the Problems]
  Thus, according to the present invention, (i) first conductivity type source / drain region formation region, second conductivity type source / drain region formation region, first conductivity type substrate contact region formation region, and second conductivity type well contact region formation After forming a LOCOS element isolation region that divides each region on the first conductivity type semiconductor substrate, a gate electrode is formed in each source / drain region formation region via a gate insulating film, and simultaneously with the formation of the gate electrode Forming a dummy gate electrode pattern on the outer periphery of the second conductivity type well contact region forming region;
(Ii) An opening for forming a second conductivity type source / drain region, a mask for forming a first conductivity type substrate contact region, and an opening for forming a second conductivity type well contact region Forming a mask pattern having,
(Iii) The second conductivity type source / drain region using the mask pattern by vertical ion implantation of 7 degrees or less under the condition that the gate electrode and the LOCOS element isolation region are not transmitted.And second conductivity type well contact regionOn the first conductive type substrate contact area under the condition of transmitting through the gate electrode and the LOCOS element isolation regionAreaForming, and
(Iv) An opening for forming the second conductivity type well region and the first conductivity type source / drain region, a mask portion covering the second conductivity type well contact region, and an end of the opening on the dummy gate electrode Forming a mask pattern having,
(V) Using the mask pattern, by vertical ion implantation of 7 degrees or less, the first conductivity type source / drain region is transmitted through the gate electrode and the LOCOS device isolation region under the condition that the gate electrode and the LOCOS device isolation region are not transmitted. Forming a second conductivity type well region under the following conditions:
A method for manufacturing a semiconductor device is provided.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in the order of steps.
First, LOCOS element isolation for partitioning a first conductivity type source / drain region formation region, a second conductivity type source / drain region formation region, a first conductivity type substrate contact region formation region, and a second conductivity type well contact region formation region, respectively After the region is formed on the first conductivity type semiconductor substrate, a gate electrode is formed in each source / drain region formation region via a gate insulating film (step (i)).
[0011]
The semiconductor substrate that can be used in the present invention is not particularly limited, but a silicon substrate is usually used. The semiconductor substrate has the first conductivity type. The first conductivity type means n-type or p-type. Examples of ions that give n-type include P ions and As ions, and examples of ions that give p-type include B ions.
[0012]
The LOCOS element isolation region can be formed by a normal LOCOS method. As the gate insulating film, a silicon oxide film, a silicon nitride film, or a laminated film thereof can be used. The gate electrode is made of a film known in the art such as a metal film such as aluminum or copper, a silicon film, or a silicide film. These gate insulating film and gate electrode can be formed by a known method.
[0013]
The first conductivity type source / drain region formation region, the second conductivity type source / drain region formation region, the first conductivity type substrate contact region formation region, and the second conductivity type well contact region formation region have desired characteristics. So that it is properly sized. These regions are usually rectangular, but are not limited to this shape, and may be other shapes such as a round shape and an oval shape. The second conductivity type means p-type when the first conductivity type is n-type, and n-type when the first conductivity type is p-type.
[0014]
Next, an opening for forming the second conductivity type source / drain region, a mask for forming the first conductivity type substrate contact region, and an opening for forming the second conductivity type well contact region are formed. A mask pattern is formed (step (ii)).
[0015]
The mask pattern can be formed by a known method. For example, a photoresist film can be formed on the entire surface by applying the material, and then exposed and developed so that the photoresist film remains in a predetermined mask pattern.
[0016]
Here, the opening for forming the second conductivity type source / drain region has, for example, 2 openings than the opening for forming the second conductivity type well contact region and the mask portion for forming the first conductivity type substrate contact region. It is preferable to have a width that is at least 3 times larger.
[0017]
Next, using the mask pattern of step (ii), the second conductivity type source / drain region and the second conductivity type well contact high concentration region are formed by vertical ion implantation of 7 degrees or less (step (iii)).
[0018]
Ion implantation for forming each region is performed within a range of 7 degrees or less, preferably 0 to 7 degrees from the perpendicular to the substrate surface. Each region is formed at a time, and the ion implantation conditions for formation are performed with energy that does not pass through the gate electrode and the LOCOS element isolation region. Specifically, energy of 10 to 40 KeV, 1 × 10¹⁵~ 5x10¹⁵/ Cm^-2It is preferable to carry out with the dose amount.
[0019]
Further, a mask pattern having an opening for forming the second conductivity type well region and the first conductivity type source / drain region and a mask portion for forming the second conductivity type well contact region is formed (step (step (2)). iv)).
[0020]
The method for forming the mask pattern is the same as the method for forming the mask pattern in the step (ii).
[0021]
Here, the opening for forming the second conductivity type well region and the first conductivity type source / drain region has a width that is, for example, 2 to 3 times larger than the mask portion for forming the second conductivity type well contact region. It is preferable to have.
[0022]
Next, a second conductivity type well region and a first conductivity type source / drain region are formed by vertical ion implantation of 7 degrees or less using the mask pattern of step (iv) (step (v)).
[0023]
Ion implantation for forming each region is performed within a range of 7 degrees or less, preferably 0 to 7 degrees from the perpendicular to the substrate surface.
[0024]
Here, the first conductivity type source / drain region and the second conductivity type well region are formed by separate ion implantation. Either of these ion implantation steps may be performed first.
[0025]
The ion implantation conditions for forming the first conductivity type source / drain regions are performed with energy that does not pass through the gate electrode and the LOCOS element isolation region. Specifically, energy of 10 to 40 KeV, 1 × 10¹⁵~ 5x10¹⁵/ Cm^-2It is preferable to carry out with the dose amount.
[0026]
On the other hand, the ion implantation conditions for forming the second conductivity type well region are performed with energy transmitted through the gate electrode and the LOCOS element isolation region. Specifically, an energy of 300 to 700 KeV, 10¹²-10¹³/ Cm^-2It is preferable to carry out with the dose amount.
[0027]
A semiconductor device can be manufactured through the above steps.
[0028]
In the method for manufacturing a semiconductor device of the present invention, each region can be formed by normal implantation without using oblique implantation, so that the throughput is improved as compared with the conventional method. Furthermore, since the manufacturing process can be simplified, a low-cost process can be realized. Further, even in a finer rule process, there is no problem that ions for forming a well region are not implanted in a minute space portion. In addition, junction leakage is less likely to be a problem due to overetching of the substrate. From the above, the present invention is more effective for a fine process.
[0029]
The second conductivity type source / drain region may be formed in the first conductivity type well region. This first conductivity type well region can be formed by vertical ion implantation of 7 degrees or less using the mask pattern of the step (ii). In this case, the first conductivity type substrate contact region becomes the first conductivity type well contact region.
[0030]
In the semiconductor device manufacturing method of the present invention, the first conductivity type substrate contact region or well contact region having the same conductivity type as the substrate is not ion-implanted at a high concentration, and only the second conductivity type well contact region different from the substrate is high. Ion implantation to concentration. Since this implantation is not oblique implantation, reverse conductivity type ions also enter the well contact region implanted at a high concentration. However, ion implantation for forming the reverse conductivity type well region is deepened and the implantation area is increased. If the absolute amount of ions implanted with a minimum is reduced, the influence can be reduced.
[0031]
Furthermore, in order to reliably connect the high-concentration regions of the substrate and the reverse conductivity type well region and the well contact region, each well contact region should have a LOCOS element isolation region in at least three of the four surrounding directions. Is preferred. In the active region without the LOCOS element isolation region, the conductivity type of the substrate surface is inverted, and if there is no LOCOS element molecular region, the well region and the high concentration region will be separated. Therefore, the ion implantation is performed through the LOCOS element isolation region to form the well region, so that the implantation depth becomes shallow, so that the concentration in the vicinity of the surface can be increased. As a result, the well region and the high concentration region can be prevented from separating.
[0032]
This is the same in both the normal well process and the twin well process.
[0033]
Moreover, it is preferable that the implantation depth for forming the first conductivity type well region in the step (iii) is deeper than the implantation depth for forming the second conductivity type well region in the step (v). Thereby, the influence of the reverse conductivity type ion implantation entering the well contact region can be minimized.
[0034]
Furthermore, the implantation depth for forming the first conductivity type well region in step (iii) may be deeper than the implantation depth for forming the second conductivity type well region in step (v). The former implantation depth is preferably 1.2 times or more deeper than the latter implantation depth.
[0035]
Further, two or three or more first well contact portions may be formed in the second conductivity type well contact region, and two or three or more plural wells may be formed in the first conductivity type substrate or well contact region. The second well contact portion may be formed. In this case, it is preferable that the first conductivity type substrate or the well contact region and the second conductivity type well contact region are partitioned by the LOCOS element isolation region. Thereby, an area can be made smaller than the conventional semiconductor device.
[0036]
Furthermore, a second conductivity type well contact region that is partitioned by the LOCOS element isolation region and located at the end of the second conductivity type well region may be formed. This region can be formed by using a mask pattern having no boundary on the end side of the second conductivity type well region in the steps (ii) and (iv).
[0037]
In step (i), a dummy gate electrode pattern is formed on the outer periphery of the second conductivity type well contact region formation region simultaneously with the gate electrode. In step (iv), the mask pattern is also formed on the dummy gate electrode pattern. In step (v), implantation for forming the second conductivity type well contact region may be performed using the mask pattern. By this step, a well region shallower than other regions can be formed.
[0038]
Furthermore, the gate electrode may have a two-layer structure, and the lower gate electrode may be used in the same manner as the dummy gate electrode pattern. Thereby, an ion region having an appropriate surface concentration can be formed under the gate electrode. Note that a flash (nonvolatile) memory can be manufactured by using a gate electrode having a two-layer structure.
[0039]
【Example】
Hereinafter, the present invention will be described in detail based on examples. The present invention is not limited by these examples.
(Example 1)
1 and 2 are schematic process cross-sectional views of the method for manufacturing a semiconductor device of the present invention. In this embodiment, an example of a manufacturing process of a CMOS semiconductor device using a P-type semiconductor substrate will be described.
[0040]
From the left in the figure, an NMOS transistor region, a P well contact region, a PMOS transistor region, and an N well contact region are shown. FIG. 3 is a schematic plan view of the resulting CMOS semiconductor device. 1 and 2 are cross-sectional views taken along the line D-D 'of FIG. FIGS. 4 to 6 are views particularly for explaining a manufacturing process of only the well contact region, and FIGS. 4 to 6 are cross-sectional views of the manufacturing process at A-A ′ in FIG. 3. N from the left (A side) in the figure^-Well contact region at the center of the well region, N^-Well contact region at the edge of the well region, P^-Well contact region in the center of the well region, P^-The well contact region at the end of the well region is shown.
[0041]
The manufacturing method of this apparatus will be described in the order of steps.
[0042]
First, as shown in FIGS. 1 and 4, a LOCOS element isolation region 2 having a thickness of 400 nm is formed on the semiconductor substrate 1 by a known LOCOS element isolation region formation step. Next, a gate electrode 4 is formed through a gate insulating film 3 made of a silicon oxide film having a thickness of 10 nm. After this, P^-Well region, N⁺A resist mask pattern 5 used for simultaneously performing implantation for forming the source / drain region and the N well contact region is formed by photolithography.
[0043]
Further, a plurality of first well contact portions 200, 202, 203 formed in the N well contact region (the dense contact region 100 in FIG. 3) and a P well contact region (the dense contact region 101 in FIG. 3) are formed. A plurality of second well contact portions 201, 204, and 205 are provided.
[0044]
The boundary of the two directions in the four directions around the first well contact portion 200 and the boundary in the two directions in the four directions around the second well contact portion 201 include a boundary of the LOCOS element isolation region and a boundary of the resist mask pattern 5. Exists.
[0045]
The boundary in the three directions in the four directions around the first well contact portions 202 and 203 and the boundary in the three directions in the four directions around the second well contact portions 204 and 205 include the boundary of the LOCOS element isolation region and the resist mask pattern. There are 5 boundaries.
[0046]
Next, P^-Implantation for well region formation, N channel stop implantation, channel implantation for matching Vth of transistor, N⁺Implantation for forming source / drain regions and N-well contact regions is performed at an implantation angle of 0 to 7 degrees.
[0047]
The injection conditions are P^-The implantation for forming the well region is performed when the ion species is B⁺Ion, energy is 400 keV, dose is 1E13 cm^-2N channel stop implantation is performed when the ion species is B⁺Ion, energy is 180 keV, dose is 1E13 cm^-2In the channel implantation, the ion species is B⁺Ion, energy 20 keV, dose 10¹²cm^-2Stand, N⁺The implantation for forming the source / drain region and the N well contact region is performed when the ion species is As.⁺Ion, energy is 40 keV, dose is 3E15 cm^-2It is.
[0048]
  Since the N well contact region is also open,High-concentration N-type ions (hereinafter referred to as N ⁺ Low concentration P-type ions (hereinafter referred to as P) ^- Called ion)Etc. enters this region as well, but as shown in FIG.^-Only the micro region is implanted with ions for forming the well region.^-The concentration is relatively low. Since the P well contact region is masked, N⁺Ions are not implanted. Further, as shown in FIGS. 1, 3 and 4, P in the P well contact region^-The ion implantation or the like for forming the well region is only by diffusion from the four directions, three directions, or two directions around the boundary of the LOCOS element isolation region.^-The concentration can be made relatively high.
[0049]
Next, as shown in FIG. 2 and FIG.^-Well region and P⁺A resist mask pattern 8 used for simultaneously performing implantation for forming source / drain regions is formed by photolithography.
[0050]
Further, the boundary of the LOCOS element isolation region and the boundary of the resist mask pattern 8 exist at the boundary in two of the four directions around the first well contact portion 200.
[0051]
The boundary of the LOCOS element isolation region and the boundary of the resist mask pattern 8 exist at the boundary in three out of the four directions around the first well contact portions 202 and 203.
[0052]
Then N^-Implantation for well region formation, P channel stop implantation, channel implantation for matching Vth of transistor, P⁺Implantation for forming the source / drain regions is performed at an implantation angle of 0 to 7 degrees.
[0053]
The injection conditions are N^-Implantation for forming the well region is performed by ion species of P ions, energy of 600 keV, and dose of 1 × 10.¹³cm^-2In the P channel stop implantation, the ion species is P ion, the energy is 300 keV, and the dose amount is 1 × 10.¹³cm^-2In the channel implantation, the ion species is B ion, the energy is 20 keV, and the dose is 10¹²cm^-2P,⁺Implantation for forming source / drain regions is performed when the ion species is BF.₂Ion, energy 30 keV, dose 2 × 10¹⁵cm^-2It is.
[0054]
Since both the N well contact region and the P well contact region are masked, P⁺Ions are not implanted and are implanted only in the PMOS transistor region.
[0055]
In addition, as shown in FIG. 3, the N well contact region has N directions beyond the LOCOS element isolation region in two or more directions.^-Since the ions for forming the well region are implanted, as shown in FIG.⁺Area and surrounding N^-The well region 9 can be surely touched.
[0056]
Next, as shown in FIG. 6, the first half process (wafer process) of the semiconductor device is completed through the formation of the interlayer film 11, the contact hole 12, the metal wiring 13, the protective film 14, etc. by a known method. To do.
[0057]
Finally, the assembly process of the latter half process is performed by a known method to complete the semiconductor device.
(Example 2)
7 and 8 show another example of the method for manufacturing a semiconductor device of the present invention. Also in this embodiment, an example of a manufacturing process of a CMOS semiconductor device using a P-type semiconductor substrate will be described. In Example 2, P is used.^-This is an example in which the present invention is applied to a process of a normal well in which no well region is formed. From the left in the figure, an NMOS transistor region, a P substrate contact region, a PMOS transistor region, and an N well contact region are shown. The manufacturing method of this apparatus will be described in the order of steps.
[0058]
First, as shown in FIG. 7, a LOCOS element isolation region 2 having a film thickness of 400 nm is formed on the semiconductor substrate 1 by a known LOCOS element isolation region forming step. Next, a gate electrode 4 is formed through a gate insulating film 3 made of a silicon oxide film having a thickness of 10 nm. After this, N⁺N for forming source / drain regions and N-well contact regions⁺A resist mask pattern 5 used for simultaneously performing ion implantation is formed by photolithography.
[0059]
Next, N channel stop injection, channel injection step for adjusting Vth of transistor, N⁺Implantation for forming source / drain regions is performed at an implantation angle of 0 to 7 degrees.
[0060]
The implantation conditions are as follows: N channel stop implantation, ion species B⁺Ion, energy is 180 keV, dose is 1E13 cm^-2In the channel implantation, the ion species is B⁺Ion, energy 20 keV, dose 10¹²cm^-2Stand, N⁺Implantation for forming source / drain regions is performed when the ion species is As.⁺Ion, energy is 40 keV, dose is 3E15 cm^-2It is.
[0061]
Here, since the N well contact region is also opened, N⁺Ions, ions for N channel stop implantation, and the like are implanted in the same manner. Since the P substrate contact region is masked, N⁺Ions are not implanted.
[0062]
Next, as shown in FIG.^-Well region and P⁺A resist mask pattern 8 used for simultaneously performing implantation for forming source / drain regions is formed by photolithography.
[0063]
Next, implantation for forming the N-well region, P channel stop implantation, channel implantation for matching the Vth of the transistor, P⁺Implantation for forming source / drain regions is performed at an implantation angle of 0 to 7 degrees.
[0064]
Since both the N well contact region and the P substrate contact region are masked, P⁺Ions are not implanted and are implanted only in the PMOS transistor region.
[0065]
The resist mask patterns 5 and 8 have the same pattern as that of the first embodiment in the dense contact region (not shown).
[0066]
Next, the first half process (wafer process) of the semiconductor device is completed through the interlayer film formation, contact hole formation, metal wiring formation, protective film formation, and the like by a known method.
[0067]
Finally, the assembly process of the latter half process is performed by a known method to complete the semiconductor device.
(Example 3)
FIGS. 9-12 is a modification of Example 1, and respond | corresponds to FIGS. FIGS. 10 to 12 are diagrams that describe only the well contact region. 9 is a plan view, and FIGS. 10 to 12 are schematic cross-sectional views of the manufacturing process at B-B ′ in FIG. 9. N from the left (B side) in the figure^-Well contact region at the center of the well region, N^-Well contact region at the edge of the well region, P^-Well contact region in the center of the well region, P^-The well contact region at the end of the well region is shown.
[0068]
The manufacturing method of this apparatus will be described in the order of steps.
[0069]
First, as shown in FIG. 10, a LOCOS element isolation region 2 having a film thickness of 400 nm is formed on the semiconductor substrate 1 by a known LOCOS element isolation region forming step. Next, a gate electrode 4 is formed through a gate insulating film 3 made of a silicon oxide film having a thickness of 10 nm.
[0070]
  This gate electrode 4aSimultaneously with the formation of the dummy gate electrode 4 around the N well contact region as shown in FIG.aSurround with. Although not shown in the drawing, the LOCOS element isolation region may be continuously covered with the dummy gate electrode pattern 4a.
[0071]
Next, P^-Well region and N⁺A resist mask pattern 5 for simultaneously performing implantation for forming source / drain regions is formed by photolithography. Furthermore P^-Implantation for well region formation, N channel stop implantation, channel implantation for matching Vth of transistor, N⁺Implantation for forming source / drain regions is performed at an implantation angle of 0 to 7 degrees. The injection conditions are P^-The implantation for forming the well region is performed when the ion species is B⁺Ion, energy is 400 keV, dose is 1E13 cm^-2N channel stop implantation is performed when the ion species is B⁺Ion, energy is 180 keV, dose is 1E13 cm^-2In the channel implantation, the ion species is B⁺ion. Energy is 20 keV, dose is 10¹²cm^-2Stand, N⁺Implantation for forming source / drain regions is performed when the ion species is As.⁺Ion, energy is 40 keV, dose is 3E15 cm^-2It is.
[0072]
Since the N well contact region is also open, N⁺Ion, P^-The ions for forming the well region are implanted in the same manner. However, as shown in FIG.^-Only the micro region is implanted with ions for forming the well region.^-The concentration can be made relatively low. Since the P well contact region is masked, N⁺Ion is not implanted, P^-The ion implantation for forming the well region is only by diffusion from the surrounding four directions or three directions.^-The concentration can be made relatively high.
[0073]
Next, as shown in FIG.^-Well region and P⁺A resist mask pattern 8 for simultaneously performing implantation for forming source / drain regions is formed by photolithography. Then N^-Implantation for well region formation, P channel stop implantation, channel implantation for matching Vth of transistor, P⁺Implantation for forming source / drain regions is performed at an implantation angle of 0 to 7 degrees.
[0074]
Since both the N well contact region and the P well contact region are masked, P⁺Ions are not implanted and are implanted only in the PMOS transistor region.
[0075]
Here, since the ions are implanted through the dummy gate electrode pattern around the N-well contact region where the dummy gate electrode pattern 4a is disposed earlier, the depth of ions implanted into the substrate is shallow, and the concentration on the surface is compared. Can be set high. Therefore, N in the N well contact region⁺Region 7 and surrounding N^-The well region 9 can be further connected to a low resistance.
[0076]
The resist mask patterns 5 and 8 have the same pattern as that of the first embodiment in the dense contact regions 100 and 101.
[0077]
Next, as shown in FIG. 12, the first half process (wafer process) of the semiconductor device is completed through the formation of the interlayer film 11, the formation of the contact hole 12, the formation of the metal wiring 13, the formation of the protective film 14, and the like.
[0078]
Finally, the assembly process of the latter half process is performed by a known method to complete the semiconductor device.
(Example 4)
In this embodiment, the gate electrode has a two-layer structure, and the lower gate electrode is also used as a dummy for injection profile control.
[0079]
13 to 16 are diagrams corresponding to FIGS. 9 to 12 of the third embodiment, respectively. In particular, FIGS. 14 to 16 are diagrams illustrating only the well contact region. FIG. 13 is a plan view, and FIGS. 14 to 16 are cross-sectional views taken along the line C-C ′ in FIG. 13. N from the left (C side) in the figure^-Well contact region at the center of the well region, N^-Well contact region at the edge of the well region, P^-Well contact region in the center of the well region, P^-The well contact region at the end of the well region is shown.
[0080]
The manufacturing method of this apparatus will be described in the order of steps.
[0081]
First, as shown in FIG. 14, a LOCOS element isolation region 2 having a thickness of 400 nm is formed on the semiconductor substrate 1 by a known LOCOS element isolation region formation step. Next, a lower layer 15 of the gate electrode is formed through the gate insulating film 3 made of a silicon oxide film having a thickness of 10 nm. Simultaneously with the formation of the lower layer 15, as shown in FIG. 13, the periphery of the N well contact region is surrounded by the dummy gate electrode pattern 15a, and the P well contact region is also covered by the dummy gate electrode pattern 15a. At this time, the LOCOS element isolation region may be continuously covered with the dummy gate electrode pattern 15a.
[0082]
Next, P^-Well region and N⁺A resist mask pattern 16 for simultaneously performing implantation for forming source / drain regions is formed by photolithography. Since the P well contact region is covered with the dummy gate electrode pattern 15a, the resist pattern 16 need not be left.
[0083]
Furthermore P^-Implantation for well region formation, N channel stop implantation, channel implantation for matching Vth of transistor, N⁺Implantation for forming source / drain regions is performed at an implantation angle of 0 to 7 degrees. The injection conditions are P^-The implantation for forming the well region is performed when the ion species is B⁺Ion, energy is 400 keV, dose is 1E13 cm^-2N channel stop implantation is performed when the ion species is B⁺Ion, energy is 180 keV, dose is 1E13 cm^-2In the channel implantation, the ion species is B⁺Ion, energy 20 keV, dose 10¹²cm^-2Stand, N⁺Implantation for forming source / drain regions is performed when the ion species is As.⁺Ion, energy is 40 keV, dose is 3E15 cm^-2It is.
[0084]
Further, a plurality of first well contact portions 200, 202, 203 formed in the N well contact region (the dense contact region 100 in FIG. 3) and a P well contact region (the dense contact region 101 in FIG. 3) are formed. A plurality of second well contact portions 201, 204, and 205 are provided.
[0085]
The boundary of the two directions in the four directions around the first well contact portion 200 and the boundary in the two directions in the four directions around the second well contact portion 201 include a boundary of the LOCOS element isolation region and a boundary of the resist mask pattern 5. Exists.
[0086]
The boundary in the three directions in the four directions around the first well contact portions 202 and 203 and the boundary in the three directions in the four directions around the second well contact portions 204 and 205 include the boundary of the LOCOS element isolation region and the resist mask pattern. There are 5 boundaries.
[0087]
Since the N well contact region is also open, N⁺Ion, P^-Ions and the like for well region formation are implanted in the same manner, but as shown in FIG.^-Only the minute region is implanted with ions for forming the well region.^-The concentration is relatively low. Further, as shown in FIG. 14, the P-well contact region is covered with a dummy gate electrode pattern 15a.⁺Ion is not implanted, P^-Implantation for forming the well region is performed through the dummy gate electrode pattern 15a. Therefore, P on the substrate surface^-The density can be set higher. Therefore, the resistance of the P well contact region can be further lowered.
[0088]
Next, as shown in FIG.^-Well region and P⁺A resist mask pattern 17 for simultaneously performing implantation for forming source / drain regions is formed by photolithography.
[0089]
Then N^-Implantation for well region formation, P channel stop implantation, channel implantation for matching Vth of transistor, P⁺Implantation for forming source / drain regions is performed at an implantation angle of 0 to 7 degrees. Since both the N well contact region and the P well contact region are masked, P⁺Ions are not implanted and are implanted only in the PMOS transistor region.
[0090]
Here, since the ions are implanted through the dummy gate electrode pattern around the N well contact region where the dummy gate electrode pattern 15a is disposed earlier, the depth of ions implanted into the substrate is shallow and the concentration on the surface is reduced. Can be set relatively high. Therefore, N in the N well contact region⁺Region 7 and surrounding N^-The well region 9 can be further connected to a low resistance.
[0091]
Next, although not shown, the dummy gate electrode pattern 15a can be removed by depositing a material layer for forming an upper gate electrode and processing this material layer together with the lower layer. FIG. 16 shows a state where the dummy gate electrode pattern 15a is removed.
[0092]
Next, the first half process (wafer process) of the semiconductor device is completed through the interlayer film 11 formation, contact hole 12 formation, metal wiring 13 formation, protective film 14 formation, and the like.
[0093]
Finally, the assembly process of the second half process is performed to complete the semiconductor device.
(Example 5)
This embodiment is an example in which a lower gate electrode is used as a dummy gate electrode pattern for injection profile control when a gate electrode such as a flash memory has a two-layer structure.
[0094]
17 to 20 are diagrams respectively corresponding to FIGS. 13 to 16 of the fourth embodiment. In particular, FIGS. 18 to 20 are diagrams illustrating only the well contact region. FIG. 17 is a plan view, and FIGS. 18 to 20 are sectional views of the manufacturing process at F-F ′ in FIG. 17. N from the left (F side) in the figure^-Well contact region at the center of the well region, N^-Well contact region at the edge of the well region, P^-Well contact region in the center of the well region, P^-The well contact region at the end of the well region is shown.
[0095]
The manufacturing method of this apparatus will be described in the order of steps.
[0096]
  First, as shown in FIG. 18, a LOCOS element isolation region 2 having a film thickness of 400 nm is formed on the semiconductor substrate 1 by a known LOCOS element isolation region forming step. Next, under the gate electrode through the gate insulating film 3 made of a silicon oxide film having a thickness of 10 nmLayerForm. Below thisLayeredSimultaneously with the formation, the periphery of the N well contact region is surrounded by the dummy gate electrode pattern 18a as shown in FIG. 17, and the P well contact region is also covered by the dummy gate electrode pattern 18a. At this time, the LOCOS element isolation region may be continuously covered with the dummy gate electrode pattern 18a.
[0097]
Next, P^-Well region and N⁺A resist mask pattern 16 for simultaneously performing implantation for forming source / drain regions is formed by photolithography. Since the P well contact region is covered with the dummy gate electrode pattern 18a, the resist pattern 16 need not be left.
[0098]
Furthermore P^-Implantation for well region formation, N channel stop implantation, channel implantation for matching Vth of transistor, N⁺Implantation for forming source / drain regions is performed at an implantation angle of 0 to 7 degrees. The injection conditions are P^-The implantation for forming the well region is performed when the ion species is B⁺Ion, energy is 400 keV, dose is 1E13 cm^-2N channel stop implantation is performed when the ion species is B⁺Ion, energy is 180 keV, dose is 1E13 cm^-2In the channel implantation, the ion species is B⁺Ion, energy 20 keV, dose 10¹²cm^-2Stand, N⁺Implantation for forming source / drain regions is performed when the ion species is As.⁺Ion, energy is 40 keV, dose is 3E15 cm^-2It is.
[0099]
Further, the plurality of first well contact portions 200, 202, 203 formed in the N well contact region (the dense contact region 100 in FIG. 17) and the P well contact region (the dense contact region 101 in FIG. 17) are formed. A plurality of second well contact portions 201, 204, and 205 are provided.
[0100]
The boundary of the two directions in the four directions around the first well contact portion 200 and the boundary in the two directions in the four directions around the second well contact portion 201 include a boundary of the LOCOS element isolation region and a boundary of the resist mask pattern 5. Exists.
[0101]
The boundary in the three directions in the four directions around the first well contact portions 202 and 203 and the boundary in the three directions in the four directions around the second well contact portions 204 and 205 include the boundary of the LOCOS element isolation region and the resist mask pattern. There are 5 boundaries.
[0102]
Since the N well contact region is also open, N⁺Ion, P^-The ions for forming the well region are implanted in the same manner, but as shown in FIG.^-Only the micro region is implanted with ions for forming the well region.^-The concentration is relatively low. Further, as shown in FIG. 18, the P-well contact region is covered with a dummy gate electrode pattern 18a.⁺Ion is not implanted, P^-Implantation for forming the well region is performed through the dummy gate electrode pattern 18a. Therefore, P on the substrate surface^-The density can be set higher. Therefore, the resistance of the P well contact region can be further lowered.
[0103]
Next, as shown in FIG.^-Well region and P⁺A resist mask pattern 17 for simultaneously performing implantation for forming source / drain regions is formed by photolithography.
[0104]
Then N^-Implantation for well region formation, P channel stop implantation, channel implantation for matching Vth of transistor, P⁺Implantation for forming source / drain regions is performed at an implantation angle of 0 to 7 degrees. Since both the N well contact region and the P well contact region are masked, P⁺Ions are not implanted and are implanted only in the PMOS transistor region.
[0105]
Here, since ions are implanted through the dummy gate electrode pattern around the N-well contact region where the dummy gate electrode pattern 18a is disposed earlier, the depth of ions implanted into the substrate is shallow, and the concentration on the surface is reduced. Can be set relatively high. Therefore, N in the N well contact region⁺Region 7 and surrounding N^-The well region 9 can be further connected to a low resistance.
[0106]
Next, although not shown, the dummy gate electrode pattern 18a can be removed by depositing a material layer for forming an upper gate electrode and processing this material layer together with the lower layer. FIG. 20 shows a state where the dummy gate electrode pattern 18a is removed.
[0107]
Next, the first half process (wafer process) of the semiconductor device is completed through the interlayer film 11 formation, contact hole 12 formation, metal wiring 13 formation, protective film 14 formation, and the like.
[0108]
Finally, the assembly process of the second half process is performed to complete the semiconductor device.
[0109]
【The invention's effect】
According to the present invention, in a semiconductor device using a CMOS structure, a mask process for forming an ion diffusion can be reduced by sharing a mask for forming a well region and a source / drain region, thereby simplifying a semiconductor process. There is an effect that can be done. In addition to cost reduction, the manufacturing process is shortened at the same time, which improves the turnaround time (TAT) and shortens the delivery time.
[Brief description of the drawings]
FIG. 1 is a manufacturing process cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention;
FIG. 2 is a manufacturing process cross-sectional view of the semiconductor device according to Example 1 of the present invention;
FIG. 3 is a schematic plan view of the semiconductor device according to the first embodiment of the present invention.
FIG. 4 is a schematic plan view of the semiconductor device according to the first embodiment of the present invention.
FIG. 5 is a manufacturing process cross-sectional view of the main part of the semiconductor device according to Example 1 of the present invention;
FIG. 6 is a manufacturing process cross-sectional view of the main part of the semiconductor device according to Example 1 of the present invention;
7 is a manufacturing process cross-sectional view of the main part of the semiconductor device according to Example 2 of the present invention; FIG.
FIG. 8 is a manufacturing process cross-sectional view of the main part of the semiconductor device according to Example 2 of the present invention;
FIG. 9 is a schematic plan view of a semiconductor device according to a third embodiment of the present invention.
FIG. 10 is a manufacturing process cross-sectional view of the main part of the semiconductor device according to Example 3 of the present invention;
FIG. 11 is a manufacturing process cross-sectional view of the main part of the semiconductor device according to Example 3 of the present invention;
FIG. 12 is a manufacturing process cross-sectional view of the main part of the semiconductor device according to Example 3 of the present invention;
FIG. 13 is a schematic plan view of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 14 is a manufacturing process cross-sectional view of the main part of the semiconductor device according to Example 4 of the present invention;
FIG. 15 is a manufacturing step sectional view of the essential part of the semiconductor device according to Example 4 of the present invention;
FIG. 16 is a manufacturing process sectional view of the main part of the semiconductor device according to Example 4 of the present invention;
FIG. 17 is a schematic plan view of a semiconductor device according to Example 5 of the present invention.
FIG. 18 is a manufacturing process cross-sectional view of the essential part of the semiconductor device according to Example 5 of the present invention;
FIG. 19 is a manufacturing process cross-sectional view of the main part of the semiconductor device according to Example 5 of the present invention;
20 is a manufacturing process sectional view of the main part of the semiconductor device according to Example 5 of the present invention; FIG.
FIG. 21 is a schematic plan view of a conventional semiconductor device.
[Explanation of symbols]
1 Semiconductor substrate
2 Locos element isolation region
3 Gate insulation film
4 Gate electrode
5, 8, 16, 17 Resist mask pattern
6P^-Well area
7 N⁺Source / drain region
9 N^-Well area
10 P⁺Source / drain region
11 Interlayer insulation film
12 Contact hole
200, 202, 203 First well contact portion
201, 204, 205 Second well contact portion
13 Metal wiring
14 Protective film
4a, 18a Dummy gate electrode pattern
20 N-well contact region
21 P-well contact region
100, 101 Close contact area

Claims (10)

(I) LOCOS element for partitioning a first conductivity type source / drain region formation region, a second conductivity type source / drain region formation region, a first conductivity type substrate contact region formation region, and a second conductivity type well contact region formation region, respectively After the isolation region is formed on the first conductivity type semiconductor substrate, a gate electrode is formed in each source / drain region formation region via the gate insulating film, and the second conductivity type well contact region is formed simultaneously with the formation of the gate electrode. Forming a dummy gate electrode pattern on the outer periphery of the formation region;
(Ii) An opening for forming a second conductivity type source / drain region, a mask for forming a first conductivity type substrate contact region, and an opening for forming a second conductivity type well contact region Forming a mask pattern having,
(Iii) Using the mask pattern, the second conductivity type source / drain region and the second conductivity type well contact region are gated by vertical ion implantation of 7 degrees or less under the condition that the gate electrode and the LOCOS element isolation region are not transmitted. forming a first conductivity type substrate contact area in conditions for transmitting electrodes and LOCOS isolation region,
(Iv) An opening for forming the second conductivity type well region and the first conductivity type source / drain region, a mask portion covering the second conductivity type well contact region, and an end of the opening on the dummy gate electrode Forming a mask pattern having,
(V) Using the mask pattern, by vertical ion implantation of 7 degrees or less, the first conductivity type source / drain region is transmitted through the gate electrode and the LOCOS device isolation region under the condition that the gate electrode and the LOCOS device isolation region are not transmitted. Forming a second conductivity type well region under the following conditions:
A method for manufacturing a semiconductor device, comprising: A second conductivity type source / drain region is formed in the first conductivity type well region, and the first conductivity type well region is separated from the gate electrode and the LOCOS element by ion implantation of 7 degrees or less using the mask pattern of step (ii). The first conductivity type substrate contact region includes a plurality of second well contact portions, and the first conductivity type substrate or the well contact region and the second conductivity type well contact region are located in the LOCOS element isolation region. The production method according to claim 1 , which is partitioned by A plurality of first well contact portions are provided in the second conductivity type well contact region, a plurality of second well contact portions are provided in the first conductivity type substrate or well contact region, and the first conductivity type substrate or well contact region and The manufacturing method according to claim 1, wherein the second conductivity type well contact region is partitioned by a LOCOS element isolation region. The manufacturing method according to claim 3, wherein two or three or more first and second well contact portions are formed. 2. The first conductivity type substrate or well contact region includes a region in which three directions are partitioned by a LOCOS element isolation region and the remaining one direction is not partitioned by a LOCOS element isolation region among the four directions around the first conductivity type substrate or well contact region. Or the manufacturing method of 2. In step (iii), the implantation depth for forming the second conductivity type source / drain region and the second conductivity type well contact region is shallower than the implantation depth for forming the first conductivity type well region;
3. The manufacturing method according to claim 2, wherein in step (v), the implantation depth for forming the first conductivity type source / drain region is shallower than the implantation depth for forming the second conductivity type well region. The manufacturing method according to claim 2, wherein an implantation depth for forming the first conductivity type well region in the step (iii) is deeper than an implantation depth for forming the second conductivity type well region in the step (v). The gate electrode in step (i) is a lower layer gate electrode, and after step (v), an electrode material layer is stacked and then patterned to form an upper layer gate electrode on the lower layer gate electrode and to form a dummy gate electrode pattern. The manufacturing method according to claim 1 to be removed. (I) LOCOS element for partitioning a first conductivity type source / drain region formation region, a second conductivity type source / drain region formation region, a first conductivity type substrate contact region formation region, and a second conductivity type well contact region formation region, respectively After the isolation region is formed on the first conductivity type semiconductor substrate, a gate electrode is formed in each source / drain region formation region via the gate insulating film, and the second conductivity type well contact region is formed simultaneously with the formation of the gate electrode. Forming a dummy gate electrode pattern so as to cover the outer periphery of the formation region and the first conductivity type substrate contact region formation region;
(Ii) An opening for forming a second conductivity type source / drain region, a mask for forming a first conductivity type substrate contact region, and an opening for forming a second conductivity type well contact region Forming a mask pattern having,
(Iii) Using the mask pattern, the second conductivity type source / drain region and the second conductivity type well contact region are gated by vertical ion implantation of 7 degrees or less under the condition that the gate electrode and the LOCOS element isolation region are not transmitted. forming a first conductivity type substrate contact area in conditions for transmitting electrodes and LOCOS isolation region,
(Iv) An opening for forming the second conductivity type well region and the first conductivity type source / drain region, a mask portion covering the second conductivity type well contact region, and an end of the opening on the dummy gate electrode Forming a mask pattern having,
(V) Using the mask pattern, by vertical ion implantation of 7 degrees or less, the first conductivity type source / drain region is transmitted through the gate electrode and the LOCOS device isolation region under the condition that the gate electrode and the LOCOS device isolation region are not transmitted. Forming a second conductivity type well region under the following conditions:
A method for manufacturing a semiconductor device, comprising: The manufacturing method according to claim 9, wherein the dummy gate electrode pattern covering the first conductivity type substrate contact region forming region also covers the LOCOS element isolation region.

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