JP2002208694A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device comprising a high breakdown- strength MOS transistor together with its manufacturing method, wherein a mutual conductance is enhanced to reduce the chip area. SOLUTION: The impurity concentration of an n-offset region 8 and a p-offset region 5 on a source side is enhanced, so that the mutual conductance of the high breakdown-strength MOS transistor is raised, resulting in a reduced special area of the high breakdown-strength MOS transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a high breakdown voltage transistor constituting a CMOS.

[0002]

2. Description of the Related Art When a low breakdown voltage CMOS and a high breakdown voltage CMOS are formed on the same semiconductor substrate, the drain of a low breakdown voltage MOS transistor constituting the low breakdown voltage CMOS has a single drain structure. On the other hand, high voltage MOS transistors
In order to secure a withstand voltage, usually, a LOCOS oxide film is formed between a gate and a source, and between a gate and a drain.
The offset gate structure has a low concentration diffusion layer formed below the LOCOS oxide film. Among the low-concentration diffusion layers, the n-type low-concentration diffusion layer is referred to as an n-offset region, and the p-type low-concentration diffusion layer is referred to as a p-offset region. The same shape and impurity concentration are formed (symmetric structure).

FIGS. 4 to 6 are cross-sectional views of a main part manufacturing process shown in the order of steps in a conventional method of manufacturing a semiconductor device. These figures are cross-sectional views of the manufacturing process of the high breakdown voltage MOS transistor constituting the CMOS. In FIG. 4, an n-well region 52 and a p-well region 5
Form 3 Next, p-offset regions 54, 55 and n-offset regions 57, 58 are formed on the surface layers of the n-well region 52 and the p-well region 53, and a high-concentration p-guard ring 56, n-guard Ring 59
To form

In FIG. 5, subsequent to FIG. 4, LOCOS oxide films 60 to 66, which are field oxide films, are formed except for portions where gate electrodes 69 and 70, drain regions 71 and 73 and source regions 72 and 74 are to be formed. Form. Next, thick gate oxide films 67 and 68 are formed, and a first layer polysilicon for the gate electrodes 69 and 70 is deposited.
Next, the first layer polysilicon is applied to the LOCOS oxide film 60.
Etching is carried out to a predetermined size so as to leave a part on .about.63, and thick gate oxide films 67 and 68 are etched using this first layer polysilicon as a mask. Next, a thin gate oxide film of a low breakdown voltage MOS transistor (not shown) is grown, a second layer polysilicon is deposited, and the thin gate oxide film is etched to a predetermined size. By doing so, both the thick gate oxide films 67 and 68 and the thin gate oxide film (not shown) can be patterned without using a resist film as a mask material, so that the film quality can be secured without being contaminated by the resist film.

Next, an n drain region 71 and an n source region 72 are formed on the surface layers of the n offset regions 54 and 55 where the LOCOS oxide film is opened, and a p offset region 57 where the LOCOS oxide film is opened. 58 on the surface layer
A drain region 73 and a p source region 74 are formed. FIG.
5, following FIG. 5, after depositing an interlayer insulating film 75 on the surface, a contact hole is opened and a drain electrode 7 is formed.
6 and 78 and source electrodes 77 and 79 are formed, and a protective film 80 is deposited thereon.

In this way, a semiconductor device is formed in which a low-breakdown-voltage CMOS constituted by a low-voltage MOS transistor having a thin gate oxide film and a high-breakdown-voltage CMOS constituted by a high-voltage MOS transistor having a thick gate oxide film are formed.
FIG. 6 is a cross-sectional view of a main part of a conventional semiconductor device on which a high breakdown voltage CMOS is formed.

[0007]

However, as described above, the presence of the low-concentration offset regions 54, 55, 57, and 58 increases the sheet resistance of the offset regions and lowers the mutual conductance of the high-voltage MOS transistor. I do. The transconductance is a value obtained by dividing a change in drain current by a change in gate voltage. Low transconductance means that a small drain current flows for a given gate voltage. Therefore, in order to obtain high transconductance,
In order to allow a necessary drain current to flow, the area occupied by the chip of the high breakdown voltage MOS transistor must be increased.

It is an object of the present invention to provide a semiconductor device having a high-breakdown-voltage MOS transistor capable of solving the above-mentioned problems, increasing the mutual conductance and reducing the chip area, and a method of manufacturing the same. It is in.

[0009]

In order to achieve the above object, there is provided a MOS type semiconductor device having an offset region on a source side and a drain side, wherein the impurity concentration is higher than the impurity concentration of the offset region on the drain side. Having a source-side offset region. The first conductivity type well region and the second conductivity type well region are formed adjacent to the surface layer of the first conductivity type semiconductor substrate, and are formed separately from the surface layer of the first conductivity type well region. A first offset region of a second conductivity type, a second offset region, a third offset region of a first conductivity type formed on a surface layer of the well region of the second conductivity type, and a fourth offset region; A first guard ring region formed on the surface layer of the one conductivity type well region so as to surround the first offset region and the second offset region; and a third offset region formed on the surface layer of the second conductivity type well region. A second guard ring region formed to surround the region and the fourth offset region; a first source region of a second conductivity type formed in a surface layer of the first offset region; and a surface layer of the second offset region. Formed into A first drain region of the second conductivity type, a second source region of the first conductivity type in a surface layer of the third offset region,
A second drain region formed in a surface layer of the fourth offset region and a first conductivity type well region sandwiched between the first offset region and the second offset region are formed via a first gate insulating film. A first gate electrode, a second gate electrode formed on the second conductivity type well region interposed between the third offset region and the fourth offset region via a second gate insulating film, and the first offset electrode; A semiconductor device comprising: a first LOCOS oxide film formed on a region; and a second LOCOS oxide film formed on the second offset region, wherein the impurity concentration of the first offset region is equal to that of the second offset region. Higher than the impurity concentration,
The third offset region has a higher impurity concentration than the fourth offset region.

[0010] Also, the surface layer of the first conductivity type semiconductor substrate may be
Forming a first conductivity type well region and a second conductivity type well region adjacent to each other; forming a second conductivity type second offset region on a surface layer of the first conductivity type well region; Forming a fourth offset region of a first conductivity type in a surface layer of the region; a first guard ring region surrounding the second offset region in a surface layer of the well region of the first conductivity type; Forming a third offset region apart from the fourth offset region of the well region; and forming the second guard ring region surrounding the third offset and the fourth offset region on a surface layer of the second conductivity type well region. And the second layer on the surface layer of the first conductivity type well region.
Forming a first offset region surrounded by the first guard ring region including the second offset region apart from the offset region; and forming the first offset region, the second offset region, the third offset region, The fourth
The first LOCOS oxide film, the second LOC
Forming an OS oxide film, a third LOCOS oxide film, and a fourth LOCOS oxide film; a first source region of a second conductivity type on a surface layer of the first offset region; and a second conductive film on a surface layer of the second offset region. Forming a first drain region of the first conductivity type; forming a second source region of the first conductivity type on the surface layer of the third offset region; and forming a second drain region on the surface layer of the fourth offset region. Forming a first gate electrode via a first gate insulating film on a first conductivity type well region sandwiched between the first offset region and the second offset region; Forming a second gate electrode on the second conductivity type well region interposed between the four offset regions with a second gate insulating film interposed therebetween. The impurity concentration of the bets region, the second
The impurity concentration of the third offset region may be higher than the impurity concentration of the fourth offset region.

[0011]

FIG. 7 is a diagram for explaining the gist of the present invention. This figure is an enlarged view of the vicinity of the gate of the high-breakdown-voltage p-channel MOSFET of FIG. 3 described later. 2 in the figure
Is an n-well region, 4 is a p-offset region on the drain side,
5 is a source side p offset region, 10 is a drain side LOCOS oxide film, 11 is a source side LOCOS oxide film, 17 is a thick gate oxide film, and 19 is a gate electrode.

The thickness of the gate oxide film 17 of the high breakdown voltage MOS transistor is increased in order to maintain the breakdown voltage between the gate and the source and between the gate and the drain. This thick gate oxide film 17 is formed by etching using gate electrode 19 formed of polysilicon as a mask. At this time,
Since the gate oxide film 17 is thick, the side-etch amount L2 increases, and the withstand voltage between the gate and the source may decrease.

In order to prevent side etching of the thick gate oxide film 17, a LOCOS oxide film 11 is formed between the gate and the source, and a thick gate oxide film 17 is coated on the LOCOS oxide film 11, Oxide film 11
The thick gate oxide film 17 formed thereon is etched. In this case, even when the side etch amount L2 is large, the LOCOS oxide film 11 is etched, and the gate oxide film 17 at the location L1 on the silicon substrate is not affected. Therefore, in a high-breakdown-voltage MOS transistor requiring a thick gate oxide film 17, LOC is also required on the source side.
An OS oxide film 11 is required. When the LOCOS oxide film 11 is formed on the source side, the p-offset region 5
The need to form comes out.

In the high breakdown voltage MOS transistor, the pn junction for maintaining the breakdown voltage between the source and the drain is the pn junction between the drain side p offset region 4 and the n well region 2, and the source side p offset region 5 and the n well. Area 2
Pn junction. Therefore, the p-side offset region 5 on the source side and the p-side offset region 4 on the drain side are formed asymmetrically (different in impurity concentration), and the impurity concentration of the p-side offset region 5 on the source side is changed to the impurity concentration of the p-side offset region 4 on the drain side. Can be higher.

According to the present invention, by increasing the impurity concentration of the offset region on the source side, the sheet resistance of the offset region is reduced, and the transconductance is improved. Hereinafter, examples will be described. 1 to 3 show a method of manufacturing a semiconductor device according to an embodiment of the present invention, and are sectional views of a main part manufacturing process shown in the order of processes. These figures are cross-sectional views of a manufacturing process of a high breakdown voltage MOS transistor constituting a high breakdown voltage CMOS.

In FIG. 1, the specific resistance is 10 to 15 Ω · cm.
5 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² at an acceleration energy of 100 to 200 keV.
After ion implantation at a dose of about a degree, annealing (drive step) is performed to form an n-well region 2. Subsequently, boron is accelerated to 2 × 10 ¹² c at an acceleration energy of 30 to 100 keV.
After ion implantation at a dose of m ^{−2 to} 5 × 10 ¹² cm ⁻² , annealing is performed to form a p-well region 3.

Next, boron is applied to the surface layer of the n-well region 2 at an acceleration energy of 50 to 100 keV for 1 × 10 ¹³ c.
ion implantation at a dose of m ^{-2 to} 2 × 10 ¹³ cm ^-2 ,
An ion implantation layer (not shown) of the p-side offset region 4 on the drain side is formed.
3 × 10 ¹² cm ² -1 at acceleration energy of 100 keV
Ions are implanted at a dose of × 10 ¹³ cm ² to form an ion implantation layer (not shown) in the n-side offset region 7 on the drain side.

Next, annealing is performed to reduce the p-side on the drain side.
The offset region 4 and the n-offset region 7 are formed. Next
Then, boron is added to the surface layer of the n-well region 2 by 50 to 100.
5 × 10 at keV acceleration energy¹³cm^-2~ 1 × 10
¹⁴cm^-2cm^-2With a dose of p guard ring 6 and saw
P offset region 5 on the drain side (p offset on the drain side)
(Improve the dose than the region 4)
A phosphorus layer on the surface layer of the p-well region 3;
1 × 10 with acceleration energy of 00 keV¹³cm^-2~ 3x
10 ¹³cm^-2Ion implantation at a dose of
9 and the source side n offset region 8 (drain side
(The dose is made higher than the n offset region 7)
A non-implanted layer, then annealed,
Source side p offset region 5 and n offset region 8
And a p guard ring 6 and an n guard ring 9 are formed. This
P guard ring 6 is formed between p drain region 4 and p source region.
Formed in a band shape so as to surround the area 5, and an n guard ring
9 surrounds the n drain region 7 and the n source region 8
Formed.

The sheet resistance of the drain side p offset region 4 and the n offset region 7 is 1 kΩ / □ to 10
and the sheet resistance of the source side p offset region 5 and the n offset region 8 is from 50 Ω / □ to 1000
Ω / □. In FIG. 2, following FIG. 1, gate electrodes 19 and 20, p drain region 21, p source region 22
LOCOS oxide films 10 to 16 as field oxide films are formed except for portions where the n drain region 23 and the n source region 24 are to be formed.

Next, 50 to 100 nm thick gate oxide films 17 and 18 are formed, and gate electrodes 19 and 20 are further formed.
Deposit a first layer of polysilicon to form Next, the first layer polysilicon is applied to the LOCOS oxide films 10 and 1.
Etching is performed to a predetermined size so as to leave a part on 1, 12, and 13, and using the first layer polysilicon as a mask, the thick gate oxide films 17 and 18 are etched. Next, a thin gate oxide film for a low-voltage MOS transistor (not shown) is grown, a second-layer polysilicon (not shown) is deposited, and the thin gate oxide film is etched to a predetermined size.

By doing so, the thick gate oxide film 1 is formed.
Both the thin gate oxide films 7 and 18 and not shown can be patterned without using a resist film as a mask material.
The gate oxide film 17, 1 without being contaminated by the resist film.
8 can be secured. Next, arsenic is applied to the surface layers of the p offset regions 4 and 5 where the LOCOS oxide film is opened at an acceleration energy of 50 to 100 keV for 3 × 10 ¹⁵ cm.
Ions are implanted at a dose of ^{-2 to} 5 × 10 ¹⁵ cm ^-2 , and then 50 to 100 keV boron difluoride is applied to the surface layers of the n offset regions 7 and 8 where the LOCOS oxide film is opened.
3 × 10 ¹⁵ cm ^{-2 to} 5 × 10 ¹⁵ cm with acceleration energy of
Ion implantation is performed at a dose of ^-2 and annealing is performed to form a p drain region 21, a p source region 22, an n drain region 23, and an n source region 24.

In FIG. 3, following FIG. 2, after an interlayer insulating film 25 is deposited on the surface, contact holes are opened, and drain electrodes 26 and 28 and source electrodes 27 and 2 are formed.
9, and a protective film 30 is formed on the surface (FIG. 3). Thus, the high withstand voltage M of the thick gate oxide films 17 and 18 is increased.
A semiconductor device is formed in which a high withstand voltage CMOS composed of OS transistors and a low withstand voltage CMOS composed of low voltage MOS transistors with thin gate oxide films 17 and 18 (not shown) are formed. FIG. 3 is a sectional view of a main part of the semiconductor device of the present invention.

In this high-voltage MOS transistor, the source-side offset regions 5 and 8 are formed at the same high impurity concentration as the guard rings 6 and 9, so that the drain-side offset regions 4 and 7, the sheet resistance of the offset regions 5 and 8 becomes smaller, and the mutual conductance can be improved. As a result, the area occupied by the high voltage MOS transistor in the chip can be reduced.

Further, the source side offset regions 5 and 8 can be formed simultaneously with the guard rings 6 and 9 using the same mask, so that the number of steps is the same as in the prior art. Further, as described above, the offset regions 5 and 8 on the source side and the well regions 2 and
When the potentials 3 are the same, the offset regions 5 and 8 on the source side and the well regions 2 and 3 may be short-circuited.

[0025]

According to the present invention, by reducing the sheet resistance of the offset region on the source side, the mutual conductance can be improved, and the area occupied by the high voltage MOS transistor can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part manufacturing process of a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a sectional view of a main part manufacturing step of the semiconductor device according to the embodiment of the present invention, following FIG. 1;

FIG. 3 is a sectional view of a main part manufacturing step of the semiconductor device according to the embodiment of the present invention, following FIG. 2;

FIG. 4 is a cross-sectional view of a main part manufacturing process of a conventional semiconductor device.

FIG. 5 is a cross-sectional view of a main part manufacturing step of the conventional semiconductor device, following FIG. 4;

FIG. 6 is a cross-sectional view of a main part manufacturing step of the conventional semiconductor device, following FIG. 5;

FIG. 7 is a view for explaining the gist of the present invention;

[Explanation of symbols]

 Reference Signs List 1 p silicon substrate 2 n-well region 3 p-well region 4 n offset region (drain side) 5 n offset region (source side) 6 n guard ring 7 p offset region (drain side) 8 p offset region (source side) 9 p Guard ring 10-16 LOCOS oxide film 17, 18 Thick gate oxide film 19, 20 Gate electrode 21 n Drain region 22 n source region 23 p drain region 24 p source region 25 Interlayer insulating film 26, 28 Drain electrode 27, 29 Source electrode 30 Protective film

Claims (3)

[Claims] 1. A MOS semiconductor device having an offset region on a source side and a drain side, wherein the semiconductor device has a source-side offset region having a higher impurity concentration than an impurity concentration of the drain-side offset region. Semiconductor device. 2. A first conductivity type well region and a second conductivity type well region which are formed adjacent to a surface layer of a first conductivity type semiconductor substrate, and are separated from a surface layer of the first conductivity type well region. A first offset region and a second offset region of the second conductivity type formed, and a third offset region and a fourth offset region of the first conductivity type formed separately on the surface layer of the well region of the second conductivity type. A first guard ring region formed in a surface layer of the first conductivity type well region so as to surround the first offset region and the second offset region;
A second guard ring region formed on the surface layer of the conductive type well region so as to surround the third offset region and the fourth offset region, and a second conductive type second region formed on the surface layer of the first offset region. A first drain region of a second conductivity type formed on a surface layer of the second offset region; a second source region of a first conductivity type on a surface layer of the third offset region; A second drain region formed in a surface layer of the offset region, and a first gate formed on a first conductivity type well region interposed between the first offset region and the second offset region via a first gate insulating film. An electrode, a second gate electrode formed on the second conductivity type well region interposed between the third offset region and the fourth offset region via a second gate insulating film, and the first offset region. A first 1LOCOS oxide film formed on, the 2LOCO formed in the second offset region
An impurity concentration of the first offset region is higher than an impurity concentration of the second offset region, and an impurity concentration of the third offset region is higher than an impurity concentration of the fourth offset region. A semiconductor device characterized by having a higher impurity concentration. 3. A step of forming a first conductivity type well region and a second conductivity type well region adjacent to a surface layer of a first conductivity type semiconductor substrate, and forming a first conductivity type well region on the surface layer of the first conductivity type well region. 2
Forming a second offset region of a conductivity type and a fourth offset region of a first conductivity type in a surface layer of the well region of the second conductivity type; and forming the second offset region in a surface layer of the well region of the first conductivity type. Forming a first guard ring region surrounding the region and a third offset region apart from the fourth offset region of the second conductivity type well region;
A second guard ring region surrounding the third offset region and the fourth offset region on a surface layer of the conductive type well region; and a second offset region separated from the second offset region on the surface layer of the first conductive type well region. Forming a first offset region surrounded by the first guard ring region including the region, and forming a first LOCOS in the first offset region, the second offset region, the third offset region, and the fourth offset region. Oxide film, 2nd LOCOS
Forming an oxide film, a third LOCOS oxide film, and a fourth LOCOS oxide film; a first source region of a second conductivity type on a surface layer of the first offset region; and a second conductivity type on a surface layer of the second offset region. Forming a first drain region, a second source region of a first conductivity type in a surface layer of the third offset region, and a second drain region in a surface layer of the fourth offset region. Forming a first gate electrode via a first gate insulating film on a first conductivity type well region sandwiched between the first offset region and the second offset region; Forming a second gate electrode on the second conductivity type well region sandwiched between the offset regions with a second gate insulating film interposed therebetween, the method comprising: A method of manufacturing a semiconductor device, wherein an impurity concentration of a region is higher than an impurity concentration of the second offset region, and an impurity concentration of the third offset region is higher than an impurity concentration of the fourth offset region.