JPS61136255A - Composite semiconductor device - Google Patents

Abstract

PURPOSE:To bring an integrated circuit, which never generate a latch-up phenomenon and which has a high-load driving power in low power consumption, into a high-density state by a method wherein the MOSFET and the bipolar transistor are structurally formed in one body. CONSTITUTION:A metal silicide film shows a Schottky junction property to an N type semiconductor layer and shows an ohmic property to a P type semiconductor layer. When the source and drain of the PMOSFET are respectively formed of a metal silicide film 112c and a metal silicide film 112b, the Schottky PMOSFET is formed, and moreover, the ohmic contact with a P type semiconductor layer 104a can be also made directly. Moreover, the well contact with a semiconductor layer 103 can be made by a metal silicide film 112c through a high-concentration N type semiconductor layer 105b. Furthermore, the gate direct contact can be made by forming a metal silicide film 112f in a self- matching manner with the source and drain. As a result, it can be contrived to drop the gate resistance and to bring the integrated circuit into a high-density state.

Description

[Detailed description of the invention] (Minute hand for use in medicine) The misfire is a device that is small in size, has a negative drive, and has low power consumption Note. It is.

(Prior Art) Conventionally, this composite semiconductor device has a structure shown in FIG. 2 and has a length of 7t. In the second factor, 100 is a P-type medium conductor substrate,
101 is a P-type medium conductor layer, 102 is a high concentration N-type semiconductor buried layer, 103 is an N-type semiconductor 9L, and 104 is a P-type semiconductor layer.
105 is a highly concentrated N type semiconductor layer, 106 is a highly concentrated P type semiconductor layer, 111 is a polysilicon gate layer, and a 110μ metal electrode. From the left in Figure 2, 105b
'i minimitter 106a' fr base, 105a
Vertical npn bipolar transistor Q with f collector
n-106c 2 drain, 1061) source, 1
P Nayanel IViO8FET with 05c as the back gate and 111a as the gate.

105d k drain, 105e f source, 1llf
N Nayanel MO8FET' with gate i is shown respectively.

1. Introducing 106a and 106b through the metal 1L pole 110i, and by connecting 105a and 105c in the same way, the circuit shown in Figure 3 can be constructed.
In the figure Kh, MP is a P-type MO8FET, and Qn is an npn bipolar transistor. 2MO8FET
By constructing npn bipolar all paulownia in the next stage, 2MO8FET with apparently large go can be constructed.
It is expected that the output load drive steering force of the complementary circuit will be significantly improved.

(Problems that the invention is trying to solve) However, in the structure shown in Figure 2, PMO8FET
103a and 1031) in order to structurally combine the bipolar transistors and create a primary occupied surface.
'If you combine it with 9, you will get the shape shown in Figure 4, which is 106c.
mWpnp bipolar transistor (Qp) with f emitter, 103a k base, 104jL collector
) or 7? : is formed. Here, Qp's pace and Qn's collector are Qp's collector and Qn's base,
106c as they each share.

103i, 104a, and 105b form a parasitic pnpn thyristor structure. In this structure, the collector charge of Qn is =9, and the base-emitter voltage of Qp is increased.
When Qp is turned on, the drawback of the ratteag phenomenon, which is a problem in bulk CMO8, occurs.

For this reason, in Figure 2, it is necessary to divide the space of the npn transistor (Qn) and the back gate layer of the 2MO8FET, and as a result, a very large occupied 1ILI is required. There were drawbacks.

[Problem f: middle step to resolve PS]

The present invention was proposed in order to eliminate the disadvantage of increasing the occupying area, and by making it similar to integrating a MOS FET and a bipolar transistor, it is possible to eliminate the lattice effect and reduce consumption. The overall object of the present invention is to provide a semiconductor device that has a high-capacity integrated circuit that can be driven by electric power.

In order to achieve the above object, the present invention
a first semiconductor layer forming a type semiconductor substrate; and a second semiconductor layer provided in a partial region of the main surface of the tenth semiconductive layer of the previous 8C and forming the entire well region of the second conductivity type. layer and
A third semiconductor 1 of a first conductivity type, which is formed in a part of the semiconductor layer of Part 2 and is shallower than the depth of the second semiconductor layer by an amount of light.
11, a second 4-type fourth semiconductor layer with a height formed in a part of the 30th half-body layer, and a second 4-type semiconductor layer of the third #P half-body layer. The above-mentioned 20th LP conductor layer region 1c
A first Kanajima silicide which extends and forms a Schottky junction for the first conductor type and forms an ohmic contact for the 241st NL type, and the Kanahashi silicide of the above bi. The first Kanabashi silicide layer, the second Kanamari silicide layer, and the first and second Kanamari silicide layers are formed in the second semiconductor layer region by cutting and distributing them at a sufficient distance t''. and 0, and a second 4 mW fifth semiconductor layer with a high concentration formed in a part under the second metal silicide film, A third metal silicide layer is formed on the fourth (1) semiconductor layer of the first metal silicide layer, and is formed on top of the third metal silicide layer similar to the first metal silicide layer. The gist of the invention is a composite semiconductor device in which silicide films are used as the first, second, and third electrodes, respectively.

Furthermore, the non-explosion fy) is formed in the first semiconductor layer forming the semiconductor substrate of the first conductive region and the Wael region of nl and second V conductivity type provided in a partial region of the main surface of the semiconductor layer of the above wJl. a second semiconductor layer formed on a part of the second semiconductor layer described in i1], and a third semiconductor layer of a conductive layer 1La having a diameter of 1 and a depth of 100 nm, Raku 30 mentioned above
The second 4 of the high-density structure formed in a part of the semiconductor RIII
The electric field area of the fourth semiconductor layer and the third semiconductor layer is extended to the second semiconductor layer region, and a Schottky junction is formed for the first and second semiconductor layer regions. For the second conductivity type, the first full-length silicide layer forming an ohmic contact and the #42 semiconductor layer are separated from each other by a distance between the first metal silicide layer and the first metal silicide layer. The first
A second Kinkaede siri-d film, which is the same as the Kanasu sili-d film,
A first gate having a thin oxidized AG layer formed on the first and second gold maple silicide bed, and a part of the second gold maple silicide layer 7? : A high-concentration second silica-type fifth semiconductor layer and a third metal similar to the first Kanazawa silica film formed on the fourth semiconductor layer. 7 silicide sides, and the 1st, 2nd, and 3rd Kinten silicides of each of the 1st, 2nd, and
A semiconductor device with a third 11L pole and a first #
! -1Iipf4: The distance between the first ac-shaped sixth semiconductor layer and the first ac sixth semiconductor layer region formed on a part of the surface of the layer is IQIt. formed pills 2
7th and 8th semiconductor layers of conductive type 11L, and
．． On the eighth semiconductor layer, fourth and fifth metal silicide films are formed, each having a Schottky alloy for the first Hironan type and forming an ohmic contact for the second 11-Turtle type. The gist of the invention is a composite semiconductor device #/It characterized by comprising: a semiconductor device having a thin oxide film M between the fourth and fifth metal silicide mirrors; It is.

A detailed explanation of the invention will be given below. It should be noted that the examples are merely illustrative, and the invention may be modified without departing from the spirit of the present invention.
) It goes without saying that there is nothing that can be done to change or improve it.

FIG. 1 shows an embodiment of the present invention, and in the figure, 1
00 is a P-type semiconductor substrate (first semiconductor layer), 101 is P
102 is a high-concentration N-type semiconductor epimexial layer, 103 is an N-type semiconductor well (second semiconductor layer), and 104a and 104b are P-type semicircular layers (second and sixth semiconductor layers). ), 105a, 105b
, 105c, and 105d are high-density ON-type semiconductor layers (m9.5th, 7th, and 8th semiconductor layers), 1lla, respectively.
, Lllb u gate layer, 112a, 112b.

112c, 112d, 1L2e, H2f
, 112g indicate the metal silicide films (3rd, 1st, 2nd, 4th, 5th, 6th, and 7th section 1), respectively.

However, when this metal silicide is used, it has the characteristic of exhibiting a Schottky junction t% for an N-type semiconductor and an ohmic junction for a P-type semiconductor. For example, Pt3i
(Platinum silicide) is barrier height or N-type silicon #-
Since it is 0.85 eV for a conductor and 0.25 eV for a P-type silicon semiconductor, the above-mentioned characteristics are satisfied.

Therefore, in FIG. 1, the source e drain of the 2MO8FET is connected to the upper δC1 Kanasu silicide llI! 112c, 11
By forming 2b, an L-Lischottky PMO8FET is formed, and ohmic contact with 104a can also be made directly. A contact with the semiconductor layer 103 can be made with the metal silicide 112e via the RI high concentration N-type conductor m 105b. Furthermore, metal silicides 112f and 112g are used as gate direct contacts.
By forming the source and drain in a self-contained manner, low gate resistance and barrier shielding can be achieved. The first attack,
Emitter electrode of vertical npn bipolar transistor t!
112a, the base electrode is 1121), the collector electrode is 112c, and the source electrode of 2MO8FET is 112c.
, the gate electrode is 1t2f, the drain electrode is 112b, and the back gate electrode is 112c"C".

Here, since the electrode 112c is shared with the collector electrode of the npn transistor and the drain electrode of the 2MO8FET,
The area occupied can be reduced. In addition, shot thousand PMO8F
Since E'rk is used, the emitter of the parasitic lateral WpnP) transistor is not formed compared to the conventional structure shown in FIG.
There is no need to separate the pn bipolar transistor and the 2MO8FET, allowing for higher density.

In addition, in the beautiful example shown in Fig. 1, P MOS F'ET
.

Although an implementation with 8MO8FETs and bipolar transistor hardware is shown, it is also possible to fabricate the F semiconductor device with bipolar transistors and 2MO8ITs.

(@Light effect) As explained above, if the present invention is implemented, bipolar transistors and MOSFETs can be structurally combined in a small occupied area.Furthermore, since there is no rattling problem, power consumption is low and high load is achieved. This has the effect of increasing the density of *m circuits with driving capacity.

[Brief explanation of the drawing]

Figure 1 shows an embodiment of the composite semiconductor device of the present invention, and Figure 2 shows the remains of a conventional composite semiconductor device.
Bipolar transistor, PMO8FET, NMO
8IT is shown. FIG. 3 is a circuit diagram of a conventional composite semiconductor device, and FIG. 4 shows a cross-sectional fabrication resulting from the second problem of structural merging. 100°...P-type-P conductor substrate 101...P-type semiconductor shrimp layer 102... ...... Flattened N-type semiconductor buried layer 103 ......
・N-type child conductor quell 104a, 104b...
P-type semiconductors 105a-105d... High concentration N-type semiconductor layers 111JL, 1llb... Gates Jl-1128-112g... Gold camphor silicide layer (*polar layer) Qn・・・・・・・・・・・・
-...npn bipolar transistor MP...
・・・・・・・・・P-channel MO8PET patent applicant Japan'#L Telephone Public Corporation Figure 1 2F! 2t Figure 3 Figure 4

Claims (3)

[Claims] (1) A first semiconductor layer forming a semiconductor substrate of a first conductivity type, and a well region of a second conductivity type provided in a partial region of the main surface of the first semiconductor layer. Second to do
a third semiconductor layer of the first conductivity type formed in a part of the second semiconductor layer and sufficiently shallower than the depth of the second semiconductor layer; a highly concentrated fourth semiconductor layer of a second conductivity type formed in a part of the semiconductor layer; and a first conductivity type extending from the third semiconductor layer region to the second semiconductor layer region A first metal silicide film having a Schottky junction with the type and forming an ohmic contact with the second conductivity type, and the first metal silicide film separated from the first metal silicide film by a predetermined distance. a second metal silicide film formed in the second semiconductor layer region, the second metal silicide film being the same as the first metal silicide film, and a thin oxide film formed between the first and second metal silicide films; 1 gate, a highly concentrated fifth semiconductor layer of a second conductivity type formed under the second metal silicide film, and a fifth semiconductor layer formed on the fourth semiconductor layer, and a third metal silicide film similar to the first metal silicide film;
, a third electrode. (2) A second semiconductor layer is placed on the bottom of the second semiconductor layer of the second conductivity type.
2. The composite semiconductor device according to claim 1, wherein a high concentration semiconductor layer of a conductivity type of is embedded. (3) A first semiconductor layer forming a semiconductor substrate of a first conductivity type, and a well region provided in a partial region of the main surface of the first semiconductor layer and having a second conductivity type. Second to do
a third semiconductor layer of the first conductivity type formed in a part of the second semiconductor layer and sufficiently shallower than the depth of the second semiconductor layer, and the third semiconductor layer a highly concentrated fourth semiconductor layer of a second conductivity type formed in a part of the semiconductor layer; A first metal silicide film having a Schottky junction for the conductivity type and forming an ohmic contact for the second conductivity type; a second metal silicide film formed in the second semiconductor layer region, the same as the first metal silicide film, and a thin oxide film formed between the first and second metal silicide films. a first gate, a highly concentrated fifth semiconductor layer of a second conductivity type formed under a portion of the second metal silicide film, and a fifth semiconductor layer formed on the fourth semiconductor layer; and a third metal silicide film similar to the first metal silicide film, the semiconductor device having the first, second, and third metal silicide films as first, second, and third electrodes, respectively. and a sixth semiconductor layer of the first conductivity type formed in a partial region of the main surface of the first semiconductor layer, and a sixth semiconductor layer formed at a predetermined distance from the sixth semiconductor layer region. Schottky junctions are provided on the seventh and eighth semiconductor layers of the second conductivity type, respectively, and Schottky junctions are provided on the seventh and eighth semiconductor layers of the second conductivity type. For the conductivity type, the fourth and fifth
A composite semiconductor device comprising: a metal silicide film; and a gate having a thin oxide film between the fourth and fifth metal silicide films.