JPS62104068A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS62104068A JPS62104068A JP24553985A JP24553985A JPS62104068A JP S62104068 A JPS62104068 A JP S62104068A JP 24553985 A JP24553985 A JP 24553985A JP 24553985 A JP24553985 A JP 24553985A JP S62104068 A JPS62104068 A JP S62104068A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- semiconductor
- integrated circuit
- semiconductor region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000002955 isolation Methods 0.000 claims description 6
- 239000012535 impurity Substances 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特に、個別パワー
トランジスタと同等の特性を有するパワートランジスタ
を内蔵するモノリシック集積回路装置に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a monolithic integrated circuit device incorporating a power transistor having characteristics equivalent to individual power transistors.
従来より大電力高速半導体装置としてパワーＭＯ８形電
界効果トランジスタ（以下「パワーＭＯＳＦＥＴＪとい
う）があるが、このパワーＭＯＳＦＥＴをモノリシック
に集積回路に組み込んだ索子として第２図に示す構造の
ものが提案されている。第２図において、１はｐ形半導
体基板、２はｎ形エピタキシャル成長層、３はｐ形分離
領域、４はｎ形高不純物濃度埋込み層、５はｎ形ドレイ
ン領域、６はｐ形ベース領域、７はｎ形ソース領域、８
はゲート電極、９はゲート酸化膜、１０はソース電極、
１１はドレイン電極、１２はシリコン酸化膜である。Conventionally, there has been a power MO8 type field effect transistor (hereinafter referred to as "power MOSFETJ") as a high-power, high-speed semiconductor device, but a structure shown in Figure 2 has been proposed as a module in which this power MOSFET is monolithically integrated into an integrated circuit. In Fig. 2, 1 is a p-type semiconductor substrate, 2 is an n-type epitaxial growth layer, 3 is a p-type isolation region, 4 is an n-type buried layer with high impurity concentration, 5 is an n-type drain region, and 6 is a p-type base region, 7 is n-type source region, 8
is a gate electrode, 9 is a gate oxide film, 10 is a source electrode,
11 is a drain electrode, and 12 is a silicon oxide film.
上述したパワーＭＯＳ Ｆ ＥＴは、ゲート電極８に電
圧を印加することによりｐ形ベース領域６内のゲート電
極８直下の部分にｎ形反転チャネル層１３を形成し、ソ
ース、ドレイン間に電圧を印加し、ソース、ドレイン間
に電流を流して動作するものである。The above-mentioned power MOS FET forms an n-type inverted channel layer 13 in a portion directly below the gate electrode 8 in the p-type base region 6 by applying a voltage to the gate electrode 8, and applies a voltage between the source and drain. However, it operates by passing a current between the source and drain.
しかしながら、従来のモノリシック化したパワーＭＯＳ
Ｆ ＥＴのドレイン電極１１はチップ上面から取り出
す構造となっている。このため、電子の流れとしては、
ソース電極１０からチャネル層１３を通ってｎ形エピタ
キシャル成長層２へ流れ、さらにｎ形高不純物濃度埋込
み層４を通り、続いてｎ形ドレイン領域５を通ってドレ
イン電極１１へ流れる。このように長い径路を流れるの
で、そのドレイン抵抗は大きくなる。However, conventional monolithic power MOS
The drain electrode 11 of the FET is taken out from the top surface of the chip. Therefore, the flow of electrons is
It flows from the source electrode 10 through the channel layer 13 to the n-type epitaxial growth layer 2, further through the n-type high impurity concentration buried layer 4, and then through the n-type drain region 5 to the drain electrode 11. Since it flows through such a long path, its drain resistance increases.
また、個別のパワーＭＯＳ Ｆ ＥＴの場合、ドレイン
電極はチップの裏面に設けられているが、従来のモノリ
シック化したパワーＭＯＳ Ｆ ＥＴは、表面側にドレ
イン電極１１を取る構造となっており、しかも大きな電
流を流すため、大きい面積を必要とし、このため大きな
チップ面積を必要とする。このように、従来のパワーＭ
Ｏ３ＦＥＴは、パワーＭＯ３ＦＥＴの特徴である大電流
を得るのに不都合な構造となっている。Furthermore, in the case of individual power MOS FETs, the drain electrode is provided on the back side of the chip, but conventional monolithic power MOS FETs have a structure in which the drain electrode 11 is provided on the front side. Since a large current flows, a large area is required, and therefore a large chip area is required. In this way, the conventional power M
The O3FET has a structure that is inconvenient for obtaining a large current, which is a characteristic of the power MO3FET.
本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、個別素子とほぼ同等の特性が得
られるパワーＭＯ３ＦＥＴのモノリシック集積回路を提
供することにある。The present invention has been made in view of these points, and its purpose is to provide a monolithic integrated circuit of a power MO3FET that can obtain characteristics almost equivalent to those of individual elements.
このような目的を達成するために本発明は、第１導電形
を有する半導体基板と、この半導体基板の主面の所定の
部分に形成された第２導電形を有する第１の半導体領域
と、この第１の半導体領域内に形成された第１導電形を
有する第２の半導体領域と、半導体基板の主面上に第１
および第２の半導体領域を埋め込むように形成された第
１導電形を有する第３の半導体領域と、第１の半導体領
域に到達するように第３の半導体領域中に形成された第
２導電形を有する分離領域と、第１の半導体領域が形成
されていない半導体基板の主面上の第３の半導体領域中
に形成されたトランジスタとを半導体集積回路装置内に
設けるようにしたものである。In order to achieve such an object, the present invention provides a semiconductor substrate having a first conductivity type, a first semiconductor region having a second conductivity type formed in a predetermined portion of the main surface of the semiconductor substrate, A second semiconductor region having a first conductivity type formed within the first semiconductor region, and a first semiconductor region formed on the main surface of the semiconductor substrate.
and a third semiconductor region having a first conductivity type formed so as to embed the second semiconductor region, and a second conductivity type formed in the third semiconductor region so as to reach the first semiconductor region. A semiconductor integrated circuit device is provided with an isolation region having a second semiconductor region and a transistor formed in a third semiconductor region on the main surface of the semiconductor substrate where the first semiconductor region is not formed.
本発明においては、チップ裏面がパワーＭＯ３ＦＥＴの
ドレイン電極となり、電子はチップ表面から裏面へ縦方
向に流れ、ドレイン抵抗は小さくなる。In the present invention, the back surface of the chip becomes the drain electrode of the power MO3FET, electrons flow vertically from the front surface of the chip to the back surface, and the drain resistance becomes small.
本発明に係わる半導体集積回路装置の一実施例を第１図
により説明する。第１図（ａｌ〜（ｄ）は本装置の主要
な製造工程を示す断面図であり、第１図（ｄ＋が完成さ
れた状態を示す断面図である。第１図において第２図と
同一部分又は相当部分には同一符号が付しである。An embodiment of a semiconductor integrated circuit device according to the present invention will be described with reference to FIG. Figures 1 (al to d) are cross-sectional views showing the main manufacturing steps of this device, and Figure 1 (d+) is a cross-sectional view showing the completed state. Figure 1 is the same as Figure 2. Parts or equivalent parts are given the same reference numerals.
まず、第１図（ａｌに示すように、第１導電形であるｎ
形の半導体基板１４の主面のパワーＭＯ３ＦＥＴを形成
する部分以外の領域に第２導電形であるｐ形の第１の半
導体領域である半導体領域１５を形成する。続いてｐ形
半導体領域１５内の所定の部分にフローティングコレク
タとなる第２の半導体領域としてのｎ形高不純物濃度埋
込み層４を形成する。First, as shown in FIG. 1 (al), the first conductivity type is n.
A semiconductor region 15, which is a first semiconductor region of p-type, which is a second conductivity type, is formed in a region other than the portion where the power MO3FET is formed on the main surface of the shaped semiconductor substrate 14. Subsequently, an n-type high impurity concentration buried layer 4 is formed in a predetermined portion of the p-type semiconductor region 15 as a second semiconductor region that will become a floating collector.
続いて、第１図（ｂ）に示すように、ｐ形半導体領域１
５およびｎ形高不純物濃度埋込み層４を埋め込むように
、エピタキシャル成長にて第３の半導体領域としてのｎ
形エピタキシャル成長層２を形成した後、ｎ形エピタキ
シャル成長層２の表面からｐ形半導体領域１５に到達す
るようにｐ形の分離領域３を形成し、ｎ形の島領域２ａ
を形成する。Subsequently, as shown in FIG. 1(b), a p-type semiconductor region 1 is formed.
5 and n-type as the third semiconductor region by epitaxial growth so as to bury the n-type high impurity concentration buried layer 4.
After forming the type epitaxial growth layer 2, a p-type isolation region 3 is formed so as to reach the p-type semiconductor region 15 from the surface of the n-type epitaxial growth layer 2, and an n-type island region 2a is formed.
form.
続いて、第１図（Ｃ１に示すように、ｐ形半導体領域１
５が形成されていない部分上のｎ形エピタキシャル成長
層２内にパワーＭＯＳ Ｆ ＥＴのｐ形ベース領域６お
よびｎ形ソース領域７を形成し、他の島領域２ａには、
ｎｐｎトランジスタあるいは抵抗等を集積回路を構成す
る他の素子として形成する。Subsequently, as shown in FIG. 1 (C1), the p-type semiconductor region 1
A p-type base region 6 and an n-type source region 7 of the power MOS FET are formed in the n-type epitaxial growth layer 2 on the part where 5 is not formed, and in the other island region 2a,
NPN transistors, resistors, etc. are formed as other elements constituting the integrated circuit.
続いて、第１図（ｄ）に示すように、パワーＭＯ３ＦＥ
Ｔのソース電極１０．ゲート電極８．ドレイン電極１１
および他の構成素子の電極をそれぞれ被着して、目的と
するモノリシック集積回路が得られる。Next, as shown in FIG. 1(d), the power MO3FE
T source electrode 10. Gate electrode 8. drain electrode 11
and the electrodes of other components, respectively, to obtain the desired monolithic integrated circuit.
このような構造の半導体集積回路におけるパワーＭＯＳ
Ｆ ＥＴは、個別のパ”７−ＭＯＳＦＥＴと同様に、
ドレイン電極１１が裏面に形成されており、電子はチッ
プ表面側から裏面側へ縦方向に流れるため、効率良く大
電流を得ることができる。Power MOS in a semiconductor integrated circuit with such a structure
The FET is similar to an individual 7-MOSFET.
Since the drain electrode 11 is formed on the back surface and electrons flow vertically from the front side of the chip to the back side, a large current can be obtained efficiently.
第２図に示す従来の半導体基板１は、通常、各構成素子
を電気的に分離する役目があるが、半導体基板１に電流
を流すことは殆どなく、この明域をチップ裏面側から取
らず、ｐ形半導体領域１５および分離領域３を通してチ
ップ表面から取り出しても何ら不都合は発生しない。従
って本装置は、従来のものと比べ、ｐ形半導体領域１５
を形成する工程を追加するのみで、パワーＭＯ３ＦＥＴ
以外の構成素子も特性を損なうことなく形成することが
できる。すなわち、本装置は、ｐ形半導体領域１５を形
成する工程を追加するのみで特性の良好なパワーＭＯ３
ＦＥＴのモノリシック集積回路装置を得ることができる
。The conventional semiconductor substrate 1 shown in FIG. 2 usually has the role of electrically isolating each component, but almost no current is passed through the semiconductor substrate 1, and this bright area is not removed from the back side of the chip. , the p-type semiconductor region 15 and the isolation region 3 are taken out from the chip surface without causing any inconvenience. Therefore, compared to the conventional device, this device has a p-type semiconductor region 15
By simply adding a step to form a power MO3FET,
Other constituent elements can also be formed without impairing the characteristics. In other words, this device can produce a power MO3 with good characteristics by only adding the step of forming the p-type semiconductor region 15.
A monolithic integrated circuit device of FETs can be obtained.
なお、上記実施例では、ｎチャネルパワーＭＯ５ＦＥＴ
を組み込んだ場合について述べたが、ｐチャネルパワー
ＭＯ３ＦＥＴあるいはｎ形半導体基板１４をコレクタと
するバイポーラパワートランジスタを組み込んでも同じ
効果が得られる。Note that in the above embodiment, the n-channel power MO5FET
Although the case has been described in which a p-channel power MO3FET or a bipolar power transistor whose collector is the n-type semiconductor substrate 14 is incorporated, the same effect can be obtained.
以上説明したように本発明は、第３の半導体領域中に形
成されたトランジスタの構造をチップ表面から裏面基板
側へ電子を流す構造とすることにより、効率良く電流を
流すことができ、かつ、モノリシック集積回路を構成す
る他の素子も電気的特性を損なうことな（形成できる効
果がある。As explained above, the present invention makes it possible to efficiently flow current by making the structure of the transistor formed in the third semiconductor region such that electrons flow from the chip surface to the rear substrate side, and Other elements constituting the monolithic integrated circuit can also be formed without impairing their electrical characteristics.
第１図は本発明に係わる半導体集積回路装置の一実施例
の主要な製造工程を示す断面図、第２図は従来の半導体
集積回路装置を示す断面図である。
２・・・・ｎ形エピタキシャル成長層、２ａ・・・・ｎ
形の島領域、３・・・・分離領域、４・・・・ｎ形高不
純物濃度埋込み層、６・・・・ｐ形ベース領域、７・・
・・ｎ形ソース領域、８・・・・ゲート電極、９・・・
・ゲート酸化膜、１０・・・・ソース電極、１１・・・
・ドレイン電極、１２・・・・シリコン酸化膜、１４・
・・・ｎ形半導体基板、１５・・・・ｐ形半導体領域。FIG. 1 is a sectional view showing the main manufacturing steps of an embodiment of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a sectional view showing a conventional semiconductor integrated circuit device. 2...n-type epitaxial growth layer, 2a...n
shaped island region, 3... isolation region, 4... n-type buried layer with high impurity concentration, 6... p-type base region, 7...
... n-type source region, 8 ... gate electrode, 9 ...
・Gate oxide film, 10... Source electrode, 11...
・Drain electrode, 12...Silicon oxide film, 14.
. . . n-type semiconductor substrate, 15 . . . p-type semiconductor region.
Claims (2)
板の主面の所定の部分に形成された第２導電形を有する
第１の半導体領域と、この第１の半導体領域内に形成さ
れた１個以上の互いに電気的に分離された第１導電形を
有する第２の半導体領域と、前記半導体基板の主面上に
前記第１および第２の半導体領域を埋め込むように形成
された第１導電形を有する第３の半導体領域と、前記第
１の半導体領域に到達するように前記第３の半導体領域
中に形成された第２導電形を有する分離領域と、前記第
１の半導体領域が形成されていない前記半導体基板の主
面上の前記第３の半導体領域中に形成されたトランジス
タとを備えたことを特徴とする半導体集積回路装置。(1) A semiconductor substrate having a first conductivity type, a first semiconductor region having a second conductivity type formed in a predetermined portion of the main surface of this semiconductor substrate, and a first semiconductor region having a second conductivity type formed in the first semiconductor region. one or more second semiconductor regions having a first conductivity type electrically isolated from each other; and a second semiconductor region formed on the main surface of the semiconductor substrate so as to embed the first and second semiconductor regions. a third semiconductor region having one conductivity type; an isolation region having a second conductivity type formed in the third semiconductor region so as to reach the first semiconductor region; and the first semiconductor region. and a transistor formed in the third semiconductor region on the main surface of the semiconductor substrate in which the semiconductor substrate is not formed.
、半導体基板をドレインとした縦形ＭＯＳトランジスタ
であることを特徴とする特許請求の範囲第１項記載の半
導体集積回路装置。(2) The semiconductor integrated circuit device according to claim 1, wherein the transistor formed in the third semiconductor region is a vertical MOS transistor whose drain is the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24553985A JPS62104068A (en) | 1985-10-30 | 1985-10-30 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24553985A JPS62104068A (en) | 1985-10-30 | 1985-10-30 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62104068A true JPS62104068A (en) | 1987-05-14 |
Family
ID=17135202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24553985A Pending JPS62104068A (en) | 1985-10-30 | 1985-10-30 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62104068A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63202971A (en) * | 1987-02-19 | 1988-08-22 | Toshiba Corp | Semiconductor device |
| JPS63299265A (en) * | 1987-05-29 | 1988-12-06 | Nissan Motor Co Ltd | Semiconductor device |
| JP2008270367A (en) * | 2007-04-17 | 2008-11-06 | Denso Corp | Semiconductor device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53135284A (en) * | 1977-04-30 | 1978-11-25 | Nec Corp | Production of field effect transistor |
| JPS54148388A (en) * | 1978-05-12 | 1979-11-20 | Nec Corp | Semiconductor integrated circuit device |
| JPS5563876A (en) * | 1978-11-08 | 1980-05-14 | Sony Corp | Field-effect semiconductor device |
| JPS55165669A (en) * | 1979-06-11 | 1980-12-24 | Hitachi Ltd | Bipolar-mos device |
| JPS57162359A (en) * | 1981-03-30 | 1982-10-06 | Toshiba Corp | Semiconductor device |
| JPS6080267A (en) * | 1983-10-07 | 1985-05-08 | Toshiba Corp | Semiconductor ic device and manufacture thereof |
-
1985
- 1985-10-30 JP JP24553985A patent/JPS62104068A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53135284A (en) * | 1977-04-30 | 1978-11-25 | Nec Corp | Production of field effect transistor |
| JPS54148388A (en) * | 1978-05-12 | 1979-11-20 | Nec Corp | Semiconductor integrated circuit device |
| JPS5563876A (en) * | 1978-11-08 | 1980-05-14 | Sony Corp | Field-effect semiconductor device |
| JPS55165669A (en) * | 1979-06-11 | 1980-12-24 | Hitachi Ltd | Bipolar-mos device |
| JPS57162359A (en) * | 1981-03-30 | 1982-10-06 | Toshiba Corp | Semiconductor device |
| JPS6080267A (en) * | 1983-10-07 | 1985-05-08 | Toshiba Corp | Semiconductor ic device and manufacture thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63202971A (en) * | 1987-02-19 | 1988-08-22 | Toshiba Corp | Semiconductor device |
| JPS63299265A (en) * | 1987-05-29 | 1988-12-06 | Nissan Motor Co Ltd | Semiconductor device |
| JP2008270367A (en) * | 2007-04-17 | 2008-11-06 | Denso Corp | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4066917A (en) | Circuit combining bipolar transistor and JFET's to produce a constant voltage characteristic | |
| JPS6153861B2 (en) | ||
| JPH0230588B2 (en) | ||
| JPH01198076A (en) | Semiconductor device | |
| JPH0865063A (en) | Semiconductor integrated circuit | |
| JP3249891B2 (en) | Semiconductor device and method of using the same | |
| JPS62104068A (en) | Semiconductor integrated circuit device | |
| JPH0656890B2 (en) | Vertical conductivity type MOS-FET | |
| JPH03276757A (en) | Semiconductor device | |
| JPH05283622A (en) | Semiconductor device | |
| JPS61281545A (en) | Bipolar-cmos semiconductor device | |
| JPS6228586B2 (en) | ||
| JPS6058633A (en) | Semiconductor integrated circuit device | |
| JPS6060753A (en) | Semiconductor device | |
| JPS6046064A (en) | Semiconductor device | |
| JP2678081B2 (en) | Semiconductor integrated circuit device | |
| JPH03145163A (en) | Thyristor | |
| JP2926785B2 (en) | Semiconductor device | |
| JPH08172100A (en) | Semiconductor device | |
| JPS59144168A (en) | Bipolar mos semiconductor device and manufacture thereof | |
| JPS6334949A (en) | Semiconductor device | |
| JPH0413861B2 (en) | ||
| JPH0669433A (en) | Semiconductor device | |
| JPS6156431A (en) | High-voltage semiconductor integrated circuit | |
| JPH02142179A (en) | Semiconductor integrated circuit device |