JPS6058633A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To ensure coexistence of an active element for small signal and a high tension resisting active element by providing a groove on one end of a semiconductor substrate for the high tension resisting active element, providing three regions for the active element for small signal on the adjacent substrate, growing an epitaxial layer on all the surface including these above by way of an insulation layer and dividing each separated region. CONSTITUTION:On one end of a p type Si substrate 10, an aperture 12 wherein the bottom is tapered is provided by anisotropic etching, the region a1 is used for a high tension resisting active element consisting of bipolar transistors and the adjacent regions a2-a4 are each used for an active element consisting of bipolar transistors for small signal. Then, an SiO2 insulation layer 22 is provided by O2 ion 20 implantation on all the surface and an arsenic layer 30 on the region a1 and a phosphorus layer 40 on the regions a2-a4 are provided. Later, an Si layer is grown epitaxially on all the surface, the regions a1-a4 separate in an island state with a p<+> type separation region 60, impurity in the layers 30 and 40 is heat-treated to be diffused upwards and each region a1-a4 is changed to n<-> type, n type, etc.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is particularly effective when applied to semiconductor technology and also to semiconductor integrated circuit devices. BACKGROUND ART The present inventor has developed the following technology regarding semiconductor technology, particularly technology for forming elements of bipolar semiconductor integrated circuits.

That is, a normal small signal active element and a high voltage active element are formed together.

However, with this technology, it is difficult to reliably electrically separate the region where the small signal active element is formed and the region where the high voltage active element is formed, and at the same time, the operation of the small signal active element is difficult. The inventors have found that the problem arises that it is also difficult to digitize.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor technology that allows a small signal active element and a high voltage active element to coexist in a state where they are reliably electrically separated.

The present invention also provides a semiconductor technology that can increase the operating speed of a small-signal active element formed together with a high-voltage active element.

Furthermore, the present invention provides semiconductor technology that enables the formation of even higher-speed Schottky diode-equipped transistors as small-signal active elements, and also provides semiconductor technology that allows the withstand voltage of high-voltage active elements to be further increased. It's about doing.

In addition, along with high-voltage active elements, C3TL (complementary Schottky transistor logic)
Another object of the present invention is to provide a semiconductor technology that can form IIL (Integrated Injection Logic).

The above-mentioned and other objects and novel features of the present invention will become clear from the description of Book #I and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, by using a semiconductor integrated circuit device in which a high voltage active element and a small signal active element coexist, it is possible to increase the voltage resistance of the high voltage active element and reduce the parasitic capacitance of the /J% signal active element. The objective is to speed up the operation.

[Embodiments] Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In addition, the same or corresponding parts are indicated by the same reference numerals in the drawings.

FIG. 1 to FIG. 10 sequentially illustrate one embodiment of the process of forming a semiconductor integrated circuit device according to the present invention.

First, the outline of the semiconductor integrated circuit device formed by the steps shown in FIGS. 1 to 10 will be explained as follows.

The semiconductor integrated circuit device 100 formed by the steps shown in FIGS. 1-10 is a bipolar type semiconductor integrated circuit device, and the elements formed therein are mainly bipolar transistors. Also, a bipolar transistor Q1 as a high voltage active element and a bipolar transistor Q2 as a small signal active element. Q3. Q4. Q5. Q6 are respectively formed on the same semiconductor substrate 10.

As shown in FIG. 11, the small signal active element is C
Configures digital logic circuits such as 3TL and IIL. Further, high voltage active elements are used, for example, to generate driving voltage for fluorescent display tubes. Furthermore, the bipolar transistors Q2 and Q3 as active elements for small signals have their electrodes
Specifically, a Schottky barrier diode is provided to connect the base and collector, which allows the transistors Q2 and Q3 to operate at high speed without saturating them.

Next, each process will be explained.

First, as shown in FIG. 1, a partially deeply dug region, that is, a well 12, is formed in a P-type silicon semiconductor substrate IO having a low impurity concentration. The well 12 is formed by anisotropic etching using an etching solution such as potassium hydroxide. As a result, etching progresses along the cleavage plane of the silicon substrate 10, and a well 12 is formed at an angle of about 60 degrees with respect to the surface of the substrate 100. Area a where this well 12 is formed
1, a high voltage bipolar transistor Q1, which will be described later, is formed.

Next, as shown in FIG. 2, oxygen ions (or nitrogen ions) are implanted into the substrate 10, so-called ion implantation. As a result, oxygen ions (or nitrogen ions) 20 are implanted at a constant location from the surface of the substrate 100. Impression] The ion 20 that has faded is
It is activated after the formation process of an epitaxial layer 50, which will be described later, to form an electrically insulating chemical layer, that is, a silicon oxide layer (or silicon nitride layer) 22.

Once the ion implantation is complete, as shown in Figure 3,
Active element formation areas al, a2. N-type impurities 30 and 40 are deposited every a3° and a4. So-called deposition is performed. The n-type impurity at this time is 30.40,
Two types of materials with different diffusion coefficients are used depending on the region.

As the first n-type impurity 30, antimony, which has a small diffusion coefficient and a slow diffusion rate, is used.

This n-type impurity 30 made of antimony is selectively deposited on the region where the well 12 is formed and the region al where a high breakdown voltage bibor 2 transistor Ql, which will be described later, is formed.

As the second n-type impurity 40, phosphorus, which has a large diffusion coefficient and a fast diffusion rate, is used. This n-type impurity 40 made of phosphorus is used in a small signal bipolar transistor Q2, which will be described later. Q3. Q4. Area a2 where Q5゜Q6 is formed
．． It is selectively attached to a3+a4.

As described above, two types of n-type impurities 30 and 40
are selectively deposited in predetermined regions, an epitaxial layer 50 of n-type silicon with a low impurity concentration is formed on the semiconductor substrate 10, as shown in FIG.
form.

Thereafter, the oxygen ions (or nitrogen ions) implanted in the step shown in FIG. 2 are activated to form a chemical layer forming an electrically insulating layer. Specifically, this chemical layer is a silicon oxide (or silicon nitride) layer 22.

Further, the two types of n-type impurities 30 and 40 selectively deposited in the step shown in FIG. 3 are each diffused from the bottom of the epitaxial layer 50 toward the surface.

At this time, as shown in Figure 5, the first
The n-type impurity 30 does not rise significantly from the bottom of the well 12, but diffuses in a crawling manner to the bottom of the well 12, and is diffused in the region a1.
This serves as an n-type buried layer 32 for increasing the conductivity in the plane direction of the epitaxial layer 500.

Further, the second n-type impurity 40 having a large diffusion coefficient is contained in the region a2. a3. It diffuses in a large upward direction from the bottom of the epitaxial layer 50 at a4 toward its surface. The diffusion reaches the surface of the epitaxial layer 500. This creates a concentration gradient of n-type impurities from the bottom of the epitaxial layer 50 toward the surface. Tsumashi,
An n-type impurity diffusion region 42 whose concentration decreases from the bottom to the surface of the epitaxial layer 50 is formed. In this case, the concentration distribution state is such that the concentration at the bottom of the epitaxial layer 50 is
The concentration at the surface of the epitaxial layer 50 is controlled such that the concentration is sufficient to increase the conductivity of the epitaxial layer 50, and the concentration is suitable for forming a Schottky barrier diode, which will be described later. This control is based on the amount of impurities attached.

This can be done by changing the diffusion temperature, diffusion time, etc.

Thereafter, a separation layer 60 made of a p+ type scattered layer is formed. As a result, the area al where each element is formed.

a2. a3. Separate a4 from the lateral direction.

Subsequently, as shown in FIG. 6, an n+ type scattered layer is formed in the epitaxial layer 50 in the region a1 where the high breakdown voltage Ibora transistor Q1 is to be formed. This n++ diffusion layer 70 is formed so as to reach the n+ type buried waste 32, so that the n type diffusion layer 70 can be used as a collector connection diffusion layer of a high breakdown voltage transistor Q1, which will be described later. Function.

Note that the separation layer 60 and the n++ diffusion N7° can be formed simultaneously by thermal diffusion.

Next, as shown in FIG.
Each region al, a2. a3. A p-diffusion layer 80 is selectively formed on a4.

Furthermore, as shown in FIG. 8, each area al, a2°a3
An n+ type scattering layer 82 is selectively formed on each of ra4.

Next, the bases B of bipolar transistors Q2 and Q3
2. Metal silicide 90t- is formed in a portion spanning the B3 region and the collector C23 region.

At this time, as described above, the n-type impurity concentration in the surface portion of the epitaxial layer 500 where the metal silicide 90 is formed is a concentration suitable for forming a Schottky diode. Therefore, each of the two transistors Q2 and Q3 becomes a so-called transistor with a Schottky diode, in which a Schottky barrier diode is connected from the base to the collector.

Accordingly, as shown in FIG. 10, a high voltage npn bipolar transistor Q1 is placed in the area
2 are two npn type bipolar transistors Q2.2 with a sirot-key barrier diode, whose collectors C23 are commonly connected. Q3 is a pnp lateral bipolar transistor Q4 in region a3, and IIL is in region a4.
A semiconductor integrated circuit device 100 is obtained in which pnp type and npn type bipolar transistors Q5 and Q6 are respectively formed.

FIG. 11 shows a circuit constituted by transistors Ql to Q6 shown in FIG. 10. As shown in the figure, in the semiconductor integrated circuit device 100, digital logic circuits such as C3TL and IIL are formed together with a high voltage bipolar transistor Q1. As mentioned above, the C3TL is capable of high-speed operation due to the Nyoyoto key barrier diode. (9) IIL constitutes a logic circuit with high integration density.

In addition, in @Figure 10 and Figure 11, CI.

B1. B1 indicates the collector, base, and emitter of the high voltage bipolar transistor Q1. t, B2゜B3. B
2. B3 indicates the base and emitter of bipolar transistors Q2 and Q3 with Shirotsky barrier diodes. 023 are the two transistors Q2. The common collector of Q3 is shown. A load consisting of a transistor Q4 is connected to this common collector C23. C4, B4. B4
indicate the collector, base, and emitter of the load transistor Q4. Transistor Q2. Q3. C by Q4
3TL is configured.

Also, transistor Q5. Q6 constitutes IIL. I
NJ indicates an injector, and A indicates a logic input (base).

C61, C62, and C63 are multi-collector outputs, which are formed by the n diffusion layer 82.

Now, in the semiconductor bond circuit device 100 formed as described above, first, the buried collector layer 32 of the high voltage bipolar transistor Q1 in the region a1 is formed using antimony having a small diffusion coefficient. Therefore, the impurity concentration in the epitaxial layer 50 above the buried layer 32 can be kept relatively low.

Thereby, the depletion layer generated from the junction surface between the p-type diffusion layer 80 and the epitaxial layer 50 can be spread easily. Along with this, the well 1 formed in this area a1
2 helps spread the depletion layer #), thereby causing the region a
The bipolar transistor Ql formed in I can have a very large breakdown voltage. Further, in the region a1, an electrically insulating layer such as the silicon oxide (or silicon nitride) layer 22 described above is interposed between the epitaxial layer 50 serving as the collector region and the semiconductor substrate 1o.

As a result, the withstand voltage of the high voltage bipolar transistor Q1 is further increased significantly.

At the same time, the electrical insulating layer made of silicon oxide (or silicon nitride) also acts to reduce the parallel capacitance parasitic to the collector CI of the transistor Q1. Accordingly, the operating speed of the transistor Q1 can also be increased.

Next, a region a2. Regarding a3°C4, in this case as well, the epitaxial layer 50 serving as the electrode color gamut of collectors C2, C3°C4, base B4, etc. is separated also in the vertical direction by the silicon oxide (or silicon nitride) layer 22. Therefore, electrical isolation from the high voltage bipolar transistor Q1 is ensured, and the parasitic parallel capacitance between the epitaxial layer 50 and the semiconductor substrate 10 is reduced by pn
The size can be significantly reduced compared to the case of separation only by bonding. As a result, the operating speed of the small-signal bipolar transistors Q2 to Q6 can be significantly increased. Furthermore, the n-type impurity concentration in the surface portion of the epitaxial i50 is adjusted to a concentration suitable for forming a Schottky barrier diode using the metal silicide 90 due to upwelling and diffusion of the n-type impurity having a relatively large diffusion coefficient from below. It becomes. At the same time, since the concentration of the n-type impurity increases as it goes below the surface of the epitaxial layer 500, the electrical resistance at this portion can be lowered. As a result, it is possible to reduce the resistance that is equimetrically interposed between the Schottky barrier diode made of the metal silicide 90 and the transistors Q2sQ3, which reduces the parasitic time constants of the transistors Q2, Q3, etc. This acts to further increase its operating speed.

〔effect〕

(1) By interposing an electrically insulating layer between the epitaxial layer and the semiconductor substrate, an effect can be obtained that the operating speed of a small signal active element formed together with a high breakdown voltage active element can be increased.

(2) By forming a partially deeply dug region in the semiconductor substrate, forming a high breakdown voltage active element in this region, and forming a small signal active element in the other σ) region, a small signal active element can be formed. This has the effect that the active element and the high voltage active element can coexist in a state where they are reliably electrically separated.

(3) By forming a diffusion region rising up from the bottom of the epitaxial layer and being diffused, it is possible to form an even faster Schottky bipolar transistor as a small signal active element.

(4) By interposing an electrically insulating layer between the epitaxial layer and the semiconductor substrate, it is possible to further increase the breakdown voltage of the high breakdown voltage active element.

The above (1) to (4) provide a synergistic effect in that a C3TL or IIL can be formed together with a high breakdown voltage active element.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, the active element may be a field effect transistor. 'Also, in this embodiment, B2°B3. Although only phosphorus is deposited in the region B4, both phosphorus and antimony may be deposited in each region. In this case, since antimony has a slow diffusion rate, an n buried layer is formed between the substrate and the epitaxial layer, and the transistors Q2 and C3
The collector series resistance can be further reduced and its operating speed can be further increased. Furthermore, if an n diffusion layer reaching the buried layer is formed immediately below the collector of the transistor Q 2 t Q a at the same time as the n diffusion 70 for connecting the collector of the high voltage transistor is formed, the effect will be even more remarkable.

[Application field]

The above explanation has mainly been about the application of the invention made by the present inventor to the technology for forming elements of digital logic circuits, which is the background field of application, but the invention is not limited thereto. It can also be applied to device formation technology, etc. The present invention is applicable to at least structures in which high-voltage active elements and small-signal active elements are formed together.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the initial stage of the process for forming a semiconductor integrated circuit device according to the present invention, FIG. 2 is a cross-sectional view showing the oxygen ion or nitrogen ion implantation process, and FIG. 3 is the impurity deposition process. 4 is a sectional view showing the state of epitaxial layer formation, FIG. 5 is a sectional view showing the state of separation layer diffusion, and FIG. 6 is a sectional view showing the state of forming a diffusion layer for collector connection. , FIG. 7 is a cross-sectional view showing a state in which a p-type diffusion layer is formed for forming a bipolar transistor, FIG. 8 is a cross-sectional view showing a state in which an n + type diffused layer is formed for forming a bipolar transistor, and FIG. The figure is a cross-sectional view showing the state in which metal silicide has been formed to form a Schottky barrier diode, Figure 10 is a cross-sectional view showing the state at the final process stage, and Figure 11 shows the state of the element shown in Figure 10. It is a circuit diagram. 10...p-type silicon semiconductor substrate, 12...partially deeply dug region (well), 20...oxygen ion (-1, nitrogen ion), 22...electrical insulation R (
Chemical layer (silicon oxide or silicon nitride), 3
0...nff1 impurity (antimony), 40...n
type impurity (phosphorus), 32... n-type impurity diffusion layer (buried layer), 42... n-type impurity diffusion region, 50... n-
type epitaxial layer, 60...p++ separation layer, 70.
...n+ type collector connection diffusion layer, 80...p type diffusion layer, 82...n+ type scattering layer 90...metal silicide, 100...semiconductor integrated circuit device, al...high Formation region of voltage-resistant active element (bipolar transistor), B
2...Small signal active element (bipolar transistor)
Formation area (Schottky transistor formation area)
, B3...Formation region of small signal active element (horizontal bipolar transistor), B4...Small signal active element (I
Bipolar transistor for IL) formation region, C1...
・High voltage bipolar transistor collector B1...
Pace of high voltage bipolar transistor, El... Emitter of high voltage bipolar transistor, C23...
Common collector of dual Schottky transistors,
B2. B3...Pace of Schottky barrier transistor, B2, B3...Emitter of Schottky barrier transistor, C3TL...Complementary Schottky transistor logic, IIL...Integrated injection logic, IN
J...IIL injector, A...IIL logic input (pace).

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device in which a J-signal active element and a high breakdown voltage active element are formed coexisting in an epitaxial layer formed on the semiconductor integrated circuit device, wherein the epitaxial layer A semiconductor integrated circuit device characterized in that an electrically insulating layer is interposed between the semiconductor substrate and the semiconductor substrate. 2. A patent characterized in that a partially deeply dug region is formed in the semiconductor substrate, the high voltage active element is formed in this region, and a small signal active element is formed in another region. A semiconductor integrated circuit device according to claim 1. 3. Claim 1, characterized in that an electrical insulating layer is interposed between at least a region of the epitaxial layer where an element is formed and the semiconductor substrate, and the electrical insulating layer is made of a chemical conversion layer. Or the semiconductor integrated circuit device according to item 2. 4. The semiconductor substrate and the epitaxial layer are each made of crystalline silicon, and a layer of silicon oxide or silicon nitride is interposed between at least a region of the epitaxial layer where an element is formed and the semiconductor substrate. A semiconductor integrated circuit device according to any one of claims 1 to 3. 5. In the region where the small signal active element is formed, an impurity for increasing conductivity is diffused into the epitaxial layer, and the impurity diffusion concentration decreases from the bottom to the surface of the epitaxial layer. A semiconductor integrated circuit device according to any one of claims 1 to 4, characterized in that: 6. In the region where the bipolar transistor is formed as the small signal active element, a Schottky barrier diode is formed on the surface of the epitaxial layer that spans the electrode of the Ibora transistor. 7. A semiconductor integrated circuit device according to any one of claims 1 to 5. 7. In a region where a bipolar transistor is formed as the small signal active element, the bipolar transistor Metal silicide is formed on the surface of the epitaxial layer that spans the X pole of the epitaxial layer, while an impurity to increase the conductivity is diffused into the epitaxial layer, and the diffusion concentration of this impurity becomes higher than that of the epitaxial layer. The concentration decreases from the bottom to the surface of the metal silicide, and the concentration at the surface is such that the metal silicide can form a Schottky barrier diode. 8. The semiconductor integrated circuit device according to any one of the preceding paragraphs. 8. A layer for increasing the conductivity of the epitaxial layer is formed in the region where the small signal active element is formed and the region where the high voltage active element is formed, respectively. The impurity is diffused from the lower part of the epitaxial layer toward the surface, and the diffusion coefficient of the diffused impurity in the region where the small signal active element is formed is changed from that in the region where the high breakdown voltage active element is formed. The semiconductor integrated circuit device according to any one of claims 1 to 7, characterized in that the diffusion coefficient of diffusion impurities is also increased.