JPS58210659A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To change the emitter density into a density higher than the base density, increase the current amplification factor, and minimize the excess accumulated carrier by a method wherein the higher density emitter region is provided just below a base region and on the surface of an N type epitaxial layer, and the inactive region is covered with an oxide film. CONSTITUTION:A thin epitaxial layer determined by the thickness of the second epitaxial layer 16 is formed at an I<2>L region, and a thick epitaxial layer determined by the sum of thicknesses of the first epitaxial layer 13 and the second epitaxial layer 16 is formed at the normal bipolar transistor region. Therefore, the bi-polar transistor can be formed at a high withstand voltage, and the I<2>L element can obtain a high current amplification factor because the emitter high density region 14 contacts the base 20. Besides, the current amplification factor can be increased by providing the high emitter region 14 under the base region 20 in the I<2>L, and the region except for the active region is covered with the oxide film 15, accordingly the generation of the excess accumulated carrier can be restrained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and in particular to a semiconductor device in which an integrated injection logic element (12L) as a high-speed logic element and a normal bipolar transistor as a high-voltage element are integrated on the same chip. Regarding the manufacturing method.

I”L (Integrated Injecti)
on Logic) consists of an inverter consisting of a so-called reverse structure vertical transistor in which the emitter and collector are arranged in the opposite way from that of a normal bipolar transistor, and a lateral transistor complementary to the vertical transistor whose collector is the base of this inverter. A logic element having an injector.

This ILL is attracting attention because it has low power consumption, high-speed operation, and a structure suitable for high integration, and it is also known that it can be easily integrated on the same chip at the same time as other bipolar transistors. It is being

A structure in which an IIL and a normal bipolar transistor are integrated according to the prior art is shown in FIG. That is, on the surface of the P-type St substrate 1, n+-type buried layers 2 and 2' containing, for example, 8i at a high concentration are formed by diffusion. Next, an n-type layer 3 with a thickness of about 3 to 8 μm is grown on this substrate, and then boron is diffused to form a p-type layer 4 for device isolation. In order to obtain a ground potential, a deep and highly concentrated n-type layer 5 reaching the n-type buried layer 1-2 is formed by diffusion in a region of the n-type layer 3 which is separated from each other in a region where the trenches 2L are to be formed. After that, a p-type layer 6', which becomes the base of the inverter, and a p-type layer 6', which becomes the emitter of the injector, are simultaneously formed on the l1lL side, and a p-type layer 6'', which becomes the base, on the normal bipolar transistor side.And,
The p-type layer 6 has an n-type layer 7 that becomes the collector of the inverter, the p-type layer 6 has an emitter 7', and the n-type layer 1fjJ3 has an n-type layer 7 for taking out the collector electrode. 7” are simultaneously diffused and formed. Thereafter, the required electrode wiring is completed through steps such as aluminum vapor deposition and patterning.

As is clear from FIG. 1, the n-type layer 3 serves as the emitter region of the inverted structure vertical transistor in the 12L portion, and serves as the collector region in the normal bipolar transistor portion. In this case, in order to increase the current amplification factor of the reverse structure vertical transistor in the IIL section, it is desirable that the impurity concentration of the n-type layer 3 is as high as possible. However, in order to obtain a sufficient collector-emitter breakdown voltage on the bipolar transistor side, it is better to have a lower impurity concentration. Furthermore, the thickness of the n-type layer 3 is 12L.
Thinner is better for high-speed operation of bipolar transistors, but thicker is better for increasing the withstand voltage of bipolar transistors.

When IaL and normal bipolar transistors are integrated in this way, and one requires high-speed operation and the other high breakdown voltage, contradictory conditions are required for the n-type layer 3. Therefore, the actual characteristics obtained are that the IIL operation period is 201 seconds.
The breakdown voltage of the ec+ bipolar transistor is 5V or less, which is not sufficient for practical use. Furthermore, if we try to increase the fanout of the 12L section, the area of the inactive 5-region of the base region 6 will also increase, so the ratio of collector-base junction area/base-emitter junction area will become smaller and the current amplification factor will decrease. I can't get enough.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which an ILL and a normal bipolar transistor are installed together in the same unit by fully utilizing their respective characteristics, and a method for manufacturing the same.

A semiconductor device according to the present invention includes a semiconductor substrate of a second conductivity type having a selectively formed first buried region of a first conductivity type, and a first semiconductor of a first conductivity type formed on the semiconductor substrate. a second buried region of the first conductivity type selectively formed on the first semiconductor layer; an insulating layer selectively formed on the second buried region; and a second semiconductor layer of the first conductivity type formed therein, and an element is formed in each of the second semiconductor layer portions on the first and second buried regions.

The method according to the present invention includes forming a first epitaxial layer of a second conductivity type on the main surface of a semiconductor substrate of a fourteenth conductivity type, and forming a first region of this epitaxial layer, that is, a normal bipolar transistor region. A first buried layer of opposite conductivity type and high fik degree is formed only at the interface with the substrate, and the first buried layer is formed in the second region, that is, the IIL region.
The second embedding 1fi of the oppositely guided tortoise-shaped high-concentration above the embedding layer of
an insulating layer selectively formed on one main surface of the second region of the first epitaxial layer, the insulating layer corresponding to the lateral transistor region of the ILL and the collector and emitter electrode extraction regions of the vertical transistor. The present invention is characterized in that an insulating layer having an opening is provided, and then a second epitaxial layer of an opposite conductivity type is formed, and element regions are formed in the second epitaxial layer portions of the first and second regions, respectively.

Another method of the present invention is characterized in that the polycrystalline portion of the second epitaxial layer is made into a single crystal to form the element region. In this case, the first buried layer is for reducing the collector resistance of the bipolar transistor as a high voltage element9, and the second buried layer is for functioning as the emitter region of the I2L inverter.

Hereinafter, the present invention will be explained in detail with reference to the drawings based on examples.

FIG. 2 shows an embodiment of the present invention in which a high-speed I"L and a normal high-voltage bipolar transistor are integrated.
This will be explained according to the mounting process.

First, as shown in FIG. 2(a), a first n-type buried layer 12112' containing a high concentration of sb is formed at a predetermined location on the surface of the P-type Si substrate 11 made of foil with a resistivity of 10 to 5θΩ. Next, a first n-type layer 13 having a specific resistance of 1 to 2 θΩ and a thickness of about 5 to 15° is epitaxially grown on the entire surface of the substrate.

Thereafter, as shown in FIG. 4B, a second n+ type buried layer 14 containing a high concentration of sb is formed in a region where 12L is to be formed on the surface of the epitaxial layer 13.

Next, an oxide film 15 is formed on the surface of the substrate, and openings are formed only in the active regions of the lateral transistors and vertical transistors in the IIIL section.That is, in the base regions of the lateral transistors in the ILL section and in the particle transistors. The oxide film formed on the top of the base region and emitter lead-out region is removed.On the other hand, all the oxide films other than the IWL portion are removed.

Next, as shown in FIG. 2C, a second n-type epitaxial layer 16' is formed over the entire surface of the substrate. At this time, polycrystalline silicon 17 grows in the region on the oxide film 15, and single crystal silicon 16 grows in the region where the oxide film 15 does not exist.

Next, the second epitaxial layer 16 is formed as shown in FIG.
Impurities are diffused from the surface of ' to form a p-type insulating region 30, and further, the emitter of the IIL injector lateral transistor 18I and the base 20 of the vertical transistor
(This region also serves as the collector 19 of the lateral transistor) and a P shadow region that serves as the base 21 of a normal bipolar transistor. Next, the collector 229 of the l1tL bipolar transistor emitter 23 . At the same time, an N-type shock region, which will become the collector extraction 24, is formed.

Finally, as shown in figure (e), an insulating layer is formed on the surface,
Predetermined portions are opened to form the injector, base, collector, and emitter of I2L, and the base, emitter, and collector extraction electrodes of a normal bipolar transistor, respectively. Here, Fig. 2(d) l
As shown in (e), I21. If the second epitaxial layer is selectively oxidized not only on the bottom surface but also on the side surfaces and surrounded by an oxide film 25, it is effective to further increase the speed.

The semiconductor device obtained by the manufacturing method explained above is
A thin epitaxial layer determined by the thickness of the second epitaxial layer 16 is formed in the ILL region, and a thick epitaxial layer determined by the sum of the thicknesses of the first epitaxial layer 13 and the second epitaxial layer 16 is formed in the normal bipolar transistor region. .

Therefore, bipolar transistors can have high voltage resistance, and 111
Since the emitter high concentration region 14 of the L element is in contact with the base 2°, a high current amplification factor can be obtained. Moreover, in I2L, the current amplification factor can be increased by providing the highly doped emitter region 14 below the base region 20, and since the regions other than the active region are covered with the oxide film 15, the excess The generation of accumulated carriers can be suppressed and the switching speed can be significantly improved.

FIG. 3 shows another embodiment of the invention. This embodiment is a further improvement of the one shown in FIG.
This is to obtain the current amplification factor of the LL section. That is, the second
In the figure, since a part of the base region 20 (collector region 19) is made of polycrystalline silicon tt, the base recombination current is relatively large.

In FIG. 3, this base recombination current is also reduced, and will be explained in detail below. The same parts as in FIG. 2 are designated by the same numbers.

First, a first N-type epitaxial layer 13 having an N-type buried region 14 is formed on a substrate 11 according to FIGS. 2(a) and 2(b), and an oxide film 15 is selectively formed as described above. do.

Next, as shown in FIG. 3(a), a polycrystalline crystal layer 40 is formed on the entire surface by LPGVD (low pressure chemical vapor deposition) at 620°C.
5000-1 is formed. After this, after annealing in a nitrogen atmosphere at 1100°C, a 20W CW argon ion laser was applied with a lens to a spot diameter of 70μ and 10cm.
Scan every 6-10μ at a speed of /sec. The substrate heating at this time is 500°C. In this way, polycrystalline silicon is laterally grown epitaxially by 80 μm using the epitaxial single crystal silicon as a seed. The IllL portion changes from the opening to polycrystalline silicon single crystal, and as a result, all the polycrystalline silicon converts to single crystal.

Next, as shown in FIG. 3B, the monocrystalline silicon layer 40' surrounding IttL is selectively oxidized to the depth of the buried oxide film 15 to form an oxide film 25. After this, the insulating region 30 + the P shadow region which becomes the emitter 18 and the collector 19 of the injector lateral transistor in the I''L part, the P shadow region which becomes the base 20 of the IL inverter and the transistor 2 transistor, and the base region of a normal bipolar transistor. The base 20 and the collector 19 are formed at the same time by BCl3 diffusion.

Next, the collector 22 and emitter electrode extraction region 22' of 12L, and the n+ type region pC1 of the emitter 23 and collector 24 of the normal
3 Formed by diffusion.

Finally, a contact hole is formed in the surface insulating layer, and an electrode metal width is applied to complete the process.

In the semiconductor device formed in this manner, the IsL has a highly concentrated emitter region 14 directly below the base region and on the surface of the n-type epitaxial layer, so that the emitter concentration can be made higher than that of the base a degree, and the current amplification factor can be increased. Moreover, since the non-active region of the base-emitter junction area of the ILL is covered with an oxide film, excess accumulated carriers can be minimized. On the other hand, the breakdown voltage of a normal bipolar transistor can be made sufficiently large because the thickness can be increased regardless of the characteristics of I2L. In addition, the surface mobility of the layer made into single crystal silicon by laser annealing is 540 CI.
rL"/V -see, which is the same as that of ordinary single crystal silicon. Therefore, 1. The base recombination current can be reduced compared to when the base region is formed as polycrystalline silicon, and a larger current amplification factor can be obtained. It will be done.

Similarly, instead of the polycrystalline silicon layer 140 shown in FIG. 3, the polycrystalline silicon layer 17 shown in FIG. 2(c) may be made into a single crystal and formed as shown in FIG. 3(b). .

[Brief explanation of drawings]

FIG. 1 is a structural sectional view of a conventional 12L, FIG. 2 is a process sectional view showing one embodiment of the present invention, and FIG. 3 is a process sectional view showing another embodiment. l・11...P-type board, 2.2'...
n+ type buried layer %3113...N type epitaxial layer, 4゜14...P+ type insulating separation layer, 5...
...n+ shape area 6...IL base, 6'
+18 Yu...Injector emitter, 6〃*21・
...Bipolar base, 7,22...
Collector of I2L, 7', 23...Emitter of bipolar transistor, 7''...Collector of bipolar transistor, 15...Insulating film, 1
2+12'...First epitaxial layer, 16
...Second epitaxial layer 14-

Claims (3)

[Claims] (1) a semiconductor substrate of a second conductivity type having a selectively formed first buried region of the first conductivity type; a first semiconductor layer of the first conductivity type formed on the semiconductor substrate; a second buried region of the first conductivity type selectively formed in the first semiconductor layer; an insulating layer selectively formed on the second buried region; and a second buried region selectively formed on the first semiconductor layer. a second conductor layer of a first conductivity type, and an element is formed in a second semiconductor layer portion on the first buried region and a second semiconductor layer portion on the second buried region, respectively. A semiconductor device featuring Irukoshichi. (2) A first semiconductor substrate of a first conductivity type is attached to a semiconductor substrate of a second conductivity type.
selectively forming a buried region; forming a first semiconductor layer of a first conductivity type on the semiconductor substrate;
selectively forming a second buried region of the first conductivity type on the semiconductor layer; selectively forming an insulating layer on the second buried region; and forming a second buried region on the first semiconductor layer. 1 conductivity type 2nd
A method for manufacturing a semiconductor device, comprising the steps of forming a semiconductor layer, and forming elements in second semiconductor layer portions on the first and second buried regions, respectively. (3) selectively forming a first buried region of a first conductivity type on a semiconductor substrate of a second conductivity type; and forming a first semiconductor I- of a first conductivity type on the semiconductor substrate; , a step of selectively forming a second buried region of a first conductivity type in the first semiconductor layer; a step of selectively forming an insulating layer on the second buried region; and a step of selectively forming a second buried region of a first conductivity type in the first semiconductor layer. a step of forming a second semiconductor layer of a first derivation type thereon, a step of converting a polycrystalline portion of the second semiconductor layer into a single crystal, and a step of forming a second semiconductor layer on the first and second buried regions;
1. A method for manufacturing a semiconductor device, comprising the step of forming elements in respective semiconductor layer portions.