JPH02163940A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance an integration density of an integrated circuit and to reduce a diffusion process by a method wherein a transistor is constituted by forming a base region, a collector region and an emitter region in an intrinsic semiconductor region in order to electrically isolate elements without forming an isolation region. CONSTITUTION:An intrinsic semiconductor layer 2 formed on a semiconductor substrate 1 of one conductivity type is provided; a first region 3 of one conductiv ity type is provided near the surface of the intrinsic semiconductor 2; second regions 4, 5, of another conductivity type, formed so as to overlap with both side faces of the first region 3 are provided. For example, an intrinsic semicon ductor layer 2 is grown on a P-type substrate 1 by using SiH4 and Cl2; after that, P-type impurities are diffused from the surface of the intrinsic semiconduc tor layer 2; a base region 3 is formed. Then, N<+> type impurities are diffused so as to overlap with both side faces of the base region 3; a collector region 4 and an emitter region 5 are formed. Then, an oxide film 6 in prescribed contact opening regions in the emitter region, the base region and the collector region is etched; respective electrode patterns 7 to 9 are formed; an NPN transis tor is manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor device, particularly a transistor.

[Conventional technology]

As shown in FIG. 2, this type of transistor conventionally used in semiconductor integrated circuits has an epitaxial layer of another conductivity type on a -conductivity type semiconductor substrate, and the epitaxial layer is electrically isolated from the substrate. As shown in FIG. 2, the structure has a base region of the negative conductivity type and an emitter region of another conductivity type within the base region.

[Problem to be solved by the invention]

Since the transistor with the conventional structure described above has a lightly doped epitaxial layer (impurity concentration: around 10"cm-3), an isolation region is required for electrical isolation from other elements in the epitaxial layer. However, the disadvantage is that the degree of integration of the integrated circuit cannot be increased.

[Means to solve the problem]

In the present invention, an epitaxial layer (impurity concentration: 101s
cm-”) without using an intrinsic semiconductor (impurity concentration: 0~
By forming a transistor in a 10" cm-3 layer, the resistivity between each element increases from infinity to 10" times that when a conventional epitaxial layer is used, so even if a potential difference occurs between elements, , the current flowing there becomes so small that it does not affect the circuit operation. In addition, by using an intrinsic semiconductor, carriers (free electrons,
Since the number of holes (holes) is extremely small, the parasitic elements that occur in conventional techniques do not occur even in a normal impurity concentration layer. In this way, the present invention realizes electrical isolation without providing an isolation region.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a structural sectional view of an embodiment of the present invention.

As shown in FIG. 1, silane gas (S
Intrinsic semiconductor layer 2 is formed using iH+) and chlorine gas (Cβ2).
After growing P-type impurities (impurity concentration: around 101"C111"") from the surface of the intrinsic semiconductor layer 20,
A base region 3 is formed. Next, N+ type impurities (impurity concentration: around xo20) are diffused so as to overlap both side surfaces of the base region 3 to form a collector region 4 and an emitter region 5. Next, the oxide film 6 is etched in predetermined contact regions of the emitter, base, and collector regions to form respective electrode patterns 7, 8, and 9. In this way, an NPN transistor is manufactured.

[Effects of the Invention] As explained above, the present invention includes a base region 3. in the intrinsic semiconductor region 2. Collector area 4. By forming the emitter region 5 and configuring a transistor, it is possible to electrically isolate between elements without providing an isolation region by utilizing the properties of an intrinsic semiconductor (high resistance). This makes it possible to improve the degree of integration of the integrated circuit and reduce the number of diffusion steps.

[Brief explanation of the drawing]

FIG. 1 is a structural sectional view of one embodiment of the present invention, and FIG. 2 is a structural sectional view of a conventional example. 1...P-type substrate, 2...Intrinsic semiconductor region, 3...P-type base region, 4...N
type collector region, 5...N type emitter region, 6
...Oxide film, 7...Collector electric tff
i, 8...Base electric L 9...
Emitter electrode, 10...N-type buried layer, 11...
...P type isolation region, 12...N type epitaxial layer. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] It has an intrinsic semiconductor layer formed on a semiconductor substrate of one conductivity type, and has a first region of one conductivity type near the surface of the intrinsic semiconductor, and another conductivity type configured to overlap on both sides of the first region. A semiconductor device characterized by having a second region.