JPH0574791A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable a semiconductor of this design to be enhanced in breakdown strength by a method wherein an N-type epitaxial layer low enough in impurity concentration is located inside a groove formed on an N<+>-type buried layer surrounding the side face of a P<+>-type buried layer. CONSTITUTION:Phosphorus ions are implanted into a P-type silicon substrate 1 to form an N<+>-type buried layer 2. P<+>-type buried layers 3 and 3a are formed the same as above. Then, an etching process is carried out surrounding the buried layer 3 to isolate the side face. In succession, an N-type epitaxial layer 4 is made to grow, and boron ions are implanted into the N-type epitaxial layer 4 through its surface to form a P<->-type collector. As mentioned above, boron ions are implanted to form a P<+>-type collector leading-out layer 6 and a P<+>-type insulating isolation layer 6a at the same time. By this setup, a depletion layer is made to extend from the P<+>-type buried layer to the N-type epitaxial layer, so that a semiconductor device of this design can be enhanced in breakdown strength.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a triple diffusion type PNP transistor.

[0002]

2. Description of the Related Art Conventional triple diffusion type PN for semiconductor integrated circuits
P-transistor (hereinafter referred to as T-PNP) FIG.
First, an N ⁺ type buried layer 2 is formed on a P type silicon substrate 1, P ⁺ type buried layers 3 and 3a are formed, and then an N type epitaxial layer 4 is grown on the entire surface. ..

Next, from the surface of the N type epitaxial layer 4 to P
A type insulation separation layer 6a is formed to perform insulation separation for each element region. At this time, the P ⁺ -type collector extraction layer 6 is formed at the same time.

Next, a P ⁻ type collector 5 is formed so as to contact the P ⁺ type collector extraction layer 6, and an N type base 7 is formed from the surface of the P ⁻ type collector 5. At this time, the N ⁺ type bias contact 7a is simultaneously formed.

Next, a P ⁺ type emitter 8 is formed from the surface of the N type base 7. Next, after a silicon oxide film 9 is grown on the entire surface, contacts are opened in each of the base 7, the emitter 8, the collector extraction layer 6, and the bias contact 7a. Next, a collector electrode 12, a base electrode 11, an emitter electrode 10 and a bias electrode 13 made of aluminum are formed to form a triple diffusion PNP transistor (T-PNP).
The element part of is completed.

[0006]

In FIG. 2, the N-type epitaxial layer 4 of the T-PNP for a semiconductor integrated circuit is biased by the maximum potential of each circuit such as V _CC in order to prevent leakage current due to parasitic elements. , Collector extraction layer 6
And the N-type epitaxial layer 4 are always set to be reverse biased.

However, the T ⁺ PNP N ⁺ type buried layer 2 and P ₊
The profile of the bottom surface of the junction with the mold burying layer 3 is gentle at low concentration, but the profile of the side surface is steep at high concentration especially near the boundary between the N-type epitaxial layer 4 and the P-type silicon substrate 1. .. Therefore, the depletion layer does not extend on the side surfaces of the buried layers 2 and 3, and the breakdown voltage is lowered, so that it is difficult to cope with the high breakdown voltage.

[0008]

The semiconductor device of the present invention comprises:
A reverse conductivity type buried layer is selectively formed on one main surface of the one conductivity type semiconductor substrate, and a one conductivity type buried layer is selectively formed on the reverse conductivity type buried layer. A semiconductor layer of the opposite conductivity type is formed in the buried layer of the opposite conductivity type so as to surround the side surface of the layer and have a lower concentration than that of the buried layer of the one conductivity type.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to (c).

This triple diffused PNP transistor is manufactured as follows.

First, as shown in FIG. 1A, a P-type silicon substrate 1 is ion-implanted with phosphorus ( ³¹ P ⁺ ), for example, and N
^{A +} type buried layer 2 is formed. Similarly, the P ⁺ type buried layer 3,
3a is formed. Then, the side surface is separated by etching so as to surround the P ⁺ type buried layer 3.

Next, as shown in FIG. 1B, after growing the N type epitaxial layer 4, boron ( ¹¹ B ⁺ ) ions are implanted from the surface of the N type epitaxial layer 4 to form the P ⁻ type collector 5. Form. Similarly, boron is ion-implanted to simultaneously form the P ⁺ -type collector extraction layer 6 and the P ⁺ -type insulating separation layer 6a.

At this time, the P ⁻ type collector 5 is connected to the P ⁺ type buried layer 3, and similarly the P ⁺ type collector extraction layer 6 is connected to the P ⁻ type collector 5 and the P ⁺ type collector extraction layer 6. .. Further, the P ⁺ type insulating separation layer 6a is connected to the P ⁺ type buried layer 3a.

Next, as shown in FIG. 1C, an N-type impurity is ion-implanted into the P-type collector 5 to form an N-type base 7,
Then, an N ⁺ type bias contact 7a is formed in the N type epitaxial layer 4. Next, P-type impurities are diffused in the N-type base 7 to form a P ⁺ -type emitter 8.

Next, after a silicon oxide film 9 is grown on the entire surface, contacts are opened in each of the base 7, the emitter 8, the collector extraction layer 6, and the bias contact 7a. Next, the collector electrode 12, the base electrode 11, the emitter electrode 10, and the bias electrode 13 made of aluminum are formed to complete the element portion of the triple diffusion PNP transistor.

[0016]

Since the impurity concentration in a groove formed in the N ⁺ -type buried layer surrounds the P ⁺ -type buried layer side according to the present invention there is sufficiently low N-type epitaxial layer, N-type from the P ⁺ -type buried layer A depletion layer extends to the epitaxial layer. Therefore, it has become possible to deal with higher breakdown voltage.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps.

FIG. 2 is a sectional view showing a conventional triple diffusion type PNP transistor.

[Explanation of symbols]

1 P-type silicon substrate 2 N ⁺ type buried layer 3, 3a P ⁺ type buried layer 4 N type epitaxial layer 5 P ⁻ type collector 6 P ⁺ type collector extraction layer 6a P ⁺ type insulating separation layer 7 N type base 7a N ⁺ type bias contact 8 P ⁺ type emitter 9 Silicon oxide film 10 Emitter electrode 11 Base electrode 12 Collector electrode 13 Bias electrode

Claims (1)

[Claims] 1. A reverse conductivity type buried layer is selectively formed on one main surface of a single conductivity type semiconductor substrate, and a reverse conductivity type buried layer is selectively formed on the reverse conductivity type buried layer. A semiconductor device in which a semiconductor layer of a reverse conductivity type is formed in the reverse conductivity type buried layer so as to surround a side surface of the first conductivity type buried layer and at a concentration lower than that of the first conductivity type buried layer.