JP3327658B2 - Manufacturing method of vertical bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a high withstand voltage vertical bipolar transistor in a bipolar integrated circuit.

[0002]

2. Description of the Related Art FIG. 3 shows a typical method of manufacturing a conventional vertical bipolar transistor. An N-type buried layer 2, a P-type isolation layer 3, and a P-type buried layer 4 serving as a collector of a PNP transistor are formed on a P-type silicon substrate 1 by a known diffusion technique. .5
It is grown to a thickness of about 3.0 microns with a resistivity of Ω · cm (FIG. 3a). Next, after an oxide film is formed on the surface of the N-type epitaxial layer, it is selectively removed by a well-known photo-etching method. Using the oxide film 6 as a mask, impurities are ion-implanted into the exposed surface of the epitaxial layer 5 and thermally diffused to simultaneously form a P-type isolation layer 7 and a P-type diffusion region 8 constituting a part of the collector of the PNP transistor. Each is connected to the P-type separation layer 3 and the P-type buried layer 4 formed earlier (FIG. 3B). With the P-type diffusion region 8 and the P-type buried layer 4,
It constitutes the collector of the PNP transistor. After removing the oxide film 6 and forming a new oxide film, the oxide film in the base formation region is selectively removed, and impurities are ion-implanted into the exposed surface of the P-type diffusion region 8 using the oxide film 9 as a mask. Then, an N-type diffusion region 10 constituting the base of the PNP transistor is formed (FIG. 3C). Thereafter, the oxide film 9 is removed, a new oxide film is formed, and after selective removal, the oxide film 1 is removed.
Impurities are ion-implanted into the exposed surface of the N-type diffusion region 10 using 1 as a mask to form a P-type diffusion region 12 constituting an emitter of the PNP transistor. At the same time, the P-type diffusion region 8 constituting the collector of the PNP transistor is exposed to form a P-type diffusion region. This constitutes the collector contact region 13 of the PNP transistor (FIG. 3)
d). Thereafter, the oxide film 11 is removed, a new oxide film is formed and selectively removed, and impurities are ion-implanted into the exposed surface of the N-type diffusion region 10 using the oxide film as a mask.
An N-type diffusion region 14 is formed. This constitutes the base contact of the PNP transistor. Next, the oxide film of the mask is removed, a new oxide film 15 is formed, and selectively removed to open the contact windows of the collector, base, and emitter of the PNP transistor, and electrodes 16, 18, and 17 are formed, respectively. A PNP transistor is completed (FIG. 3E).

As described above, the conventional method of manufacturing a PNP transistor uses the P-type diffusion region 8 forming a part of the collector.
Was formed by thermal diffusion after ion implantation. When the thickness of the epitaxial layer 5 is relatively small, such as about 3.0 μm, this thermal diffusion needs to be completed in a short time. Therefore, the profile of the impurity concentration in the depth direction of the P-type diffusion region 8 has a concentration gradient such that the impurity concentration decreases as the depth increases. When the N-type diffusion region 10 serving as the base of the PNP transistor is formed on the P-type diffusion region 8 having such a concentration gradient, the concentration of the P-type diffusion region 8 affects the concentration of the N-type diffusion region 10. Change. FIG. 2A shows a profile of an impurity concentration in a depth direction of a base portion of a PNP transistor formed by a conventional manufacturing method. The concentration of the P-type diffusion region 8 forming the collector of the PNP transistor becomes higher on the side of the N-type diffusion region 10 forming the base. In such a concentration profile, the impurity concentration of the N-type diffusion region 10 constituting the base becomes relatively low, so that the expansion of the depletion layer between the collector and the base to the base side cannot be suppressed, and the effective base width changes. However, there is a problem that the Early voltage is reduced. Further, there is a problem that the impurity concentration of the P-type diffusion region 10 constituting the collector becomes relatively high, and the withstand voltage between the base and the collector is lowered.

[0004]

In the conventional method of manufacturing a PNP transistor, since the impurity concentration of the P-type diffusion region forming the collector is relatively high, the Early voltage is reduced and the base-collector breakdown voltage is reduced. There was a problem. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a vertical bipolar transistor having a high withstand voltage.

[0005]

According to the present invention, in order to achieve the above object, a reverse conductivity type epitaxial layer is formed on a semiconductor substrate of one conductivity type, and a reverse conductivity type is formed between the epitaxial layer and the semiconductor substrate. A vertical bipolar transistor for forming a buried layer of conductivity type and forming a collector of one conductivity type, a base of opposite conductivity type, and an emitter of one conductivity type at predetermined positions of the epitaxial layer on the buried layer; In the method for manufacturing a transistor, an impurity of one conductivity type and an impurity of the opposite conductivity type are respectively formed on the surface of the epitaxial layer in the base formation region.
After ion implantation and thermal diffusion at the same time, a reverse conductivity type
The base region is formed by ion implantation of impurities.
As well as formed, between the base and the collector,
Forming a diffusion region of one conductivity type having a lower impurity concentration than that of the collector.

[0006]

FIG. 1 shows a method of manufacturing a vertical PNP transistor according to the present invention. An N-type buried layer 2 on a P-type silicon substrate 1;
A P-type isolation layer 3 and a P-type buried layer 4 serving as a collector of a PNP transistor are formed by a well-known diffusion technique. Further, an N-type epitaxial layer 5 is formed with a specific resistance of, for example, 1.5 Ωcm and about 3.0 μm. Growing in thickness. next,
Using the oxide film as a mask, impurities are ion-implanted from the surface of the N-type epitaxial layer 5 and thermally diffused to form a P-type isolation layer 7.
And a P-type diffusion region 8 which is a part of the collector of the PNP transistor is formed at the same time, and is connected to the P-type separation layer 3 and the P-type buried layer 4 formed earlier. The P-type diffusion region 8 and the P-type buried layer 4 form a collector of the PNP transistor. A new oxide film is formed and PNP
The oxide film 9 in the base formation region of the transistor is selectively removed (FIG. 1A). The steps so far are the same as the conventional manufacturing method.

An impurity is ion-implanted into the exposed surface of the P-type diffusion region 8. Conventionally, this impurity implantation was performed only once by implanting boron in order to form the N-type diffusion region 10. However, in the present invention, the following ion implantation, It is characterized by adding a heat diffusion step. That is, boron and phosphorus are respectively ion-implanted into the exposed surface of the P-type diffusion region 8 and simultaneously thermal diffusion is performed. As an example, after boron is implanted at a dose of 1.5E12 and an acceleration voltage of 200 KeV, phosphorus is immediately implanted at a dose of 1.3E12 and an acceleration voltage of 200 KeV. Thereafter, thermal diffusion is performed at 1100 ° C. for 120 minutes. Due to the relationship between the range of ion implantation and the concentration, boron diffuses deeper by thermal diffusion than phosphorus. As a result, a P-type diffusion region 8 having a depth lower than the impurity concentration of the P-type diffusion region 8 is introduced into the P-type diffusion region 8 having a depth of 1.0 to 1.3 μm from the surface.
A mold diffusion region 19 is formed. Subsequent steps are the same as in the conventional method, and an impurity is ion-implanted using the oxide film 9 as a mask to form an N-type diffusion region 10 constituting the base of the PNP transistor (FIG. 1B). Thereafter, the oxide film 9 is removed, a new oxide film is formed, and the oxide film 11 is selectively removed. Then, ions are implanted into the exposed surface of the N-type diffusion region 10 using the oxide film 11 as a mask to form a P-type transistor constituting the emitter of the PNP transistor. A diffusion region 12 is formed. At the same time, the P-type diffusion region 8 constituting the collector of the PNP transistor is exposed to form a P-type diffusion region. This constitutes the collector contact region 13 of the PNP transistor (FIG. 1).
c). Further, the oxide film 11 is removed, a new oxide film is formed, and the oxide film is selectively removed. Using this oxide film as a mask, impurities are ion-implanted into the exposed N-type diffusion region 10 to form the N-type diffusion region 14. Form. This constitutes the contact at the base of the PNP transistor. Next, the oxide film is removed, and a new oxide film 15 is formed.
The contact windows of the collector, base, and emitter of the transistor are opened, and electrodes 16, 18, and 17 are formed, respectively, to complete the PNP transistor (FIG. 1d).

FIG. 2B shows the impurity concentration profile in the depth direction of the base portion of the PNP transistor formed by the above-described manufacturing method (solid line). It can be seen that there is a great difference in the concentration profile of the P-type diffusion region, that is, the collector portion, as compared with the PNP transistor (shown by the dotted line) formed by the conventional manufacturing method. In the PNP transistor of the present invention, since the P- diffusion region is present in the collector portion, the impurity concentration in the collector portion is low, and the concentration gradient is increased on the N-type diffusion region (base) side as conventionally observed. Has not occurred. In addition, it can be seen that the shortening of the width of the N-type diffusion region (base), which is considered to have conventionally occurred due to the concentration gradient, has eased. According to the present invention, by realizing such a concentration profile, the impurity concentration of the N-type diffusion region becomes relatively high,
The expansion of the depletion layer between the collector and the base toward the base side was suppressed, the effective base width did not change, and the problem of an early voltage drop could be solved. Also, the impurity concentration of the P-type diffusion region (collector) was relatively low, and a sufficient base-collector breakdown voltage was obtained.

In the case where P-diffusion region 18 is formed, the case where boron and phosphorus are implanted has been described as an example.
The present invention is not limited to this combination. In a combination of impurities that become P-type and N-type with respect to the semiconductor substrate, the P-type impurity diffuses deeper than the N-type impurity as a result of thermal diffusion. Good. In order to realize such diffusion, the concentration of the epitaxial layer, implantation conditions of P-type impurities and N-type impurities, thermal diffusion conditions, and the like are appropriately set.

The present invention is particularly effective when forming an integrated circuit having a vertical bipolar transistor and a CMOSFET on the same semiconductor substrate. For example, usually, the P-type diffusion region 8 constituting the collector of the vertical PNP transistor is formed simultaneously with the P-well of the nMOS transistor, but according to the present invention, regardless of the impurity concentration of the P-well, the P-type diffusion region 8 is formed immediately below the base. The impurity concentration can be determined.
Therefore, a high breakdown voltage vertical bipolar transistor is
It can be formed on the same substrate as the MOSFET.

[0011]

As described above, in the vertical bipolar transistor according to the manufacturing method of the present invention, the P- diffusion region having a low impurity concentration is formed in the collector region immediately below the base region, so that the relative base region can be formed. The impurity concentration was increased, the expansion of the collector-base depletion layer to the base side was suppressed, the change in the effective base width was reduced, and the early voltage was prevented from lowering. Further, the impurity concentration of the collector was relatively low, and a sufficient base-collector breakdown voltage could be obtained. Furthermore, forming a high concentration emitter,
As a result, the base can also be made highly concentrated, the base resistance is small, the current amplification factor is high, and a sufficient punch-through voltage can be obtained even if the base width is reduced. Since the gap can be formed shallow, high-frequency operation has become possible.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing a manufacturing method according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram comparing impurity concentration profiles of the present invention and a conventional example.

FIG. 3 is an explanatory view showing a method for manufacturing a conventional vertical bipolar transistor.

[Description of sign]

 Reference Signs List 1 P-type silicon substrate 2 N-type buried layer 3 P-type separation layer 4 P-type buried layer 5 N-type epitaxial layer 6 oxide film 7 P-type separation layer 8 P-type diffusion region 9 oxide film 10 N-type diffusion region 11 oxidation Film 12 P-type diffusion region 13 Collector contact region 14 N-type diffusion region 15 Oxide film 16 Collector electrode 17 Emitter electrode 18 Base electrode 19 P-type diffusion region

Claims (1)

(57) [Claims] An epitaxial layer of a reverse conductivity type is formed on a semiconductor substrate of one conductivity type, and a buried layer of a reverse conductivity type is formed between the epitaxial layer and the semiconductor substrate. A method of manufacturing a vertical bipolar transistor in which a collector of one conductivity type, a base of opposite conductivity type, and an emitter of one conductivity type are formed at predetermined positions of the epitaxial layer above, wherein the epitaxial layer in the base formation region On the surface, impurities of one conductivity type and impurities of the opposite conductivity type are ionized, respectively.
After implantation and thermal diffusion at the same time, impurities of the opposite conductivity type
Forming the base region by performing ion implantation of
And a step of forming a one-conductivity-type diffusion region having a lower impurity concentration than the collector between the base and the collector.