JP2001291781A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device into which a BiCOMS semiconductor device capable of constituting a bi-polar transistor capable of reducing a collector resistance without forming any epitaxial layer is integrated. SOLUTION: An N type diffusion area 9 is formed just under an N+ type diffusion area 16 for ohmic contact in an N-type well 3 of the collector area of an NPN type bi-polar transistor, by using a process to carry out ion injection for forming an N type diffusion area 8 for improving punch through breakdown strength between the drain and source of a P type channel MOS transistor simultaneously prepared with the bi-polar transistor. Thus, the concentration of the collector of the NPN type bi-polar transistor can be improved, and electric characteristics can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same substrate without forming an epitaxial layer. .

[0002]

2. Description of the Related Art In recent years, integrated circuits having a mixture of analog and digital functions have been widely used, and semiconductor devices (BiCMOS semiconductor devices) having a built-in bipolar transistor and MOS transistor have been used for such integrated circuits.

[0003] A conventional method for manufacturing a semiconductor device will be described below.

FIG. 4 is a sectional view showing a completed state of a conventional BiCMOS semiconductor device without forming an epitaxial layer. Since this method of manufacturing a semiconductor device is manufactured by a well-known technique, a cross-sectional view in the order of steps will be omitted and will be briefly described. Some hatching is omitted because the drawing becomes complicated.

In FIG. 4, reference numeral 1 denotes a semiconductor substrate made of P-type silicon. 2 denotes N ⁻ formed on the semiconductor substrate 1.
A P-channel MOS transistor (hereinafter referred to as P
(abbreviated as chMOS transistor). Numeral 3 denotes a vertical NPN formed simultaneously with the N ^- type well 2
N ^- type well serving as a collector region of a bipolar transistor (hereinafter abbreviated as an NPN transistor). Reference numeral 4 denotes a P-type well formed in the semiconductor substrate 1 and serves as an N-channel MOS transistor (hereinafter abbreviated as an NchMOS transistor) region.

Reference numeral 5 denotes a P-type well for separating the collector region of the NPN transistor from the MOS transistor region. Reference numeral 6 denotes a LOCOS oxide film for isolating MOS transistors. Reference numeral 8 denotes an N-type diffusion region for preventing punch-through between the drain and the source of the PchMOS transistor and increasing the breakdown voltage. Reference numeral 10 denotes a gate oxide film. Reference numeral 11 denotes a gate electrode made of polycrystalline silicon. Reference numeral 12 denotes a P-type base (diffusion region) of the NPN transistor. Reference numeral 13 denotes a CVD film serving as a spacer.

[0007] Reference numeral 14 denotes an N ⁺ type diffusion region serving as a source and a drain of the NchMOS transistor. 15 is NPN
This is an N ⁺ type diffusion region that becomes an emitter of the transistor.
Reference numeral 16 denotes an N ⁺ -type diffusion region for an ohmic contact provided on the surface of the collector region of the NPN transistor. Reference numeral 17 denotes a P ⁺ type diffusion region serving as a source and a drain of the PchMOS transistor. Reference numeral 18 denotes a P ⁺ -type diffusion region provided on the surface of the P-type base 12 of the NPN transistor and serving as an external base region. 19 is P for element isolation
This is a P ⁺ type diffusion region provided on the surface of the mold well 5.
Reference numeral 20 denotes a field oxide film made of a CVD film.

Reference numeral 21a is a source electrode of the NchMOS transistor. 21b is a drain electrode of the NchMOS transistor. 22a is a source electrode of the PchMOS transistor. 22b is a drain electrode of the PchMOS transistor. 23a is an emitter electrode of the NPN transistor. 23b is a base electrode of the NPN transistor. 23c is a collector electrode of the NPN transistor.

Next, a method of manufacturing a conventional BiCMOS semiconductor device without forming an epitaxial layer will be described.

First, using a mask, an N ^- type well 2 is formed in a region to be a Pch MOS transistor in a semiconductor substrate 1 made of P-type silicon,
An N ^- type well 3 is formed in a region to be a collector of the PN transistor. Using a mask, a P well 4 is formed in a region to be an Nch MOS transistor, and a P well 4 is formed in a region to be used for element isolation of a bipolar transistor.
A well 5 is formed.

Next, a LOCOS oxide film 6 for element isolation between the PchMOS transistor and the NchMOS transistor is formed by thermal oxidation. This LOCOS oxide film 6 is also formed on a part of the surface of the collector region of the NPN transistor and becomes a field oxide film.

Further, ion implantation for adjusting the threshold voltage of the MOS transistor is performed into the N ^- type well 2 in the PchMOS transistor region and the P-type well 4 in the NchMOS transistor region (not shown in FIG. 4). .

Then, 80 keV using phosphorus impurities
Ion implantation with energy of 200 keV from Pch
An N-type diffusion region 8 is formed near the surface of the N ^- type well 2 of the MOS transistor. N-type diffusion region 8 is a PchMOS
This is to prevent the withstand voltage between the drain and the source of the transistor from being reduced by punch-through. It is formed immediately below the source / drain diffusion region and the region where the channel region is to be formed.

Next, the LOCOS oxide film 6 is thermally oxidized.
A gate oxide film 10 is formed on the surface of the semiconductor substrate 1 other than the above, polycrystalline silicon containing phosphorus is deposited, and the resultant is etched to pattern the gate electrode 11. Also, a P-type base 12 is formed on the surface of the collector region of the NPN transistor by ion implantation using boron, and the polycrystalline silicon of the gate electrode 11 is oxidized by thermal oxidation (not shown in FIG. 4).

The entire surface is formed by CVD (Chemical Vapor).
Deposition) film is deposited, and RIE (Reactive Io)
n Etch) to etch the entire surface,
On one side surface, a CVD film 13 is formed as a spacer.
The CVD film 13 is not shown in FIG. 4 to prevent the short channel effect of the MOS transistor.
An N-type diffusion region is formed in the S transistor region and Pc
This spacer is used as a mask for ion implantation for forming a P-type diffusion region in the hMOS transistor region.

Next, by ion implantation using an N-type impurity, an N ⁺ -type diffusion region 14 serving as a source and a drain of the N-channel MOS transistor, an N ⁺ -type diffusion region 15 serving as an emitter of the NPN transistor, and a collector of the NPN transistor are provided. An N ⁺ type diffusion region 16 for ohmic contact on the surface of the region is formed.

Subsequently, by ion implantation using boron,
A P ⁺ -type diffusion region 17 serving as a source and a drain of the PchMOS transistor, and the P ⁺ -type diffusion region 18 serving as an external base region of the P-type base 12 surface of the NPN transistor, the surface of the P-well 5 of isolation P ⁺ The mold diffusion region 19 is formed.

Thereafter, a field oxide film 20 made of a CVD film is formed, and the source electrodes 21a and N of the NchMOS transistor are formed in the same manner as in a normal semiconductor device manufacturing method.
The drain electrode 21b of the chMOS transistor, Pch
Source electrode 22a of MOS transistor, PchMOS
Drain electrode 22b of transistor, emitter electrode 23a of NPN transistor, base electrode 23b of NPN transistor, collector electrode 23c of NPN transistor
Formed without forming an epitaxial layer
Complete the manufacture of semiconductor devices.

FIG. 5 is a sectional view showing a completed state of another conventional BiCMOS semiconductor device. The region of the MOS transistor is the same as that of FIG. In FIG. 5, reference numeral 9c denotes an N-type diffusion region formed on the surface of the N ⁻ -type well 3 serving as a collector region of the NPN transistor.

BiCMO without forming epitaxial layer
In the manufacture of S semiconductor devices, N^-Formed in mold well 3
The buried layer having a high concentration is often omitted. And that
Come, N ^-Since the well 3 also has a relatively low concentration,
The collector parasitic resistance of the transistor increases. for that reason,
In the conventional manufacturing method, the LOCOS oxide film 6 was formed.
Then, using a mask, the collector electrode of the NPN transistor
Implantation with N-type impurities only immediately below 23c
An N-type diffusion region 9c is formed. N-type diffusion region 9c
Is N^-Higher concentration than mold well 3 and formed later
N⁺It is formed at a position deeper than the mold diffusion region 16.

FIG. 6 shows a horizontal PNP bipolar transistor.
Built-in transistor (hereinafter abbreviated as PNP transistor)
Shows a completed state of another conventional BiCMOS semiconductor device.
It is sectional drawing. MOS transistor area is the same as in FIG.
Therefore, the description is omitted. In FIG. 6, 3 is a PchMO
N of S transistor^-P formed simultaneously with the mold well 2
N serving as a base region of an NP transistor^-Type well
15a is N which is a base region of the PNP transistor.
^-Ohmic contact provided on the surface of the mold well 3
N for⁺Type diffusion region, 18a is the PNP transistor
P to be a mitter ⁺Diffusion region, 18b is a PNP transistor
P to be the collector of the star⁺Type diffusion region, 24a is PNP
Transistor base electrode, 24b is a PNP transistor
24c is the collector of the PNP transistor.
Electrode.

In the following, PN without an epitaxial layer is formed.
A method for manufacturing a conventional BiCMOS semiconductor device incorporating a P transistor will be described.

First, an N ^- type well 2 is formed in a region to be a Pch MOS transistor in a semiconductor substrate 1 made of P-type silicon by using a mask,
N ^- type well 3 is formed in a region serving as a base of the NP transistor.
To form At the same time, a P-type well 4 is formed in a region to be an NchMOS transistor by using a mask,
A mold well 5 is formed.

Next, a LOCOS oxide film 6 for element isolation between the PchMOS transistor and the NchMOS transistor is formed by thermal oxidation. Since the region of the MOS transistor is the same as that of FIG. 4, some description is omitted. However, a gate oxide film 10 is provided, polycrystalline silicon containing phosphorus is deposited, and the gate electrode 11 is patterned by etching it. Further, a CVD film 13 is formed as a spacer on the side surface of the gate electrode 11. Also, by ion implantation using an N-type impurity, an N ⁺ -type diffusion region 14 serving as a source and a drain of the NchMOS transistor,
An N ⁺ -type diffusion region 15a for ohmic contact on the surface of the base region of the PNP transistor is formed.

Subsequently, by ion implantation using boron,
A P ⁺ -type diffusion region 17 serving as a source and a drain of the PchMOS transistor; a P ⁺ -type diffusion region 18a serving as an emitter of the PNP transistor; a P ⁺ -type diffusion region 18b serving as a collector of the PNP transistor; The P ⁺ -type diffusion region 19 on the surface of No. 5 is formed.

Thereafter, a field oxide film 20 made of a CVD film is formed, and a base electrode 24a of the PNP transistor, an emitter electrode 24b of the PNP transistor, and a collector electrode 24c of the PNP transistor are formed in the same manner as in a normal semiconductor device manufacturing method. And a BiCM incorporating a PNP transistor without forming an epitaxial layer.
The manufacture of the OS semiconductor device is completed.

The operation of the BiCMOS semiconductor device having no epitaxial layer formed as described above will be described below. In the conventional example of FIG.
The N ^- type well 3 serving as the collector region of the NPN transistor is formed by also using the step of forming the N ^- type well 2 in the S transistor region, thereby reducing the number of manufacturing steps. Pc
Easy control of threshold voltage of hMOS transistor and NPN
Since the N ⁻ -type wells 2 and 3 have a relatively low concentration in consideration of ensuring the withstand voltage of the transistor, the parasitic collector resistance of the NPN transistor is high.

FIG. 9 shows the distribution of the impurity concentration in the depth direction immediately below the collector electrode in the conventional example of FIG. 4, and the parasitic resistance of the collector is the N ⁺ type diffusion region 16 on the surface of the semiconductor substrate 1 which is shallow. It is determined by the concentration of the deep N ⁻ -type well 3 which is lower than the concentration. The current amplification factor, which is an important characteristic of an NPN transistor, is such that the emitter is Nch
Since the MOS transistor is formed by also using the process of forming the source and the drain, it is controlled by the impurity concentration and the thickness of the base.

In the conventional example of FIG. 5, the number of manufacturing steps is increased, but the N-type diffusion region 9 having a higher concentration than the N ⁻ -type well 3 is provided only under the collector electrode of the NPN transistor by using a mask.
c is formed to lower the collector resistance immediately below the collector electrode.

In the conventional example shown in FIG. 6, the step of forming the N ⁻ type well 2 in the Pch MOS transistor region is also
An N ⁻ -type well 3 serving as a base region of the NP transistor is formed to reduce the number of manufacturing steps. The current amplification factor of the PNP transistor is controlled by the impurity concentration of the base serving as the N ⁻ -type well 3 and the base width, that is, the distance between the emitter and the collector of the PNP transistor.

[0031]

However, in the conventional configuration as shown in FIG. 4 described above, in order to ensure the controllability of the threshold value of the PchMOS transistor and the breakdown voltage of the NPN transistor, the collector region of the NPN transistor is used. ^- since -type well 3 are relatively concentration low, NP
The parasitic collector resistance of the N transistor is high. As a result, the saturation voltage of the NPN transistor is high, and a large current cannot flow. Further, between the base of the NPN transistor and the substrate, the current amplification factor of the parasitic PNP transistor that operates based on the collector region of the low-concentration NPN transistor becomes large, and the integrated circuit is likely to malfunction.

Further, in the conventional configuration as shown in FIG.
An N-type diffusion region 9c having a higher concentration than the N ^-- type well 3 is formed just below the collector electrode of the N-transistor, and the concentration immediately below the collector electrode is increased to increase the parasitic collector resistance and the current amplification factor of the parasitic PNP transistor. But
The number of manufacturing steps is increasing, and the cost of the manufacturing method is high.

4 and 5, the distribution of impurity concentration in the depth direction immediately below the emitter of the NPN transistor is as shown in FIG. The concentration of the N ⁻ -type well 3 serving as the collector region of the NPN transistor is 1 × 10 ¹⁵ to
It is about 6 × 10 ¹⁶ , and the steepness of the impurity concentration distribution of the base is lost due to channeling that occurs when the base is formed by ion implantation with the P-type impurity and the redistribution of the impurity during the heat treatment. As a result, the width of the base also increases,
Current cut-off frequency f _T of the base transit time increases transistor during operation is reduced. Further, since the concentration of the N ⁻ -type well 3 is low, the base spreading effect is apt to be generated at the time of operation with a large current, and the current cutoff frequency f _T is further likely to be further reduced.

Further, in the conventional configuration as shown in FIG. 6, a parasitic PNP transistor operates between the substrate and the collector of the lateral PNP transistor as in FIG. 4, and a large current amplification factor causes a large leakage to the substrate. An electric current is generated. The conventional example has various problems as described above.

An object of the present invention is to solve the above-described conventional problems, and to reduce the parasitic collector resistance of a vertical bipolar transistor without forming an epitaxial layer.
Another object of the present invention is to provide a method for manufacturing a semiconductor device, which can reduce the manufacturing cost.

Another object of the present invention is to provide a method of manufacturing a semiconductor device having good frequency characteristics and a high current cutoff frequency.

Still another object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing a current amplification factor of a parasitic PNP transistor between a substrate and a collector of a lateral bipolar transistor to reduce a leakage current flowing to the substrate. It is to provide.

[0038]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a MOS transistor having a channel of a first conductivity type on a surface of a semiconductor substrate of a first conductivity type. Forming a first well of a second conductivity type for a MOS transistor in a semiconductor substrate and simultaneously forming a second conductivity type serving as a collector region of the vertical bipolar transistor in a semiconductor substrate. A first step of forming a second well of a second conductivity type, and forming a first diffusion region of a second conductivity type having a higher impurity concentration than the first well and a shallower diffusion depth by using a source of a MOS transistor in the first well. A second conductive layer which is formed immediately below a region where a drain diffusion region and a channel region are to be formed, and which has a higher impurity concentration than the second well and a shallower diffusion depth; And a second step of the second diffusion region formed immediately below the forming area of the ohmic contact impurity diffusion region of the collector region of the vertical bipolar transistor in the second well.

According to this method, the first diffusion of the second conductivity type is performed by ion implantation of impurities of the second conductivity type immediately below the source / drain diffusion region of the MOS transistor and the region where the channel region is to be formed in the first well. Using a manufacturing process for forming a region, a second conductive type of a second conductive type having a higher concentration than the second well is formed in the second well immediately below the region where the ohmic contact diffusion region is to be formed in the collector region of the vertical bipolar transistor. A second diffusion region is formed. This makes it possible to increase the impurity concentration immediately below the ohmic contact diffusion region in the collector region without adding a manufacturing process, thereby reducing the parasitic collector resistance. Therefore, the manufacturing cost can be kept low.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first aspect.
Simultaneously with the formation of the first diffusion region, a third diffusion region of the second conductivity type having a higher impurity concentration than the second well and a shallower diffusion depth is connected to the collector region of the vertical bipolar transistor in the second well. It is formed immediately below the region where the base region is to be formed on the surface and directly below the region where the emitter region is to be formed on the surface of the base region.

According to this method, the first diffusion of the second conductivity type is performed by ion implantation of impurities of the second conductivity type immediately below the source / drain diffusion region of the MOS transistor and the region where the channel region is to be formed in the first well. Using a manufacturing process for forming a region, a second bipolar transistor is formed just below a region where a base region is to be formed on a surface of a collector region of a vertical bipolar transistor and directly below a region where a emitter region is to be formed on a surface of a base region. Since the concentration of the collector at the junction between the base and the collector is increased by providing the diffusion region of No. 3, the base spreading effect that occurs at the time of a large current operation hardly occurs without adding a manufacturing process, and a high current cutoff frequency is obtained. can get.

Further, by providing the third diffusion region, the width of the base can be reduced, the base transit time during operation can be shortened, and the frequency characteristics of the transistor can be improved.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a MOS transistor having a first conductivity type channel and a lateral bipolar transistor are formed on a surface of a semiconductor substrate of a first conductivity type. So,
A first of a second conductivity type for a MOS transistor is provided on a semiconductor substrate.
A first step of forming a second well of the second conductivity type which becomes a base region of the lateral bipolar transistor at the same time as forming the second well, and a second conductive layer having an impurity concentration higher than the first well and a shallower diffusion depth. The first diffusion region of the type is formed immediately below the region where the source / drain diffusion region of the MOS transistor and the channel region are to be formed in the first well, and the impurity concentration is higher than the second well and the diffusion depth is shallower. A second step of forming a second diffusion region of the second conductivity type in the second well immediately below a region where the ohmic contact diffusion region, the emitter diffusion region and the collector diffusion region are to be formed in the base region of the lateral bipolar transistor; including.

According to this method, the first diffusion of the second conductivity type is performed by ion implantation of impurities of the second conductivity type immediately below the source / drain diffusion region of the MOS transistor and the region where the channel region is to be formed in the first well. Forming a second diffusion region in the second well immediately below a region where the ohmic contact diffusion region, the emitter diffusion region and the collector diffusion region are to be formed in the base region of the lateral bipolar transistor by using a manufacturing process for forming the region; Since the concentration of the base region of the lateral bipolar transistor is increased, the current amplification factor of the parasitic PNP transistor formed between the substrate and the collector of the lateral bipolar transistor can be reduced, and the leakage current can be reduced.

[0045]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view in the order of steps for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

First, as shown in FIG. 1A, using a mask, a (1) having a specific resistance of 10 to 20 Ω · cm containing a P-type impurity is used.
00) In the semiconductor substrate 1, an N ⁻ -type well 2 is implanted into a region to be a PchMOS transistor by ion implantation with phosphorus.
Is formed, an N ⁻ -type well 3 is formed in a region serving as a collector of the NPN transistor by ion implantation with phosphorus. Using a mask, a P-type well 4 is formed by ion implantation using boron in a region to be an NchMOS transistor, and a P-type well 5 is formed by ion implantation using boron in a region to be used for element isolation of a bipolar transistor. Thereafter, thermal diffusion is performed. At this time, the impurity concentration on the surfaces of the N ⁻ -type wells 2 and 3 and the P-type wells 4 and 5 is 1 × 10 ^{15 to} 6 × 10 ¹⁶ cm ⁻³ .

Next, a LOCOS oxide film 6 for element isolation between the PchMOS transistor and the NchMOS transistor is formed by thermal oxidation. The LOCOS oxide film 6 has a thickness of about 500 to 700 nm, and is also formed on a part of the surface of the collector region of the NPN transistor to become a field oxide film. Further, in order to adjust the threshold voltage of the MOS transistor to the N ^- type well 2 in the PchMOS transistor region and the P-type well 4 in the NchMOS transistor region, ion implantation using boron impurities is performed (FIG. 1A). Is omitted).

Thereafter, a resist 7 is applied to the entire surface, and the mask 7 is used to open the resist 7 on the PchMOS transistor region and on the region where the collector region electrode of the NPN transistor is to be provided. And 8 using phosphorus impurities
Ion implantation is performed at an energy of 0 keV to 200 keV to form an N-type diffusion region 8 near the surface of the N ⁻ -type well 2 of the PchMOS transistor and, at the same time, to form an N-type diffusion region 9 near the surface of the collector of the NPN transistor.

Thereafter, heat treatment is performed as annealing. At this time, the impurity concentration of the N-type diffusion regions 8 and 9 is 1 × 10 ¹⁷ to
The depth becomes 0.4 to 0.7 μm at about 4 × 10 ¹⁷ cm ⁻³ . The N-type diffusion region 8 is for preventing the withstand voltage between the drain and the source of the PchMOS transistor from being lowered by punch-through, and is expected to form a P ⁺ -type diffusion region (to be described later) serving as a source / drain and a channel region. It is formed immediately below the region. The N-type diffusion region 9 is formed immediately below a region where an N ⁺ -type diffusion region (described later) for ohmic contact of the collector region is to be formed.

Next, as shown in FIG. 1B, the resist 7 is removed, and a gate oxide film 10 having a thickness of about 7 to 30 nm is formed on the surface of the semiconductor substrate 1 other than the LOCOS oxide film 6 by thermal oxidation. Then, polycrystalline silicon having a thickness of 400 nm containing phosphorus is deposited and etched to pattern the gate electrode 11. The sheet resistance of the gate electrode 11 is 15 to 50 Ω / □.

Further, ion implantation using boron causes N
P-type base 1 on the surface of the collector region of the PN transistor
2 is formed, and polycrystalline silicon of the gate electrode 11 is oxidized by 10 to 30 nm by thermal oxidation. (Not shown in FIG. 1B) Next, as shown in FIG.
(Tetra-Ethyl-Ortho-Silica
te) 100-300n of CVD film utilizing thermal decomposition
m, and the entire surface is etched by using the RIE method.
Form 3 Although not shown in FIG. 1C, the CVD film 13 forms an N-type diffusion region in the N-channel MOS transistor region and a P-channel diffusion region in the P-channel MOS transistor region in order to prevent the short channel effect of the MOS transistor.
This spacer is used as a mask for ion implantation for forming the mold diffusion region.

Then, by ion implantation using arsenic,
An N ⁺ type diffusion region 14 serving as a source and a drain of the NchMOS transistor, an N ⁺ type diffusion region 15 serving as an emitter of the NPN transistor, and an N ⁺ type diffusion region 16 on the surface of the collector region of the NPN transistor for making ohmic contact; To form N ⁺ type diffusion region 16
Is formed immediately above the N-type diffusion region 9.

Subsequently, by ion implantation using boron,
P ⁺ -type diffusion region 17 serving as a source and a drain of a PchMOS transistor, and P ⁺ -type diffusion region 18 serving as an external base region on the surface of base 12 of an NPN transistor
And a P ⁺ type diffusion region 1 on the surface of a P type well 5 for element isolation.
9 are formed. P ⁺ type diffusion region 17 is provided immediately above N type diffusion region 8.

Further, by including a heat treatment, the N ⁺ type diffusion region 14 and the N
⁺ Type diffusion region 15 has a surface impurity concentration of 2 × 10 ²⁰ c
The depth is about 0.2 to 0.3 μm at about m ⁻³ . Also, P
⁺ Type diffusion regions 17 and 18 have a surface impurity concentration of 2 × 10
^The depth is about 0.3 to 0.4 μm at about ²⁰ cm ⁻³ .

Next, as shown in FIG. 1D, a field oxide film 20 made of a CVD film is formed, and the source electrode 21a of the NchMOS transistor and the drain electrode of the NchMOS transistor are formed in the same manner as in a normal semiconductor device manufacturing method. 21b, source electrode 22a of PchMOS transistor, drain electrode 22 of PchMOS transistor
b, NPN transistor emitter electrode 23a, NPN
The base electrode 23b of the transistor and the collector electrode 23c of the NPN transistor are formed to complete the manufacture of the BiCMOS semiconductor device according to the first embodiment of the present invention.

The operation of the semiconductor device thus configured according to the first embodiment of the present invention will be described below.

First, in such a manufacturing method, an N ⁻ -type well 3 serving as a collector region of an NPN transistor is also used without forming an epitaxial layer and further, forming an N ⁻ -type well 2 in a PchMOS transistor region. It is needless to say that the number of manufacturing steps is small and the cost is low. However, since the N ⁻ -type well 3 in the collector region of the NPN transistor has a relatively low concentration, the parasitic collector resistance is high. If this is solved by adding a manufacturing process, the cost will be high.

Therefore, the drain of the PchMOS transistor is
The breakdown voltage between the in and source is reduced by punch through
From 80 keV to 20
Ion implantation at an energy of 0 keV
N of Lanista^-N type diffusion region near the surface of the type well 2
8, without increasing the number of manufacturing steps. ^-
Near the surface of the region just below the collector electrode in the mold well 3
N-type diffusion region 9 is added beside to reduce parasitic collector resistance.
Comb.

FIG. 7 shows the distribution of the impurity concentration in the depth direction immediately below the collector electrode 23c in the first embodiment of the present invention. As shown in FIG.
1 × 10 ¹⁷ to between the low-concentration N ⁻ -type well 3 as the collector region of the transistor and the N ⁺ -type diffusion region 16 on the surface.
The concentration of the collector region can be increased by adding the N-type diffusion region 9 having a depth of about 4 × 10 ¹⁷ cm ⁻³ and a depth of 0.4 to 0.7 μm.

Therefore, the parasitic collector resistance of the NPN transistor is reduced, the saturation voltage of the NPN transistor is also low, and a large current can flow.

Further, as shown in FIG. 11, by surrounding N-type diffusion region 9 and N ⁺ diffusion region 16 around P-type base 12, the impurity concentration in the base region of the lateral parasitic PNP transistor can be increased. , Lateral parasitic PNP
The current amplification factor of the transistor decreases. FIG. 11 (a)
Shows a plan view of an NPN transistor region, and FIG. 4B shows a cross-sectional view taken along line aa of FIG.

The lateral parasitic PNP transistor is NP
The P-type base 12 of the N transistor is used as an emitter, and N ⁻
The mold well 3 is used as a base, and the P-type well 5 is used as a collector. As the parasitic PNP transistor, a vertical PNP transistor (having the semiconductor substrate 1 as a collector) also exists in a distributed manner, but the current amplification factor of a parasitic PNP transistor obtained by combining a vertical transistor and a horizontal transistor is as follows. It decreases along with the decrease in the horizontal direction.

As described above, the parasitic collector resistance and the saturation voltage of the NPN transistor can be reduced without using the process of the PchMOS transistor in the first embodiment and increasing the manufacturing cost.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention for each process.
The present invention is different from the first embodiment shown in FIG. 1 in that an N-type diffusion region 9b is formed in an N ⁻ -type well 3 in a collector region of an NPN transistor.
Are given with the same numbers used in FIG.

[0067] First, as shown in FIG. 2 (A), the semiconductor substrate 1 of P-type, N in a region to be a PchMOS transistor ^- simultaneously makes a type well 2, N in a region to be a collector of the NPN transistor ^- -type well Form 3
At the same time as forming the P-type well 4 in the region to be the N-channel MOS transistor, the P-type well 5 is formed in the region to become the element isolation of the bipolar transistor.

Next, a LOCOS oxide film 6 for element isolation between the PchMOS transistor and the NchMOS transistor is formed by thermal oxidation. Thereafter, a resist 7 is applied to the entire surface, and the resist 7 on the PchMOS transistor region, on the region where the electrode of the collector region of the NPN transistor is provided, and on the emitter region of the NPN transistor formed in a later process is opened using a mask. Let it.

Then, 80 keV using the impurity of phosphorus
Ion implantation with energy of 200 keV from Pch
MOS transistor N^-N type near the surface of mold well 2
A diffusion region 8 is formed, and a collector of the NPN transistor is formed.
An N-type diffusion region 9a is formed near the surface, and
The base formed in a later step and N^-Junction of mold well 3
Then, an N-type diffusion region 9b is formed. The N-type diffusion region 8 is
P to be the source and drain⁺Mold diffusion region (described later) and
It is formed immediately below a region where a channel region is to be formed. Also,
The N-type diffusion region 9a is an ohmic contact of the collector region.
N⁺Immediately below the region where the mold diffusion region (described later) is to be formed
Is formed. The N-type diffusion region 9b ^-In mold well 3
Of the surface of the collector region of the NPN transistor in
Base area immediately below the area to be formed
Just below the area where the emitter region (described later) is to be formed on the surface of
It is formed.

Next, as shown in FIG. 2B, a gate oxide film 10 having a thickness of about 7 to 30 nm is formed on the surface of the semiconductor substrate 1, and polycrystalline silicon containing phosphorus having a thickness of 400 nm is formed. Deposit and etch it to form the gate electrode 11
Is patterned. Further, a P-type base 12 is formed on the surface of the N ⁻ -type well 3 which is the collector region of the NPN transistor by ion implantation using boron.

Next, as shown in FIG. 2C, a CVD film is deposited on the entire surface, and a CVD film 13 is formed as a spacer on the side surface of the gate electrode 11 by RIE.

Then, by ion implantation using arsenic,
An N ⁺ -type diffusion region 14 serving as a source and a drain of an Nch MOS transistor, an N ⁺ -type diffusion region 15 serving as an emitter of an NPN transistor, and an N ⁺ -type diffusion region 16 for ohmic contact on the surface of the collector region of the NPN transistor Form. The N ⁺ type diffusion region 16
It is formed immediately above the mold diffusion region 9. N ⁺ type diffusion region 15
Are formed directly above the N-type diffusion region 9b.

Subsequently, by ion implantation using boron,
P ⁺ -type diffusion region 17 serving as a source and a drain of a PchMOS transistor, and P ⁺ -type diffusion region 18 serving as an external base region on the surface of base 12 of an NPN transistor
And a P ⁺ type diffusion region 1 on the surface of a P type well 5 for element isolation.
9 are formed. P ⁺ type diffusion region 17 is provided immediately above N type diffusion region 8.

Next, as shown in FIG.
A field oxide film 20 composed of a film is formed, and the source electrode 21a of the NchMOS transistor, the drain electrode 21b of the NchMOS transistor, the source electrode 22a of the PchMOS transistor, and the drain electrode 2 of the PchMOS transistor are formed in the same manner as in a normal semiconductor device manufacturing method.
2b, emitter electrode 23a of NPN transistor, NP
The base electrode 23b of the N transistor and the collector electrode 23c of the NPN transistor are formed to complete the manufacture of the BiCMOS semiconductor device according to the second embodiment of the present invention.

The operation of the semiconductor device thus configured according to the second embodiment of the present invention will be described below.

First, FIG. 8 shows the distribution of the impurity concentration in the depth direction immediately below the emitter according to the second embodiment of the present invention. PchMOS transistors the N ^- without increasing also serves as a step of forming an N-type diffusion region 8 production process in the vicinity of the surface of the type well 2, N ^- the type well 3,
N ⁺ type diffusion region 1 which is an emitter of NPN transistor
The N-type diffusion region 9b is formed in a region immediately below the base region 5 and directly below the base region, and the collector concentration at the junction between the P-type base 12 and the N-type diffusion region 9b immediately below the emitter is 1 × 10 ^{15 to} 6 × 10 ¹⁶ cm ^-3 to 1 × 10
It is increased to about ¹⁷ to 4 × 10 ¹⁷ cm ⁻³ .

For this reason, channeling that occurs when the base is formed by ion implantation hardly occurs, and the redistribution of impurities during annealing or heat treatment hardly occurs. Therefore, the distribution of the impurity concentration in the base is steep. be able to.
Due to the high concentration of the collector, the width of the base is reduced for the same base concentration. Therefore, the base transit time during operation is shortened, and the frequency characteristics of the NPN transistor can be improved. Further, since the concentration of the collector is high, the base spreading effect hardly occurs at the time of operation with a large current, and the current cutoff frequency f _T is increased. Further, since the concentration of the collector immediately below the emitter is high, the parasitic collector resistance can be reduced.

As described above, the frequency characteristics of the NPN transistor can be improved and the current cutoff frequency can be increased without increasing the manufacturing cost by also using the process of the PchMOS transistor in the second embodiment. Can be.

Hereinafter, a third embodiment of the present invention will be described.
This will be described with reference to the drawings.

FIG. 3 is a sectional view showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention for each step.
The present invention differs from the first embodiment shown in FIG. 1 in that a lateral PNP transistor is incorporated as a bipolar transistor, and common points are given the same reference numerals used in FIG. Detailed explanation is omitted.

[0081] First, as shown in FIG. 3 (A), N in a region to be a PchMOS transistor on a semiconductor substrate 1 of P type ^- at the same time to form a type well 2, N in a region to be a base of the PNP transistor ^- -type well 3 To form Also, N
At the same time as forming the P-type well 4 in a region to be a chMOS transistor, a P-well 5 is formed in a region for element isolation of a bipolar transistor.

Next, the PchMOS transistor and Nc
A LOCOS oxide film 6 for element isolation of the hMOS transistor is formed. Thereafter, a resist 7 is applied to the entire surface, and a PNP is formed over the PchMOS transistor region using a mask.
The resist 7 on the base region of the transistor is opened.

Then, 80 keV using the impurity of phosphorus
Ion implantation with energy of 200 keV from Pch
An N-type diffusion region 8 is formed near the surface of the N ^- type well 2 of the MOS transistor, and an N-type diffusion region 9d is formed near the surface of the base of the PNP transistor. N-type diffusion region 8
Are formed immediately below a P ⁺ type diffusion region (to be described later) serving as a source / drain and a region where a channel region is to be formed.
Further, N-type diffusion region 9d is, N ^- P in the mold well 3
An NP transistor is formed immediately below an ohmic contact diffusion region (described later), an emitter diffusion region (described later), and a collector diffusion region (described later) of a base region (described later).

Next, as shown in FIG. 3B, a gate oxide film 10 having a thickness of about 7 to 30 nm is formed on the surface of the semiconductor substrate.
Is formed, polycrystalline silicon containing phosphorus having a thickness of 400 nm is deposited, and is etched to pattern the gate electrode 11. A CVD film is deposited on the entire surface, and CVD is used as a spacer on the side surface of the gate electrode 11 by using the RIE method.
A film 13 is formed.

Then, an N ⁺ -type diffusion region 14 serving as a source and a drain of the NchMOS transistor and an N ⁺ -type diffusion region 15a for ohmic contact provided on the surface of the base region of the PNP transistor are formed. Also, P
P ⁺ serving as source and drain of chMOS transistor
A P ⁺ -type diffusion region 18a serving as an emitter, a P ⁺ -type diffusion region 18b serving as a collector, and a P ⁺ -type diffusion region 18b serving as a collector are formed on the surface (directly above) of the N-type diffusion region 9d in the base region of the PNP transistor. A P ⁺ type diffusion region 19 on the surface of the P type well 5 is formed.

Next, as shown in FIG.
A field oxide film 20 composed of a film is formed, and the source electrode 21a of the NchMOS transistor, the drain electrode 21b of the NchMOS transistor, the source electrode 22a of the PchMOS transistor, and the drain electrode 2 of the PchMOS transistor are formed in the same manner as in a normal semiconductor device manufacturing method.
2b, PNP transistor base electrode 24a, PNP
The emitter electrode 24b of the transistor and the collector electrode 24c of the PNP transistor are formed to complete the manufacture of the BiCMOS semiconductor device according to the third embodiment of the present invention.

The operation of the semiconductor device thus configured according to the third embodiment of the present invention will be described below.

In the third embodiment, the step of forming the N-type diffusion region 8 near the surface of the N ⁻ -type well 2 of the PchMOS transistor is also used, without complicating the manufacturing process.
An N-type diffusion region 9d having a higher concentration than that of the N ^- type well 3 is formed in a region serving as a base of the PNP transistor to reduce the current amplification factor of a parasitic PNP transistor that operates between the substrate and the collector of the PNP transistor. And a large leakage current to the substrate hardly occurs. Therefore, malfunction of the integrated circuit using the third embodiment is suppressed.

As described above, the current amplification factor of the parasitic PNP transistor can be reduced without increasing the manufacturing cost by also using the process of the PchMOS transistor in the third embodiment.

In the first and second embodiments, the P-type base 12 of the NPN transistor is formed after patterning the gate electrode 11, but the P-type base 12 is formed in this order. It may not be necessary, for example, before the field oxide film 20 is deposited.
Further, in the first to third embodiments, the semiconductor substrate 1 is made of P-type silicon. However, N-type silicon may be used, or a semiconductor substrate bonded on an oxide film may be used.

[0091]

As described above, according to the method of manufacturing a semiconductor device according to the first aspect, the first semiconductor substrate is formed on the surface of the same semiconductor substrate.
In a method of manufacturing a semiconductor device in which a MOS transistor having a conductivity type channel and a bipolar transistor are formed, an impurity of a second conductivity type is formed in a first well immediately below a source / drain diffusion region of a MOS transistor and a region where a channel region is to be formed. Using a manufacturing process of forming a first diffusion region of the second conductivity type by ion implantation, a second well is formed in the collector region of the vertical bipolar transistor immediately below the region where the diffusion region for ohmic contact is to be formed. Since the second diffusion region of the second conductivity type having a higher concentration than that of the well is formed, the impurity concentration immediately below the ohmic contact diffusion region in the collector region can be increased without increasing the manufacturing cost. A bipolar transistor with low collector resistance and low saturation voltage Door can be.

Further, according to the method of manufacturing a semiconductor device according to the second aspect of the present invention, the second conductivity type impurity is located immediately below the source / drain diffusion region and the channel region of the MOS transistor in the first well. Using a manufacturing process of forming a first diffusion region of the second conductivity type by ion implantation of the second conductivity type, a portion of the surface of the collector region of the vertical bipolar transistor in the second well immediately below the region where the base region is to be formed and the base region By providing the third diffusion region just below the region where the emitter region is to be formed on the surface of the substrate, the concentration of the collector at the junction between the base and the collector is increased. The resulting base spreading effect is less likely to occur, and a high current cutoff frequency can be obtained, and the base width can be reduced, thus improving the frequency characteristics. Door can be.

Further, according to the method of manufacturing a semiconductor device according to the third aspect of the present invention, the second conductivity type impurity is formed immediately below the source / drain diffusion region and the channel region of the MOS transistor in the first well. Of a diffusion region for an ohmic contact, an emitter diffusion region, and a collector diffusion region in a base region of a lateral bipolar transistor in a second well by using a manufacturing process of forming a first diffusion region of a second conductivity type by ion implantation of By providing the second diffusion region immediately below the predetermined region, the concentration of the base region of the lateral bipolar transistor is increased, so that the parasitic PN formed between the substrate and the collector of the lateral bipolar transistor can be achieved without increasing the manufacturing cost.
The current amplification factor of the P transistor can be kept low, the leakage current can be reduced, and malfunction of the integrated circuit can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.

FIG. 4 is a sectional view showing a completed state of a semiconductor device in a first conventional example.

FIG. 5 is a sectional view showing a completed state of a semiconductor device in a second conventional example.

FIG. 6 is a sectional view showing a completed state of a semiconductor device in a third conventional example.

FIG. 7 is a schematic diagram showing a distribution of an impurity concentration of the bipolar transistor according to the first embodiment of the present invention.

FIG. 8 is a schematic diagram showing a distribution of impurity concentration of a bipolar transistor according to a second embodiment of the present invention.

FIG. 9 is a schematic diagram showing a distribution of impurity concentration of a bipolar transistor in the first conventional example.

FIG. 10 is a schematic diagram showing an impurity concentration distribution of a bipolar transistor in a second conventional example.

FIG. 11A shows that the N-type diffusion region and the N ⁺ -type diffusion region are P-type.
FIG. 2B is a plan view of the NPN transistor region surrounding the mold base, and FIG. 2B is a cross-sectional view taken along the line aa of FIG.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 N ^- type well 3 N ^- type well 4 P-type well 5 P-type well 6 LOCOS oxide film 7 resist 8 N-type diffusion region 9 N-type diffusion region 9a N-type diffusion region 9b N-type diffusion region 9c N-type Diffusion region 9d N-type diffusion region 10 Gate oxide film 11 Gate electrode 12 P-type base 13 CVD film 14 N ⁺ type diffusion region 15 N ⁺ type diffusion region 15a N ⁺ type diffusion region 16 N ⁺ type diffusion region 17 P ⁺ type diffusion Region 18 P ⁺ -type diffusion region 18a P ⁺ -type diffusion region 18b P ⁺ -type diffusion region 19 P ⁺ -type diffusion region 20 Field oxide film 21a Source electrode of NchMOS transistor 21b Drain electrode of NchMOS transistor 22a Source electrode of PchMOS transistor 22b PchMOS transistor Of the NPN transistor 23b Base electrode of NPN transistor 23c Collector electrode of NPN transistor 24a Base electrode of PNP transistor 24b Emitter electrode of PNP transistor 24c Collector electrode of PNP transistor

 ──────────────────────────────────────────────────続 き Continued on front page F-term (reference) 5F048 AA01 AA05 AA09 AA10 AC05 BA01 BB05 BD00 BD04 BE01 BE02 BE03 BF03 BG12 BH01 CA00 CA01 CA12 DA06 DA13 DA14 DA15 DA25 5F082 AA16 AA26 BA00 BA02 BA04 BA23 BC10 BC09 EA09 EA

Claims (3)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: forming a MOS transistor having a channel of a first conductivity type and a vertical bipolar transistor on a surface of a semiconductor substrate of a first conductivity type; Forming a first well of the second conductivity type at the same time as forming a first well of the second conductivity type,
Forming a first diffusion region of a second conductivity type having an impurity concentration higher than that of the first well and a shallower diffusion depth than a source region of the MOS transistor in the first well. At the same time as forming immediately below the region where the drain diffusion region and the channel region are to be formed, the second conductivity type second diffusion region having a higher impurity concentration and a lower diffusion depth than the second well is formed in the second well. Forming the collector region of the vertical bipolar transistor immediately below the region where the diffusion region for ohmic contact is to be formed. 2. The method according to claim 2, wherein simultaneously with forming the first diffusion region, the second diffusion region has a higher impurity concentration than the second well and a shallower diffusion depth.
A third diffusion region of a conductivity type is formed in the second well immediately below the region where the base region is to be formed on the surface of the collector region of the vertical bipolar transistor and in the region where the emitter region is to be formed on the surface of the base region. 2. The method according to claim 1, wherein the semiconductor device is formed immediately below. 3. A method of manufacturing a semiconductor device in which a MOS transistor having a channel of a first conductivity type and a lateral bipolar transistor are formed on a surface of a semiconductor substrate of a first conductivity type, the method comprising the steps of: A first step of forming a first well of the second conductivity type and simultaneously forming a second well of a second conductivity type to be a base region of the lateral bipolar transistor; and an impurity concentration higher than that of the first well. A first diffusion region of a second conductivity type having a high diffusion depth and a shallow depth is formed in the first well immediately below a source / drain diffusion region of the MOS transistor and a region where a channel region is to be formed. Forming a second diffusion region of a second conductivity type, which is higher in diffusion depth and shallower in diffusion depth than the second well, in the lateral well in the second well; Ohmic contact impurity diffusion region of the base region of La transistor, a method of manufacturing a semiconductor device and a second step of forming immediately below the forming area of the emitter diffusion region and a collector diffusion region.