JPH0271526A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to isolate between a collector and a substrate without lowering withstand voltage and also without increasing the thickness of an epitaxial layer by a method wherein a one-conductivity type region and a first opposite conductivity type region are formed successively on the surface of the prescribed region of a one-conductivity type substrate, a second opposite conductivity type region is formed on the other prescribed region, and an opposite conductivity type epitaxial layer is formed on the surface of the substrate. CONSTITUTION:An SiO2 film 30 is formed on a p-type substrate 29, and injection windows 31 and 32 are formed. Then, injection regions 33 and 34 are formed by injecting ions. Subsequently, an arsenic implantation region 35 is formed by implanting arsenic into silicon from the injection window 32 provided on the region where an n-p-n transistor is formed. Then, n-type regions 36 and 37 are formed on the phosphorus-implantation regions 33 and 34 by conducting a prescribed heat treatment. Also, an n<-> type region 38 is formed on the arsenic-ion implantation region 35. Then, boron implanting windows 39 and 40 are formed using photolithographic technique, boron is ion-implanted and boron-implanted regions 41 and 42 are formed. Subsequently, p<+> buried regions 43 and 44 are formed on the boron-implanted regions 41 and 42. Then, an n-type epitaxial layer 45 is formed thereon. As a result, high withstand voltage can be obtained on the collector 38 and the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to high speed bipolar pnp transistors, npn
The present invention relates to a structure and manufacturing method for forming transistors on the same substrate.

2. Prior Art A conventional manufacturing method for forming bipolar pnp transistors and npn transistors on the same substrate is shown in FIGS. 3A and 3B.

NPN transistor on p-type silicon substrate 1, pnp
5x10I5ions/
Ci ions are implanted and heat treated at 1200° C. for 1 hour to form n+ type buried regions 2 and 3 with a diffusion depth of 1.5 μm. Then, 5 boron was added to the pnp transistor and isolation region forming region.
X 10 1ons/ci ion implantation is performed. and p
Epitaxial layer 4 with a shape of 0.5 Ωμm and a thickness of 3 to 4 μm
form. Then, the epitaxial layer in the isolation region is changed to the SiO□ film 5 using a selective oxidation method. At the same time, boron in the region where boron was ion-implanted is diffused, and p
+ type pnp transistor collector region 6 and p+
A shaped separation channel stopper region 7 is formed (FIG. 3A).

Next, boron is added to the collector contact region of the pnp transistor at 5×10 +ons/c+j, n p
Phosphorus is ion-implanted at 5×10 15 ions/ci into the collector contact region of the n transistor and heat treated to form a p+ type region 8 and an n+ type region 9, respectively. Next, 5 x 10 +ons/- boron ions are implanted simultaneously into the emitter region of the pnp transistor and the graft base region of the npn transistor, and heat treatment is performed to form a p+ type emitter region 10 with a depth of 0.8 μm and a p type graft base. Region 11 is formed.

Also, in the base region of the npn transistor, 2×10
A p-type base region 12 is formed by implanting +ons/cd of boron ions and performing heat treatment. and 7 x 10 in the base contact area of the pnp transistor and the emitter area of the npn transistor.
A base contact region 13.+ons/c- is implanted and heat treated to form a base contact region 13. with a depth of 0.3 μm. An emitter region 14 is formed (FIG. 3B).

In the above process, the collector region 6 of the pnp) transistor
By heat treatment, boron is diffused to form a p+ layer region with a thickness of 1 μm and a sheet resistance of approximately 1 Ω/hole.

Problems to be Solved by the Invention In the above process, boron is diffused into the epitaxial layer and p
A thick epitaxial layer is required to form the positive region 6. In this case, the thickness of the 5 inch 2 separation membrane 5 becomes thicker. Therefore, the width of the bird's beak during selective oxidation is W
There is a problem that the separation width becomes larger.
Furthermore, as the thickness of the Si 02 film 5 increases, crystal defects occur more frequently, resulting in an increase in pn junction leakage current.

Furthermore, since the p++-containing region 7 and the n++-containing region 3 are in contact with each other, there is a problem that the breakdown voltage between the collector and the substrate is deteriorated.

In order to avoid the above problems, SiO
□If the n++-containing region 3 is not formed directly under the film 5, a problem arises in that the hFE of the parasitic pnp transistor in which the graft base region 11 is the emitter, the epitaxial layer 4 is the base, and the substrate 1 is the collector becomes large.

Furthermore, as shown in FIG.
There is a problem in that if the separation is made apart, the separation width becomes wider.

Means for Solving the Problems The technical means of the present invention for solving the above problems is to form a region of one conductivity type and a first region of the opposite conductivity type in a predetermined region of a semiconductor substrate of one conductivity type in this order from the surface. a second opposite conductivity type region is formed in another predetermined region, and an opposite conductivity type epitaxial layer is formed on the substrate surface;
A bipolar transistor having the one conductive shadow region as a collector and a bipolar transistor having the second opposite conductivity type region as a collector are formed.

For production The effect of this technical means is as follows.

That is, the thickness of the epitaxial layer (npn
A transistor and a pnp transistor can be formed on the same substrate. Further, separation between the collector and the substrate can be formed without causing a decrease in breakdown voltage. Furthermore, a pnl)Tnpn transistor with good high frequency characteristics can be obtained.

Embodiments Embodiment 1 A method for forming an npn transistor and a pnp transistor on the same substrate will be described below as a first embodiment of the present invention with reference to FIG.

First, a p-type 10Ωμm substrate 29 was heated to a thickness of 0 by thermal oxidation.
．． A 5in2 film 30 of 6 μm is formed, and the Sin film 31 in the pnp transistor (npn) transistor forming region is removed by photoetching to form injection windows 31 and 32. Then add 60ke of phosphorus into the exposed silicon.
, 5×10 +ons/cd ions are implanted to form implanted regions 33,34. Then, using a photoresist film as a mask, a 60k histogram was deposited in the silicon within 0.5 to 1 μm from the injection window 32 in the npn transistor formation region.
ey.

5.times.1015.1 ons/cl ion implantation is performed to form a hypothetical implant region 35 (FIG. 1A).

Next, heat treatment at 1200°C for 30 minutes results in phosphorus injection region 33
．． 34, n-shaded regions 36 and 37 with a diffusion depth of approximately 1.8 μm are formed. Further, in the Hiso ion implantation region 35, an n+ type region 38 with a diffusion depth of 0.8 μm is formed (FIG. 1B).
.

Next, the area other than the collector region and element isolation region of the PNP transistor is covered with a photoresist film using photolithography, the exposed 5in2 film 30 is removed, boron implantation windows 39 and 40 are formed, and I
d, boron is ion-implanted at 60 keV to form boron implanted regions 41 and 42 (FIG. 1C).

Next, by heat treatment at 1000° C. for 30 minutes, the boron implanted regions 41.42 form p++-containing regions 43.44 with a diffusion depth of about 0.8 μm. and n-type 0.1~0.6Ω
μm, and an epitaxial layer 45 with a thickness of 2 μm is formed (
Figure 1 D).

Next, a 50 nm thick SiO2 film, a 120 nm thick S
i, N411! Form I. Then, using a photoetch technique, the Si, N4 film, and 5in2 film in the isolation region are removed, and the epitaxial layer is further etched to a thickness of 1 μm. Then, using the Si3N4 film as a mask, high-pressure oxidation was used to
A 5i02 film 46 of 2 .mu.m is formed at .degree. And Si,
Remove N4 film and pad S i O2 film (Fig. 1E)
.

Next, using the photoresist film as a mask, 5×10 +ons was applied to the collector contact area of the npn transistor.
/cd of phosphorus and 5 x 10 +ons/cd of boron into the collector contact region of the pnp transistor;
Heat treatment is performed to form an n+ type region 47p+ type region 48. Then, using a photoresist film as a mask, 3×10”1ons/c was applied to the base region of the NPN transistor.
d boron is implanted to form a base region 49, and pnp
5 X 1014 ions/in the emitter region of the transistor and the graft base region of the npn transistor
The emitter region 50 is implanted with boron ions of cIll.
, forming a graft base region 51. 7 more
pn by ion implantation of 10+ons/cd
P transistor base contact region 52, npn
Forming the emitter region of the transistor (Fig. 1F)
.

In the above step, the distance fl1x between the base 49 and the n+ buried 38 is set so that the BVCEO of the npn transistor is equal to or higher than a predetermined voltage (for example, equal to or higher than 5V). That is, the voltage until the distance X of the n layer is depleted and the breakdown electric field strength is reached is a predetermined voltage Bvc. Anything above that is fine. On the other hand, Bvc of a pnp transistor. is the voltage at which the region of base width y is completely depleted, and Bvc8o of the pnp transistor is lower.

Therefore, the thickness of the epitaxial layer is determined by the emitter depth of the pnp transistor and the base width to obtain a predetermined BVoEo.

Further, in the above process, the impurity concentration of the p+ buried layer 43 is not very high, so boron hardly diffuses into the epitaxial layer 45. Moreover, since the p+ type collector region is formed under the epitaxial layer, a thin epitaxial layer is sufficient. Therefore, the collector resistance of the npn transistor does not increase and a transistor with good high frequency characteristics can be obtained.

Further, since the p+ buried 44 and the n buried 37 with a low impurity concentration are formed directly under the isolation 5i0246, a high withstand voltage of 20 V or more can be obtained between the collector 38 and the substrate. Moreover, since the N-buried layer 37 serves as the base region of the parasitic PNP transistor in which the graft base 51 of the NPN transistor has the emitter collector 47 as the base and the substrate 29 as the collector, the base width is wide (and hFE is small).

Example 2 A second embodiment is shown in FIG.

In the first embodiment, 5 to 10×10” phosphorus was applied to the emitter regions of both the pnp and npn transistors.
By implanting s/cni and performing heat treatment, it is diffused to the bottom of the epitaxial layer 45 to form phosphorus diffusion regions 60.61. Then, emitter regions 50 and 53 are formed in the same manner as in the first embodiment.

In this case, since the impurities in the base region directly under the emitter 50 of the pnp transistor are high, the base region is not completely depleted even if the voltage between the collector and emitter is increased.

That is, even if the base width e is made smaller, a predetermined BvCEO can be obtained. Therefore, the epitaxial layer can be made thinner by an amount corresponding to the smaller base width e. Furthermore, since the base width e is small, a transistor with high f can be obtained.

Since the resistance of the epitaxial layer under the base region 49M of the npn transistor is low, the collector resistance becomes small.
A transistor with good high frequency characteristics can be obtained.

Furthermore, since both transistors have an n-type epitaxial layer with a high impurity concentration only directly below the emitter region, the base,
Since the increase in pn junction capacitance between the collectors is small, there is no deterioration in high frequency characteristics due to an increase in parasitic capacitance.

In the first and second embodiments described above, both pnp and npn transistors can be formed on the same substrate without increasing the thickness of the epitaxial layer. Therefore, the thickness of the isolation 5in2 film can be made thinner, which prevents the isolation width from increasing due to the intrusion of bird's beaks, and prevents the occurrence of crystal defects due to oxidation, which prevents a decrease in LSI yield due to pn junction leakage current. be able to.

Furthermore, the npn transistor has a low impurity concentration 0 layer 3
7 is in contact with the p-type substrate 29, so there is a p
Since the n-junction capacitance is small, the high frequency characteristics of the npn transistor are good.

Effects of the Invention According to the present invention, both pnp and npn transistors with good high frequency characteristics can be formed on the same substrate.

In addition, the withstand voltage between the collector and substrate of the npn transistor is high (and isolation between elements can be formed in which the hFE of the parasitic pnp transistor does not increase).

Furthermore, since the epitaxial layer is thin, the separation width does not become large, making it possible to create a high-density LSI.
A high-yield LSI with less n-junction leakage can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional flowchart of the manufacturing process of the first embodiment of the present invention, FIG. 2 is a cross-sectional structure diagram showing the second embodiment of the present invention, and FIG. 3 is a diagram showing the manufacturing process of a conventional bipolar transistor. Cross-sectional view, Figure 4. FIG. 5 is a cross-sectional structural diagram of a conventional transistor. 36.37...embedding, 38...n+embedding, 43.44...p+embedding, 45...
・Epitaxial layer, 46...5in2 for separation
film, 50... emitter of pnp transistor,
53... Emitter of npn transistor, 60
．． 61...N layer formed by phosphorus implantation. Name of agent: Patent attorney Shigetaka Awano and one other person 6θ2/

Claims (5)

[Claims] (1) One conductivity type region and a first opposite conductivity type region are formed in order from the surface in a predetermined region of a one conductivity type semiconductor substrate, and a second opposite conductivity type region is formed in another predetermined region. an epitaxial layer of opposite conductivity type is formed on the surface of the substrate, and a bipolar transistor having the one conductivity type region as a collector and a bipolar transistor having the second opposite conductivity type region as a collector are formed. A semiconductor integrated circuit characterized by: (2) A first opposite conductivity type region is formed in a predetermined region of one conductivity type semiconductor substrate, and a predetermined region within the first opposite conductivity type region has a lower conductivity than the first opposite conductivity type. A second conductivity type opposite to that of the semiconductor substrate is formed, an epitaxial layer of the opposite conductivity type is formed on the surface of the substrate, and a second conductivity type having a resistivity lower than that of the semiconductor substrate is formed immediately below the element isolation insulating film. A semiconductor integrated circuit characterized in that a conductivity type region and the first opposite conductivity type region are formed. (3) Both pnp and npn transistors, a first bipolar transistor based on an epitaxial layer of opposite conductivity type and a second bipolar transistor serving as a collector, are formed on the same substrate, and under the emitter region of the first transistor and A semiconductor integrated circuit characterized in that an epitaxial layer of an opposite conductivity type under an emitter region of a second transistor has a resistivity lower than epitaxial layers in other regions. (4) a step of introducing a first opposite conductivity type forming impurity into a first predetermined region of a semiconductor substrate of one conductivity type to form a first region; a step of introducing an impurity for forming an opposite conductivity type to form a second region;
introducing a first opposite conductivity type forming impurity into a predetermined region of the first region and an element isolation region formation region to form third and fourth regions; a step of forming an epitaxial layer region on at least the fourth region as an insulating film, a bipolar transistor forming an emitter of one conductivity type epitaxially on a predetermined region of the third region; forming a bipolar transistor having an emitter of an opposite conductivity type in an epitaxial layer on a predetermined region of the region. (5) A claim characterized in that it has a step of introducing an opposite conductivity type impurity into an epitaxial layer in an emitter formation region of a bipolar transistor so as to increase the opposite conductivity type impurity more than other epitaxial layers. The method for manufacturing a semiconductor integrated circuit according to item 4.