JPH0621077A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device and a method for manufacturing the same which can easily form the device in which high frequency characteristics are satisfactory at a high speed. CONSTITUTION:When boron is ion implanted in a predetermined region 9 to be formed with an emitter layer and annealed, the boron is diffused to a predetermined region 41 to be formed with a base layer. Then, when arsenic is ion implanted, an emitter layer 13 and a collector layer 15 are formed. In this case, since the arsenic has larger diffusion coefficient than that of the boron, a base layer 11 is so formed in a self-alignment manner as to protrude from the P-type emitter layer 13. Thus, the base layer of a thickness corresponding to a difference of diffusing speeds can be formed in a self-alignment manner.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to improvement of its operating speed and performance.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit,
An epitaxial growth layer is formed on a silicon substrate, and a circuit is formed on this epitaxial growth layer. By the way, in such a structure, the silicon substrate and the epitaxial growth layer form a PN junction and have a capacitance. The capacitance of the PN junction reduces the operating speed of the device. Therefore, the structure is not suitable for forming an element that requires high-speed operation.

In order to solve this problem, an SOI (Semiconductor on Insulator) substrate in which a silicon single crystal layer is further formed on an insulating layer on a silicon substrate has been provided in recent years. In the SOI substrate, the silicon single crystal layer can be insulated from the silicon substrate. Therefore, by forming the lateral bipolar transistor in the silicon single crystal layer, the PN junction between the semiconductor element formed in the silicon single crystal layer and the silicon substrate can be eliminated.

FIG. 5 shows a method of manufacturing the lateral bipolar transistor 31 using the SOI substrate 4. Figure A shows
The SOI substrate 4 is shown. The SOI substrate 4 is the silicon substrate 2
A silicon oxide film (SiO ₂ ) 3, which is an insulating layer, is formed on top of the above. A single crystal silicon layer 5 is further formed on the silicon oxide film 3.

Next, a photoresist 7 is applied to the surface of the SOI substrate 4 and patterned as shown in FIG. 3B to form an opening 8. After that, from the substrate surface B
Ion-implant ⁺ (boron).

After removing the photoresist 7 shown in FIG.
A photoresist 8 is newly applied to the surface of the SOI substrate 4 and patterned as shown in FIG. 6C to form an opening 10. After that, P ⁺ (phosphorus) is ion-implanted from the substrate surface.

Next, after removing the photoresist 23 shown in FIG. 1C, annealing is performed to form the P-type base layer 11, the N-type collector layer 15 and the emitter layer 13. After that, collector layer 1
5, electrodes are formed on the emitter layer 13 and the base layer 11 (not shown), and the lateral bipolar transistor 31 is completed.

[0008]

However, the lateral bipolar transistor 31 as described above has the following problems. The width W of the base layer 11 is determined by the patterning width of the photoresist 7. Reducing the width of this patterning has a limit (about 1 μm) from the alignment tolerance and the processing accuracy. Therefore, there is a limit to narrowing the width W of the base layer 11. Therefore, the operation speed is slow and the high frequency characteristics are not good.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and provide a semiconductor device having a high speed and good high frequency characteristics and a manufacturing method capable of easily manufacturing the semiconductor device.

[0010]

A semiconductor device according to a first aspect of the present invention is a semiconductor device formed on a thin film semiconductor layer on an insulating layer, both of which include a first conductivity type emitter layer and a collector layer, and the emitter. A base layer of a second conductivity type disposed between a layer and a collector layer, and a semiconductor device in which the second conductivity type base layer is disposed laterally in the thin film semiconductor layer, in the emitter layer formation planned region or the collector layer formation planned region. , The first impurity and the second impurity having a diffusion coefficient larger than that of the first impurity are injected and diffused to form the diffusion region of the first impurity as an emitter layer or a collector layer, and protrude from the diffusion region of the first impurity. The second impurity diffusion region is used as the base layer.

A semiconductor device according to a second aspect is characterized in that an intermediate layer having an impurity concentration lower than that of the collector layer is provided between the base layer and the collector layer.

A semiconductor device according to a third aspect is characterized in that a high-concentration layer for taking out a base electrode is provided beside the base layer.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a first impurity and a second impurity having a diffusion coefficient larger than that of the first impurity are added to the emitter layer formation scheduled region or the collector layer formation scheduled region. Implanting and diffusing to form an emitter layer or a collector layer with the first impurity diffusion region, and forming the base layer with a second impurity diffusion region protruding from the first impurity diffusion region. To do. A method of manufacturing a semiconductor device according to a fifth aspect of the present invention includes a step of forming an intermediate layer having an impurity concentration lower than that of the collector layer between the base layer and the collector layer.

A method of manufacturing a semiconductor device according to a sixth aspect of the invention is characterized by including a step of forming a protective film on the predetermined base layer region to prevent ion implantation.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises a step of forming a protective film on the base layer formation-scheduled region and the intermediate layer formation-scheduled region to prevent impurity implantation. To do.

A method of manufacturing a semiconductor device according to an eighth aspect of the present invention is characterized by including a step of forming a high concentration layer for taking out the base electrode, beside the base layer.

[0017]

In the semiconductor device or the method for manufacturing the same according to any one of claims 1 and 4, a first impurity and a diffusion coefficient larger than that of the first impurity in the emitter layer formation planned region or the collector layer formation planned region. The second impurity is injected and diffused. Then, the emitter layer or the collector layer is formed by the first impurity diffusion region, and the base layer is formed by the second impurity diffusion region protruding from the first impurity diffusion region. Therefore, the base layer having a thickness corresponding to the difference in diffusion coefficient can be formed in a self-aligned manner.

In the semiconductor device or the method for manufacturing the same according to claims 2 and 5, an intermediate layer having an impurity concentration lower than that of the collector layer is provided between the base layer and the collector layer. Therefore, this intermediate layer can be used as a withstand voltage region between the base layer and the collector layer.

In the semiconductor device and the manufacturing method thereof according to the third and eighth aspects, a high-concentration layer for taking out the base electrode is formed beside the base layer. Therefore,
Even if the width of the base layer is small, the base electrode can be reliably connected to the base layer. Further, the base electrode and the base layer can be connected even if the impurity concentration of the base layer is lowered.

In the method of manufacturing a semiconductor device according to the sixth aspect, the protection film protects the base layer planned region from being doped with impurities. Therefore, by diffusion, a base layer having a thickness corresponding to the difference in diffusion coefficient is formed in a lower region of the protective film in a self-aligned manner.

In the method of manufacturing a semiconductor device according to the seventh aspect, the protective film protects the base layer formation-scheduled region and the intermediate layer formation-scheduled region from being implanted with impurities. Therefore, by diffusion, a base layer and an intermediate layer having a thickness corresponding to the difference in diffusion coefficient are formed in a lower region of the protective film in a self-aligned manner.

[0022]

FIG. 4 shows a lateral bipolar transistor which is an embodiment of the present invention. Note that FIG. 4A is a cross-sectional view taken along line XX of FIG.

In this lateral bipolar transistor, the insulating layer 3 is formed on the silicon substrate 2, the thin film semiconductor layer 5 is formed on the insulating layer 3, and the thin film semiconductor layer 5 is made of N ^+. Shaped emitter layer 1
3, a P-type base layer 11, an N-type intermediate layer drift region 14, and an N ⁺ -type collector layer 15 are provided side by side in the lateral direction. In the present specification,
The lateral direction means a direction orthogonal to the depth direction of the thin film semiconductor layer 5.

An emitter electrode 43 and a collector electrode 45 are connected to the emitter layer 13 and the collector layer 15, respectively. The emitter layer 13, the base layer 11, the drift region 14, and the collector layer 15 are covered with the silicon oxide film 46.

Further, as shown in FIG.
1 is provided with P ^{+ -type} external base layers 52 and 53 which are high-concentration layers for taking out the base electrodes 54 and 55. Note that in this specification, “horizontal” means that the thin film semiconductor layer is positioned in a direction orthogonal to the depth direction.

The manufacturing process of this lateral bipolar transistor will be described with reference to FIGS. 2A shows SO
The I substrate 4 is shown. The SOI substrate 4 has a silicon oxide film 3 as an insulating layer formed on a silicon substrate 2. On the silicon oxide film 3, a single crystal silicon layer 5 which is a thin film semiconductor layer is further formed. In this embodiment, the SOI substrate 4 is formed by depositing a silicon oxide film on the silicon substrate 2 to a thickness of 500 nm and then growing single crystal N-type silicon (Si) to a thickness of 200 nm.

Next, a photoresist is patterned on the surface of the SOI substrate 4, and element isolation is performed by the LOCOS method. As a result, the field oxide layer 23 is formed as shown in FIG. Next, after cleaning the substrate, a 500 nm silicon oxide film is deposited by the CVD method. Then, etching is performed while leaving only the upper portion of the region 36, whereby the silicon oxide film 33 as a protective film is formed. Further, the silicon oxide film 34 is grown to 100 nm by thermal oxidation (at 900 ° C. for 30 minutes) (FIG. 7C).

Thereafter, as shown in FIG. 1A, the collector layer formation planned region 37 is covered with a resist 39, and the emitter layer formation planned region 9 is ion-implanted with B ⁺ (boron) as a second impurity. Here, the region 36 and the collector layer formation planned region 37 are covered with the silicon oxide film 33 and the resist 39, respectively. Therefore, ion implantation is not performed in the region 36 and the collector layer formation planned region 37.

In this embodiment, the ion implantation is performed with an acceleration energy of 50 KeV and a dose of 5 * 10 ^12.
It was performed under the condition of cm ^-2 .

After that, the implanted boron is activated by performing the first annealing. Since boron has a large diffusion coefficient, the implanted boron diffuses up to the base layer formation scheduled region 41 as shown in FIG.

Next, as shown in FIG. 6C, the photoresist 39 is removed, and the first impurity As ⁺ (arsenic) is ion-implanted from the surface of the SOI substrate 4. At that time, since the region 36 is covered with the silicon oxide film 33, ion implantation is not performed. In this embodiment, the ion implantation is performed with an acceleration energy of 50 KeV and a dose amount of 5 * 1.
It was carried out under the condition of 0 ¹⁵ cm ^-2 . Then, the implanted arsenic is activated by performing a second annealing. Thereby, the P-type emitter layer 13 and the collector layer 15 are formed.

By the way, the diffusion coefficient of boron is larger than that of arsenic. Therefore, even if the second annealing is performed, the implanted arsenic does not diffuse to the region where the base layer is to be formed. In this way, the P-type emitter layer 13
The N-type base layer 11 protruding from is formed in a self-aligned manner. The width D of the base layer 11 can be controlled almost accurately by controlling the annealing condition, so that the thin base layer 11 can be formed.

Further, the drift region 14 is formed in a self-aligned manner in a portion of the region 36 where the base layer 11 is not formed. The impurity concentration of the drift region 14 is the initial substrate concentration, and is lower than the impurity concentration of the collector layer 15. Therefore, the drift region 14 can be used as a withstand voltage region between the base layer 11 and the collector layer 15.

Next, the external base layers 52 and 53 (see FIG. 4B)
(Refer to FIG. 3) will be described. 3A is a line Y- of FIG. 4B.
It is sectional drawing in Y. A region other than the region where the external base layer is to be formed is covered with a resist and B ⁺ ions are implanted as shown in FIG. 3A. In this embodiment, the ion implantation is performed with an acceleration energy of 50 KeV and a dose of 1 * 10 ¹⁵ c.
It was carried out under the condition of m ^-2 . After that, the implanted boron is the third
Is activated by annealing.

As described above, by providing the high-concentration layer for taking out the base electrodes 54 and 55 beside the base layer 11, the base electrode can be easily formed even if the width D of the base layer 11 is small. . Furthermore, even if the impurity concentration of the base layer 11 is lowered, the base electrode and the base layer 11 can be reliably connected. Therefore, a higher speed lateral bipolar transistor can be provided.

Next, as shown in FIG. 9B, a 500 nm silicon oxide film is deposited by the CVD method. After that, an opening 63 for the emitter electrode and an opening 65 for the collector electrode are formed as shown in FIG. Similarly, an opening for a base electrode is also formed in the external base layer (not shown).

Finally, aluminum is deposited on the entire surface and patterned (not shown) to complete the lateral bipolar transistor.

In this embodiment, the annealing is performed twice, after the ion implantation of boron as the second impurity and after the ion implantation of arsenic as the first impurity. However, the present invention is not limited to this. For example, after ion implantation of boron as the second impurity and ion implantation of arsenic as the first impurity, annealing may be performed collectively.

Further, in this embodiment, after ion implantation of boron which is the second impurity into the region 9 where the emitter layer is to be formed, ion implantation of arsenic which is the first impurity is performed. However, without being limited to this, the second impurity, boron, may be ion-implanted after the first impurity, arsenic, is ion-implanted.

In this embodiment, arsenic is used as the first impurity and boron is used as the second impurity. However, the present invention is not limited to this, and any diffusion coefficient may be used. May be, for example,
Antimony (Sb) may be adopted as the first impurity and boron may be adopted as the second impurity.

In addition, although a single transistor has been described in this embodiment, it may be configured as an integrated circuit including a lateral bipolar transistor.

[0042]

According to the semiconductor device or the method of manufacturing the same according to any one of claims 1 and 4, in the emitter layer formation planned region or the collector layer formation planned region, a diffusion coefficient of the first impurity and the first impurity is higher than that of the first impurity. Is injected and diffused. Then, the emitter layer or the collector layer is formed by the first impurity diffusion region, and the base layer is formed by the second impurity diffusion region protruding from the first impurity diffusion region. Therefore, the base layer having a thickness corresponding to the difference in diffusion coefficient can be formed in a self-aligned manner. As a result, it is possible to provide a high-speed semiconductor device having excellent high-frequency characteristics and a manufacturing method capable of easily manufacturing the semiconductor device.

In the semiconductor device or the method of manufacturing the same according to the second and fifth aspects, an intermediate layer having an impurity concentration lower than that of the collector layer is provided between the base layer and the collector layer. Therefore, this intermediate layer can be used as a withstand voltage region between the base layer and the collector layer.
This makes it possible to provide a semiconductor device having a high withstand voltage between the base layer and the collector layer.

In the semiconductor device or the manufacturing method thereof according to the third and eighth aspects, a high-concentration layer for taking out the base electrode is formed beside the base layer. Therefore,
Even if the width of the base layer is small, the base electrode can be easily formed. Further, even if the impurity concentration of the base layer is lowered, the base electrode and the base layer can be reliably connected.

In the method of manufacturing a semiconductor device according to the sixth aspect, the protection film protects the base layer planned region from being doped with impurities. Therefore, by diffusion, the base layer can be formed in a lower region of the protective film in a self-aligned manner. This makes it possible to easily manufacture a semiconductor device which has high speed and good high frequency characteristics.

In the method of manufacturing a semiconductor device according to the seventh aspect, the protection film protects the base layer formation-scheduled region and the intermediate layer formation-scheduled region from being doped with impurities. Therefore, the base layer and the intermediate layer can be formed in the lower region of the protective film in a self-aligned manner by diffusing. This makes it possible to easily manufacture a semiconductor device which has high speed and good high frequency characteristics.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a lateral bipolar transistor according to the present invention.

FIG. 2 is a diagram showing a manufacturing process of a lateral bipolar transistor according to the present invention.

FIG. 3 is a diagram showing a manufacturing process of a lateral bipolar transistor according to the present invention.

FIG. 4 is a diagram showing a lateral bipolar transistor according to the present invention.

FIG. 5 is a diagram showing a manufacturing process of a conventional lateral bipolar transistor 31.

[Explanation of symbols]

 3 ... Insulating layer 11 ... Base layer 13 ... Emitter layer 14 ... Drift layer 15 ... Collector layer 33 ... Silicon oxide film 52, 53 ... External base layer

Claims (8)

[Claims] 1. A semiconductor device formed on a thin-film semiconductor layer on an insulating layer, which comprises an emitter layer and a collector layer of a first conductivity type, and a second layer disposed between the emitter layer and the collector layer. In a semiconductor device in which a conductivity type base layer is laterally arranged in the thin film semiconductor layer, a diffusion coefficient of a first impurity and a diffusion coefficient of the first impurity in the emitter layer formation planned region or the collector layer formation planned region is formed. By injecting and diffusing a second impurity having a large
A semiconductor device, wherein the first impurity diffusion region is an emitter layer or a collector layer, and the second impurity diffusion region protruding from the first impurity diffusion region is the base layer. 2. The semiconductor device according to claim 1, wherein an intermediate layer having an impurity concentration lower than that of the collector layer is provided between the base layer and the collector layer. 3. The semiconductor device according to claim 1, wherein a high-concentration layer for taking out a base electrode is provided beside the base layer. 4. A method for manufacturing a semiconductor device on a thin film semiconductor layer on an insulating layer, the method comprising: a first conductivity type emitter layer and a collector layer; and a first conductive type emitter layer and a collector layer disposed between the emitter layer and the collector layer. In a method of manufacturing a semiconductor device, in which a two-conductivity-type base layer is arranged in the thin film semiconductor layer in a direction orthogonal to the depth direction of the thin film semiconductor layer, the emitter layer formation planned region or the collector layer formation planned region is provided. Of the first impurity and a second impurity having a diffusion coefficient larger than that of the first impurity are implanted and diffused to form an emitter layer or a collector layer by the first impurity diffusion region. A method of manufacturing a semiconductor device, characterized in that the base layer is formed by a protruding second impurity diffusion region. 5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of forming an intermediate layer having an impurity concentration lower than that of the collector layer between the base layer and the collector layer. Manufacturing method of semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 4, further comprising the step of forming a protective film on the planned base layer region to prevent impurity implantation. . 7. The method for manufacturing a semiconductor device according to claim 5, further comprising: forming a protective film on the base layer formation scheduled region and the intermediate layer formation scheduled region to prevent impurity implantation. A method for manufacturing a characteristic semiconductor device. 8. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of forming a high-concentration layer for taking out a base electrode beside the base layer.