JPS5837990B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS5837990B2 JPS5837990B2 JP14836380A JP14836380A JPS5837990B2 JP S5837990 B2 JPS5837990 B2 JP S5837990B2 JP 14836380 A JP14836380 A JP 14836380A JP 14836380 A JP14836380 A JP 14836380A JP S5837990 B2 JPS5837990 B2 JP S5837990B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- oxidation
- semiconductor substrate
- manufacturing
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 230000003647 oxidation Effects 0.000 claims description 34
- 238000007254 oxidation reaction Methods 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 28
- 239000012535 impurity Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 3
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000009931 harmful effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 150000003863 ammonium salts Chemical class 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000002485 combustion reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- GALOTNBSUVEISR-UHFFFAOYSA-N molybdenum;silicon Chemical compound [Mo]#[Si] GALOTNBSUVEISR-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
この発明は半導体装置の製造力法に係り、特に絶縁物に
よる素子分離技術に好適な半導体装置の製造力法Ｏこ関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing semiconductor devices, and particularly to a method for manufacturing semiconductor devices suitable for element isolation technology using insulators.
半導体集積回路【こおける分離技術（こ関しては高集積
化、製造プロセスの容易化を図るものとして一般（こ分
離領域を選択酸化技術｛こよって形或した酸化膜を使用
するものが知られている。Isolation technology in semiconductor integrated circuits (semiconductor integrated circuits) is generally used to increase the integration density and simplify the manufacturing process. ing.
この力式｛こよれば、能動領域の周囲が酸化膜Ｏこよっ
て取り囲まれているため、ベース拡散等（こおいてセル
ファライメントが可能で従来のようなマスク合せのため
の不要な部分が省略でき、高集積化が可能となり、また
側面が深い酸化膜（こより構威されたことＱこより接合
容量は桁違いに減少する。This force formula {Accordingly, since the active region is surrounded by the oxide film O, base diffusion, etc. (self-alignment is possible here, and unnecessary parts for mask alignment as in the conventional method are omitted) This makes it possible to achieve high integration, and since the sides are formed with a deep oxide film (Q), the junction capacitance is reduced by an order of magnitude.
しかし、この方式ではシリコン基板中【こ熱酸化膜を選
択的（こ埋没させる構造のため、シリコン基板（こ大き
な歪が生じ、かつ酸化誘起積層欠陥も発生しやすく素子
の電気的特性を劣化させ、耐酸化性マスクの構造、構戒
、膜厚及び選択酸化条件、時にはシリコン基板そのもの
の材料自身の選択に著しい制限を与えている。However, since this method selectively buries the thermal oxide film in the silicon substrate, it causes large distortions in the silicon substrate, and is also prone to oxidation-induced stacking faults, deteriorating the electrical characteristics of the device. This places significant restrictions on the structure, composition, film thickness and selective oxidation conditions of the oxidation-resistant mask, and sometimes on the selection of the material of the silicon substrate itself.
これは、例えば文献ＩＥＤＭＨｉｇｈ Ｐｒｅｓｓｕｒ
ｅ Ｏｘｉｄａｔｉｏｎ ｆｏｒＩ ｓｏｌａｔｉｏｎ
ｏｆ Ｈｉｇｈ Ｓｐｅｅｄ Ｂ ｉｐｏｌａｒＤｅ
ｖｉｃｅｓ １ ９ ７ ９年ｐｐ３４０ 〜３４３に
記載されている。This can be seen for example in the document IEDM High Pressur
e Oxidation for Isolation
of High Speed BipolarDe
Vices 1979, pp. 340-343.
また、絶縁物（こよる素子分離技術ではフィールド酸化
時間が長いため、それがチャンネルストツパの不純物層
の拡散、再分布｛こ与える影響は著しく太きい。In addition, since the field oxidation time is long in device isolation technology using insulators, this has a significant effect on the diffusion and redistribution of the impurity layer of the channel stopper.
例えば、横力向への拡散が太きいとＭＯＳトランジスタ
の実効チャンネル巾は減少しドレイン接合容量は増大す
るので高速デバイス実現に大きな障害になる。For example, if the diffusion in the direction of lateral force is large, the effective channel width of the MOS transistor will decrease and the drain junction capacitance will increase, which will be a major hindrance to realizing high-speed devices.
又、酸化膜中ヘの不純物の再分布の効果を考えてイオン
注入のドーズ量を大きくしたり加速電圧を高くしたり加
速電圧を高くしたりしなければならず、イオン注入の損
傷｛こよる歩留りの低下が生じる。In addition, considering the effect of redistribution of impurities in the oxide film, it is necessary to increase the ion implantation dose, increase the acceleration voltage, or increase the acceleration voltage, which may cause ion implantation damage. A decrease in yield occurs.
又窒化膜をマスクにして熱酸化を行なうと１ホワイトリ
ボン“と称するシリコンナイトライドが窒化膜の下のシ
リコン基板中（こ形或され、これが素子の耐圧不良の原
因となる。Furthermore, when thermal oxidation is performed using the nitride film as a mask, silicon nitride, called a "white ribbon", is formed in the silicon substrate under the nitride film, which causes a breakdown voltage failure of the device.
本発明は、上記点に鑑みなされたもので、半導体基板に
前記半導体基板より酸化速度の速い材料層を形或する工
程と、この酸化速度の速い材料層上に部分的に耐酸化マ
スクを形成する工程と、この耐酸化マスクをマスクとし
て素子形或予定領域上の前記酸化速度の速い材料層を酸
化し酸化膜を形或する工程と、前記耐酸化マスクを除去
する工程と、前記酸化膜を不純物ドーピングマスクとし
て前記半導体基板へ不純物をドープする工程と、前記酸
化膜を厚さ力向に少なくとも一部除去する工程と、残っ
た酸化速度の速い材料層を酸化する工程と、前記素子形
或予定領域上の酸化膜を少なくとも一部除去し前記半導
体基板面を露出させる工程を有すること（こよって半導
体基板に欠陥が少なく電気特性の良い半導体装置の製造
力法を提供することを目的とするものである。The present invention has been made in view of the above points, and includes a step of forming a layer of a material having a faster oxidation rate than the semiconductor substrate on a semiconductor substrate, and forming an oxidation-resistant mask partially on the material layer having a faster oxidation rate. a step of oxidizing the material layer with a high oxidation rate on a device shape or a planned region using the oxidation-resistant mask as a mask to form an oxide film; a step of removing the oxidation-resistant mask; and a step of removing the oxidation film. doping an impurity into the semiconductor substrate using an impurity doping mask; removing at least a portion of the oxide film in the thickness direction; oxidizing the remaining material layer with a high oxidation rate; a step of removing at least a portion of the oxide film on a certain predetermined region to expose the surface of the semiconductor substrate (thus, the purpose is to provide a method for manufacturing a semiconductor device with few defects on the semiconductor substrate and good electrical characteristics); It is something to do.
以下、実症例｛こ従って本発明を詳細に説明する，第１
図ａ〜ｉは本発明を詳細｛こ説明するための断面概略図
である。Hereinafter, an actual case {therefore, the present invention will be explained in detail, Part 1
Figures a to i are schematic cross-sectional views for explaining the present invention in detail.
まず、第１図ａに示すように半導体基板例えばｎ型の単
結晶シリコン基板１の表面に絶縁層例えば厚さ１０００
λの熱酸化膜２を形戊する。First, as shown in FIG.
A thermal oxide film 2 of λ is formed.
本発明ではｎ型単結晶シリコン基板で説明するがｐ型単
結晶シリコン基板でも可能であり、さら（こは化合物半
導体でも可能である。In the present invention, an n-type single-crystal silicon substrate will be described, but a p-type single-crystal silicon substrate may also be used, and a compound semiconductor may also be used.
また前記酸化膜２は必らずしも形成されなくてもよ０）
。Furthermore, the oxide film 2 does not necessarily have to be formed0)
.
そして熱酸化膜２の上｛こ酸化速度の速い材料層例えば
厚さ０．４μｍの多結晶シリコン膜をＰＯＣｌｓ雰囲気
中下気相成長させ、高濃度Ｑこリンを含んだ多結晶シリ
コン層３を形成する。Then, on the thermal oxide film 2, a material layer having a high oxidation rate, for example, a polycrystalline silicon film with a thickness of 0.4 μm, is grown in a lower vapor phase in a POCls atmosphere to form a polycrystalline silicon layer 3 containing a high concentration of Q-phosphorus. Form.
多結晶シリコンの代わり｛こモリブデンシリサイ．ドあ
るいはタングステンシリサイドを使用しても良い。An alternative to polycrystalline silicon (molybdenum silicon). Alternatively, tungsten silicide or tungsten silicide may be used.
また高濃度不純物としてリン以外（こボロン砒素等を使
用することも可能である。Further, it is also possible to use other than phosphorus (boron, arsenic, etc.) as a high concentration impurity.
さら｛こ前記高濃度不純物を含有する多結晶シリコン成
長時（こ同時に前記不純物を添加して形戊することもで
きる。Furthermore, during the growth of polycrystalline silicon containing impurities at a high concentration, the impurities can be added at the same time to shape the polycrystalline silicon.
次（こ第１図ｂ（こ示すようＱこ窒化シリコン膜を気相
或長Ｑこより１０００λ被着した後、フォトエッチング
プロセス（こよりパターニングし、残された窒化シリコ
ン膜を耐酸化マスク４とする。Next (as shown in Figure 1b), after depositing a silicon nitride film with a length of 1000λ in the vapor phase, patterning is carried out by a photo-etching process, and the remaining silicon nitride film is used as an oxidation-resistant mask 4. .
次いで第１図Ｃ｛こ示すように前記窒化シリコン膜４を
マスクとして多結晶シリコン層３を選択酸化する。Next, as shown in FIG. 1C, the polycrystalline silicon layer 3 is selectively oxidized using the silicon nitride film 4 as a mask.
多結晶シリコン層を酸化すること｛こより膜厚約９００
０人の厚い酸化膜６が形或される。Oxidizing the polycrystalline silicon layer {thickness approximately 900 mm
A thick oxide film 6 is formed.
次に第１図ｄｌこ示すように耐酸化マスク４を例えばプ
ラズマエッチングＱこよって除去した後厚い酸化膜６を
マスクとしてイオン注入を行ない、基板と同一導電導型
の不純物層を形戊しチャンネルストツパ５とする。Next, as shown in FIG. 1dl, after removing the oxidation-resistant mask 4 by, for example, plasma etching, ions are implanted using the thick oxide film 6 as a mask to form an impurity layer of the same conductivity type as the substrate, forming a channel. Set the stopper to 5.
この場合、耐酸化マスク除去前｛こイオン注入してもよ
い。In this case, ions may be implanted before removing the oxidation-resistant mask.
例えばイオンとしてリンをイオン注入するのであればリ
ンをドーズ量４Ｘ１０１２／ｉで３６０Ｋｅｙのエネル
ギでイオン注入する。For example, if phosphorus is to be implanted as ions, phosphorus is ion-implanted at a dose of 4×10 12 /i and an energy of 360 keys.
次に第１図ｅに示すように厚い酸化模６をフフ化アンモ
ニア液｛こより除去すると、端の傾斜がなだらかな多結
晶シリコン層３が残る。Next, as shown in FIG. 1e, when the thick oxide pattern 6 is removed using a fluorinated ammonium solution, a polycrystalline silicon layer 3 with gently sloped edges remains.
ここで酸化膜６を厚さ男向に薄く残すと、最終的｛こ素
子分離領域の酸化膜８が厚く形成される。If the oxide film 6 is left thinner in the direction of thickness, the oxide film 8 in the element isolation region will eventually be formed thicker.
又第１図ａの工程で酸化膜２を形或しない場合、部残っ
た酸化膜６が後の工程で残った多結晶シリコン層３を低
湿燃焼酸化する時に、半導体基板１の酸化防止の役割を
する。In addition, if the oxide film 2 is not formed in the process shown in FIG. do.
この残った多結晶シリコンを低温燃焼酸化例えば温度８
５０℃で３００分の時間で酸化すると第１図Ｎこ示すよ
う｛こ膜厚約０．９μｍの端の形のなだらかな厚い酸化
膜８が形或される。This remaining polycrystalline silicon is oxidized by low-temperature combustion, for example, at a temperature of 8.
When oxidized at 50 DEG C. for 300 minutes, a thick, smooth oxide film 8 in the shape of an edge with a film thickness of about 0.9 .mu.m is formed as shown in FIG.
この時同時にシリコン基板（こ食い込んだ酸化膜７例え
ば食い込み約８００λ、全膜厚約２７００人を除去する
と、第１図ｇに示すように、膜厚約０．６μｍの絶縁酸
化膜８に囲まれた半導体基板面が得られる。At this time, if the silicon substrate (for example, the intruded oxide film 7 with a depth of about 800λ and a total film thickness of about 2700 mm) is removed, the silicon substrate will be surrounded by an insulating oxide film 8 with a thickness of about 0.6 μm as shown in A semiconductor substrate surface is obtained.
その後、この半導体基板面Ｑこ酸化、拡酸等一連の処理
を行い。After that, a series of treatments such as oxidation and acid expansion were performed on the surface of this semiconductor substrate.
ＭＯＳトランジスタ、バイポーラトランジスタ等の半導
体素子を形或する。Forms semiconductor elements such as MOS transistors and bipolar transistors.
例えばＭＯＳＩ−ランジスタであれば第１図ｈ｛こ示す
ように熱酸化によりゲート酸化膜９を厚さ１０００人で
形或する。For example, in the case of a MOSI transistor, the gate oxide film 9 is formed to a thickness of 1000 mm by thermal oxidation as shown in FIG.
次（こ多結晶シリコン膜を気相成長し不純物をドープレ
、フォトリソグラフをこよりゲート電極１０を形成する
。Next, this polycrystalline silicon film is grown in a vapor phase, doped with impurities, and then photolithography is performed to form a gate electrode 10.
次（こ基板１と反対導電型の不純物をイオン注入し熱処
理を行いソース１１，ドレイン１２を形成する。Next, impurities of the opposite conductivity type to the substrate 1 are ion-implanted and heat treated to form a source 11 and a drain 12.
最後｛こ第１図ｉ（こ示すよう｛こ絶縁用ＣＶＤシリコ
ン酸化膜１３を或長させ、ソース１１，ドレイン１２へ
の電極取り出し孔をフォトリングラフＱこより形威し、
アルミニウム等の金属膜Ｑこよる配線１４．１５をパタ
ーニングＱこより配設して完或する。Finally, as shown in FIG.
Wiring lines 14 and 15 made of a metal film Q such as aluminum are provided by patterning Q to complete the process.
従って、本発明｛こよれば多結晶シリコンを酸化して厚
い酸化膜を形或するため、シリコン基板Ｏこはストレス
が加わらず、又半導体基板を直接厚く酸化しないので酸
化誘起積層欠陥の発生も防止でき、良好な特性を有す半
導体素子が形威され、信頼性、歩留り共Ｑこ高い半導体
装置の製造法が得られる。Therefore, according to the present invention, since polycrystalline silicon is oxidized to form a thick oxide film, stress is not applied to the silicon substrate, and since the semiconductor substrate is not directly oxidized thickly, the occurrence of oxidation-induced stacking faults is also avoided. A method of manufacturing a semiconductor device with high reliability and high yield can be obtained, in which a semiconductor element with good characteristics can be produced.
耐酸化マスクとして、窒化シリコンのみからなる層を使
用できるのでパースピークの長さが小さくなり高集積化
ｔこ有利である。Since a layer made only of silicon nitride can be used as the oxidation-resistant mask, the length of the perspective peak becomes smaller, which is advantageous for higher integration.
さらＱこ、従来の選択酸化法と異りホワイトリボンが多
結晶シリコン上｛こできるため、その弊害を考慮しなく
て済む。Furthermore, unlike the conventional selective oxidation method, a white ribbon is formed on the polycrystalline silicon, so there is no need to consider its harmful effects.
同時（こ多結晶シリコンＱこは不純物が高濃度に拡散さ
れており、フィールド酸化が低漉短時間で済むため、経
済性が向上すると共Ｑこ熟的ストレス｛こよる弊害を防
ぐことができそれＧこ加え、チャンネルストツパの横力
向拡散は小さくなるのでＭＯＳトランジスタにおいて実
効チャネル巾が大きく、ドレイン接合容量は小さくなり
高速化が可能となる。At the same time (polycrystalline silicon Q), impurities are diffused at a high concentration, and field oxidation can be done in a short time, which improves economic efficiency and prevents the harmful effects of polycrystalline stress. In addition to this, the lateral force diffusion of the channel stopper is reduced, so the effective channel width of the MOS transistor is increased, the drain junction capacitance is reduced, and high speed operation is possible.
又半導体基板は酸化されないので不純物の再分布Ｑこよ
る酸化膜へのとり込まれは少なくてすみ、従ってイオン
注入のドーズ量が少なくてすむのでイオン注入Ｏこよる
損傷は小さく歩留りを高くすることができる。In addition, since the semiconductor substrate is not oxidized, impurities are less likely to be incorporated into the oxide film due to redistribution Q, and therefore the dose of ion implantation can be reduced, so damage caused by ion implantation O can be minimized and the yield can be increased. I can do it.
さらＱこ、端の傾斜のなだらかな酸化膜をマスク｛こチ
ャネルストッパーイオン注入を行うためソース，ドレイ
ン近労のチャネルストッパー不純物濃度は小さく、ドレ
イン接合容量を小さくできる。Furthermore, since channel stopper ion implantation is performed using an oxide film with a gentle slope at the end, the concentration of the channel stopper impurity near the source and drain is small, and the drain junction capacitance can be reduced.
かつ、絶縁酸化端はなだらかな形状を持ち、断切れの発
生しＱこくい半導体装置の製造力法を提供することがで
きる。In addition, the insulating oxidation end has a gentle shape, and it is possible to provide a method for manufacturing a semiconductor device with a low Q and a low Q.
第１図ａ〜ｉは本発明を説明するための一実施例を示す
製造工程の断面概略図である。
図Ｑこおいて、
１・・・・・・半導体基板、２・・・・・・酸化膜、３
・・・・・・高濃度不純物を含む多結晶シリコン、４・
・・・・・耐酸化マスク、５・・・・・・チャンネルス
トツパ、６・・・・・・厚い酸化膜、７・・・・・・半
導体基板面上の薄い酸化膜、８・・・・・・表子分離用
の厚い酸化膜、９・・・・・・ゲート酸化膜、１０・・
・・・・ゲート電極、１１・・・・・・ソース、１２・
・・・・・ドレイン、１３・・・・・・絶縁用ＣＶＤシ
リコン酸化膜、１４．１５・・・・・・配線。FIGS. 1A to 1I are schematic cross-sectional views of manufacturing steps showing an embodiment for explaining the present invention. In Figure Q, 1... Semiconductor substrate, 2... Oxide film, 3
...Polycrystalline silicon containing high concentration impurities, 4.
... Oxidation-resistant mask, 5 ... Channel stopper, 6 ... Thick oxide film, 7 ... Thin oxide film on semiconductor substrate surface, 8 ... ... Thick oxide film for front and child isolation, 9... Gate oxide film, 10...
...gate electrode, 11...source, 12.
...Drain, 13...CVD silicon oxide film for insulation, 14.15...Wiring.
Claims (1)
料層を形威する工程と、この酸化速度の速い材料層上Ｑ
こ部分的に耐酸化マスクを形戊する工程と、この耐酸化
マスクをマスクとして素子形或予定領域上の前記酸化速
度の速い材料層を酸化し酸化膜を形或する工程と、前記
耐酸化マスクを除去する工程と、前記酸化膜を不純物ド
一つピングマスクとして前記半導体基板へ不純物をドー
プする工程と、前記酸化膜を厚さ力向ｌこ少なくとも一
部除去する工程と、残った酸化速度の速い材料層を酸化
する工程と、前記素子形或予定領域上の酸化膜を少なく
とも一部除去し前記半導体基板面を露出させる工程を有
することを特徴とする半導体装置の製造力法。 ２ 前記半導体基板と前記酸化速度の速い材料との間（
こ酸化膜を介在させることを特徴とする前記特許請求の
範囲第１項記載の半導体装置の製造力法。 ３ 前記酸化速度の速い材料として高不純物濃度の多結
晶シリコン及ひモリブデンシリサイド及ひタングステン
シリサイドの内少なくとも一つの材料を用いることを特
徴とする、前記特許請求の範囲第１項乃至第２項いずれ
か記載の半導体装置の製造力法。 ４ 前記耐酸化マスク材料Ｑこ窒化シリコンを用いるこ
とを特徴とする前記特許請求の範囲第１項乃至第３項い
ずれか記載の半導体装置の製造力法。 ５ 前記酸化膜が素子間分離膜であることを特徴とする
前記特許請求の範囲第１項乃至第４項いずれか記載の半
導体装置のＶ造力法。 ６ 前記酸化模を厚さ力向Ｏこ少なくとも一部除去する
工程において前記酸化膜を厚さ力向（こ少なくとも全膜
厚の３／４を除去することを特徴とする前記特許請求の
範囲第１項乃至第５項いずれか記載の半導体装置の製造
力法。[Claims] 1. A step of forming a layer of material having a faster oxidation rate than that of the semiconductor substrate on a semiconductor substrate, and a step of forming a layer of material having a faster oxidation rate than that of the semiconductor substrate;
a step of partially forming an oxidation-resistant mask; a step of using the oxidation-resistant mask as a mask to oxidize the material layer with a high oxidation rate on a planned area of the element shape to form an oxide film; a step of doping an impurity into the semiconductor substrate using the oxide film as an impurity doping mask; a step of removing at least a portion of the oxide film in the thickness direction; and a step of removing the remaining oxide film. A method for manufacturing a semiconductor device, comprising the steps of: oxidizing a material layer at a high rate; and removing at least a portion of an oxide film on a predetermined region of the element shape to expose the surface of the semiconductor substrate. 2 between the semiconductor substrate and the material with a high oxidation rate (
2. A method for manufacturing a semiconductor device according to claim 1, characterized in that an oxidized film is interposed therebetween. 3. Any one of claims 1 to 2, characterized in that the material with a high oxidation rate is at least one of polycrystalline silicon with a high impurity concentration, molybdenum silicide, and tungsten silicide. The method for manufacturing semiconductor devices described in . 4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that the oxidation-resistant mask material Q is silicon nitride. 5. The V force forming method for a semiconductor device according to any one of claims 1 to 4, wherein the oxide film is an element isolation film. 6. The method according to claim 1, wherein in the step of removing at least a portion of the oxide film in the thickness direction, the oxide film is removed in the thickness direction (at least 3/4 of the total film thickness). A method for manufacturing a semiconductor device according to any one of items 1 to 5.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14836380A JPS5837990B2 (en) | 1980-10-24 | 1980-10-24 | Manufacturing method of semiconductor device |
| US06/313,324 US4419142A (en) | 1980-10-24 | 1981-10-20 | Method of forming dielectric isolation of device regions |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14836380A JPS5837990B2 (en) | 1980-10-24 | 1980-10-24 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5772344A JPS5772344A (en) | 1982-05-06 |
| JPS5837990B2 true JPS5837990B2 (en) | 1983-08-19 |
Family
ID=15451082
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14836380A Expired JPS5837990B2 (en) | 1980-10-24 | 1980-10-24 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5837990B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6267983U (en) * | 1985-10-19 | 1987-04-28 | ||
| JPS6246880Y2 (en) * | 1983-08-26 | 1987-12-21 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3371837D1 (en) * | 1982-12-08 | 1987-07-02 | Ibm | Method for making semiconductor devices having a thick field dielectric and a self-aligned channel stopper |
| JP2623907B2 (en) * | 1990-04-25 | 1997-06-25 | 日本電気株式会社 | Method for manufacturing semiconductor device |
-
1980
- 1980-10-24 JP JP14836380A patent/JPS5837990B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6246880Y2 (en) * | 1983-08-26 | 1987-12-21 | ||
| JPS6267983U (en) * | 1985-10-19 | 1987-04-28 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5772344A (en) | 1982-05-06 |
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