JP2892436B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method of manufacturing a semiconductor device having both a P-type impurity layer and an N-type impurity layer as buried layers.

(Prior Art) In recent years, the use of the BiCMOS mixed technology for the purpose of increasing the speed of the analog / digital hybrid or CMOS has increased in many cases, and has become the mainstream in the composite technology field.

Bi CMOS LSIs have the characteristics of both bipolar and CMOS, so high speed, high integration, high withstand voltage, high load drive capability,
Although excellent performance such as low power consumption can be realized, an epitaxial layer and an isolation diffusion are necessary in order to structurally govern a bipolar element.

Further, since the bipolar and CMOS elements are simultaneously formed without deteriorating the performance, the process is complicated and the number of masks is increased, which is disadvantageous in terms of economy.

Here, a conventional method of manufacturing a BiCMOS type semiconductor integrated circuit will be described with reference to FIG. In FIG. 2, an N ⁺ buried layer 2 is formed in a P-type semiconductor substrate 1, and the N ⁺
The buried layer 2 is usually made of As or Sb to reduce the collector series resistance of the NPN bipolar transistor 100 to 20 to 100.
It is diffused to Ω / □. The method of manufacturing the portion of the NPN bipolar transistor 100 is described in JP-A-63-102259.

The N ⁺ buried layer 2 is also diffused into the PMOS 300 forming region at the same time so that the CMOS does not cause a parasitic bipolar operation.

4 is a P ⁺ buried layer, which is an NPN bipolar transistor 100
Are formed in advance in the element isolation region by an ion implantation method or the like, and are used in order to shorten the separation / diffusion time by utilizing upward diffusion from the semiconductor substrate 1 during the next epitaxial step or separation / diffusion. Usually, it is set to 50 to 300Ω / □ using B (boron).

The NMOS 200 is also formed in the NMOS 200 formation region at the same time so that the parasitic bipolar operation does not occur.

The concentration and thickness of the N ⁻ epitaxial layer 5 are determined so that the device characteristics of the NPN bipolar transistor 100 and the gate threshold voltage of the PMOS can be controlled.

P ⁻ diffusion region 6 is diffused from the surface of N ⁻ epitaxial layer 5 in order to control the element isolation of NPN bipolar transistor 100 and the threshold voltage of NMOS 200.

7 is a P diffusion layer, the active base of the NPN bipolar transistor 100, 8 is a P ⁺ diffusion layer,
The drain and the inactive base layer of the NPN bipolar transistor 100 are formed. The inactive base layer is necessary to make ohmic contact with the base layer.

Reference numeral 9 denotes an N ⁺ diffusion layer, which is a source, a drain and an N
The contact extraction of the emitter and collector layers of the PN bipolar transistor 100 is formed.

The P diffusion layer 7, the P ⁺ diffusion layer 8, and the N ⁺ diffusion layer 9 are respectively
It is selectively diffused using oxide film 11 as a mask to form P, P ⁺ , and N ⁺ regions. Reference numeral 10 denotes a gate of a PMOS or NMOS.

In this way, a BiCMOS type semiconductor integrated circuit is formed. However, the steps after the formation of the N ⁻ epitaxial layer 5 are the same as the ordinary CMOS manufacturing steps except for the step of forming the active base layer. Are formed at the same time.

Therefore, in order to pursue the economics of the manufacturing process of the BiCMOS type integrated circuit, simplification of the process before forming the epitaxial layer is inevitable.

As a further improved process, as described in Nikkei Micro Devices, November 1986, page 75, the portion where the P ⁺ buried layer 4 is to be formed is first covered with a Si ₃ N ₄ film,
Then, using this Si ₃ N ₄ film as a mask, Sb for an N ⁺ buried layer is implanted by ion implantation.

Next, while performing drive-in in an oxidizing atmosphere and forming a thick oxide film in the region where Sb was implanted,
After peeling off the ₃ N ₄ film, implanted B ⁺ for P ⁺ buried layer, there is a method for drive-in.

(Problems to be Solved by the Invention) However, the method described on page 75 of the Nikkei Microdevices November 1986 / November, in which the N ⁺ layer and the P ⁺ layer are formed by one mask, Therefore, the N ⁺ buried layer and the P ⁺ buried layer collide with each other in a high concentration region, and the general concentration (N ⁺ … 10 ²⁰
ions / cm ³ , P ⁺ … 10 ¹⁸ ions / cm ³ ), the withstand voltage is at most about 10 V, and an element with a higher withstand voltage cannot be formed.

When the P ⁺ buried layer and the N ⁺ buried layer are formed using one mask each, the P layer and the N layer can be separated from each other. Since two masks are required and misalignment between the two masks must be taken into account, there is a problem that the reduction in size is hindered.

This invention is one of the problems of the prior art.
The point that the breakdown voltage due to the collision between the P-type buried layer and the N-type buried layer is reduced, and that the mask is formed when the P ⁺ buried layer and the N ⁺ buried layer are formed using one mask each. It is an object of the present invention to provide a method of manufacturing a semiconductor device, which solves the problem that two wafers are required and that a reduction in mask due to misalignment is prevented.

(Means for Solving the Problems) According to the present invention, in a method for manufacturing a semiconductor device, an SiO ₂ film and a Si ₃ N ₄ film are formed on a semiconductor substrate, and the first impurity is formed using the Si ₃ N ₄ film as a mask. The step of removing the SiO ₂ film using the Si ₃ N ₄ film as a mask, the opening on the Si substrate and the Si ₃ N
After growing the silicon single crystal or polycrystalline silicon laterally ₄ film, to remove the Si ₃ N ₄ film, it is obtained by introducing a step of introducing a second impurity into the entire surface.

(Operation) According to the present invention, in a method of manufacturing a semiconductor device,
Since the steps described above have been introduced, an opening is formed in the Si ₃ N ₄ film, impurity ions of the same conductivity type as the semiconductor substrate are implanted, a first diffusion layer is formed, and the SiO ₂ film in the opening is formed. After removal, single crystal silicon or polycrystalline silicon
The Si ₃ N ₄ film on the grown laterally, Si ₃ N ₄ and the semiconductor substrate film is removed monocrystalline silicon or polycrystalline silicon as a mask by implanting the opposite conductivity type ions, the second diffusion The layer can be formed at a predetermined distance from the first diffusion layer, so that the above problem can be eliminated.

(Example) Hereinafter, an example of a method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. 1 (a) to 1 (f) are process sectional views of one embodiment of the present invention.

First, as shown in FIG. 1 (a), a P-type silicon substrate
Using a known thermal oxidation technique, 200-300
₂ Film 102 is formed, and 1000
The Si ₃ N ₄ film 103 is formed to a degree.

Next, as shown in FIG.
An opening 103A is formed by opening a window in the Si ₃ N ₄ film 103 by using a known photolithographic etching technique such as using plasma of CF ₄ + O ₂ .

Further, a P-type impurity is introduced into the opening 103A by using a known ion implantation method using the opened Si ₃ N ₄ film 103 as a mask.

However, at this time, the energy of the ion is SiO ₂ of 200 to 300 °.
Since it is necessary to pass through the film 102, the dose is set to about 5 × 10 ¹² ions / cm ² at a dose of 40 to 50 KeV. Thus, a P-type impurity diffusion layer 104 is obtained.

Next, as shown in FIG. 1C, an opening 10 is formed by using a known wet etching technique using an HF buffer solution or the like.
The 3A SiO ₂ film 102 is removed.

Next, as shown in FIG. 1D, silicon is formed on the P-type impurity diffusion layer 104 by using a well-known CVD technique.
Selectively grow only on A. This silicon may be single crystal silicon or polycrystalline silicon.

For example, for single-crystal silicon, “Growth Proce
ss of Silicon Over SiO ₂ by CVD: Epitaxial Lateral O
vergrowth Technique: J. Electrochem. Soc .: Solid-Stat
e Science and Technology: July 1983 ", P1576, 1050 ° C., SiH ₂ Cl ₂ = 0.75 / min, HCl = 2 / mi
By growing at n, H ₂ = 180 / min, selective and further lateral growth of the openings is obtained. Here, for example, if silicon of 3 μm is grown, growth of about 3 to 5 μm is obtained in the lateral direction. This lateral growth dimension is for forming an N-type diffusion layer described later with a distance from the P-type impurity diffusion layer 104.

Next, as shown in FIG. 1 (e), by using a known etching technique using such as an aqueous solution of hot phosphoric acid type, Si ₃ N ₄
The entire surface of the film 103 is removed, and using a known iontophoresis technique, 4
N-type irregularity is introduced with an energy of about 0 KeV dose of about 2 × 10 ¹⁵ ions / cm ² to form the above-described N-type diffusion layer.

At this time, since the N-type impurity is not introduced into the laterally grown portion of the silicon 105, the P-type impurity diffusion layer 104 is
A distance of 3 to 5 μm is formed between the mold diffusion layers 106.

After that, the silicon 105 is removed by etching. For example, the following method can be considered. A resist with an etching rate very similar to silicon is coated on the entire surface, and a well-known RI
Etch silicon and resist using E technology,
After etching an appropriate amount (remaining silicon
Å) resist is removed, subjected to thermal oxidation, after all the silicon to the SiO ₂ film is entirely removed SiO ₂ film by using a buffered HF solution.

Thereafter, a heat treatment at 1100 ° C. to 1200 ° C. is performed, and as shown in FIG. 1 (f), the P-type impurity diffusion layer 104 and the N-type diffusion layer 106 are set to have a desired diffusion layer depth and a predetermined specific resistance is set. obtain.

(Effects of the Invention) As described in detail above, according to the present invention, a window is formed in a Si ₃ N ₄ film formed on a semiconductor substrate via an SiO ₂ film, and the Si ₃ N ₄ film is masked. After forming an impurity diffusion layer of the same copper type as that on the semiconductor substrate, the SiO ₂ film is removed and grown on the single crystal silicon or polycrystalline silicon opening, and the Si ₃ N ₄ film is removed to remove the semiconductor substrate. Since a diffusion layer of the opposite conductivity type is formed, a P-type impurity buried layer and an N-type impurity buried layer are formed in a self-aligned manner using only one mask. Therefore, the number of mask alignment steps is reduced, and the steps are simplified.

In addition, since a spacer is formed between the N-type impurity diffusion layer and the P-type impurity diffusion layer by laterally growing silicon single crystal or polycrystalline silicon, a distance is formed between the two diffusion layers by the amount of the spacer. . It is a well-known fact that the larger the distance, the higher the breakdown voltage is obtained. If the distance between the diffusion layers is about 3 μm with respect to about 10 V shown in the conventional example, a breakdown voltage of about 40 to 50 V can be expected.

[Brief description of the drawings]

1 (a) to 1 (f) are process cross-sectional views of an embodiment of a method of manufacturing a semiconductor device according to the present invention, and FIG. 2 is a process cross-sectional view of a conventional method of manufacturing a semiconductor device. 101: P-type silicon substrate, 102: SiO ₂ film, 103: Si ₃
N ₄ film, 103A ...... opening, 104 ...... P-type impurity diffusion layer, 105
... silicon, 106 ... N-type diffusion layer.

Claims (1)

(57) [Claims] (A) On a semiconductor substrate having a first conductivity type
Forming a SiO ₂ film and a Si ₃ N ₄ film sequentially, and forming an opening at a predetermined position of the Si ₃ N ₄ film; and (b) using the Si ₃ N ₄ film as a mask to form a first conductivity type. Forming a first conductivity type diffusion layer on the semiconductor substrate by ion-implanting impurities having the same; and (c) selectively removing the SiO ₂ film on the first conductivity type diffusion layer after the removal. and removing the the Si ₃ N ₄ film is grown laterally on the silicon is grown and the the Si ₃ N ₄ film, and ion implanting impurities having a second conductivity type as a mask (d) is the silicon Forming a diffusion layer of the second conductivity type by using the above method.