JPH04361533A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To restrain the recombination current during the actuation time of a transistor by a method wherein a base layer is formed on an exposed silicon surface and then the first layer amorphous silicon film is transformed into the first layer polycrystal silicon film. CONSTITUTION:An N<+> type collector wall layer 7 is formed and then a CVD film 20 on the region to be a P<+> type true layer and a P<+> type outer base layer respectively and selectively formed in the later steps is partially and selectively etched away to form the first layer amorphous silicon film 24 for leading-out base electrode on the whole surface. Next, after specifically patterning said film 24, the second interlayer insulating film 10 is formed on said film 24 at the temperature whereat the first amorphous silicon film 24 is not transformed into polycrystal silicon. Through these procedures, the ruggedness on the surface of the amorphous silicon film 24 can be made less conspicuous than that on the polycrystal silicon film.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly, to a method for manufacturing a bipolar semiconductor integrated circuit device having a two-layer polycrystalline silicon structure that enables high integration and high-speed operation. This relates to improvement of the method.

0002

Conventionally, for example, in a bipolar semiconductor integrated circuit device having a two-layer polycrystalline silicon structure, a polycrystalline silicon layer for leading out a base electrode and a polycrystalline silicon layer for leading out an emitter electrode have been formed separately. By depositing it, the junction capacitance between the base and collector of a bipolar transistor, which has a large effect on the operating speed, is reduced.

The main steps of a conventional method for manufacturing a bipolar semiconductor integrated circuit device having a two-layer polycrystalline silicon structure are sequentially schematically shown in FIGS. 10 to 20.

First, the structure of this bipolar semiconductor integrated circuit device having a two-layer polycrystalline silicon structure will be described.

That is, in the device configurations shown in FIGS. 10 to 20, reference numeral 1 is a P- type semiconductor substrate, and 2 and 3 are N+ type buried semiconductor substrates sequentially laminated on the semiconductor substrate 1. and an N-type epitaxial layer. 4 is P formed in the semiconductor substrate 1.
+ type channel cut layer, 5 is the epitaxial layer 3
, the buried layer 2, and the isolation insulating layer for element isolation formed to reach the channel cut layer 4 through the surface layer of the semiconductor substrate 1. Reference numeral 6 denotes a first interlayer insulating film selectively formed on the epitaxial layer 3.

Further, 7 is an N+ type collector wall layer selectively formed in the epitaxial layer 3,
Similarly, 8a is a P+ type intrinsic base layer selectively formed in the epitaxial layer 3, and 8b is the intrinsic base layer 8a.
9 is a P+ type external base layer selectively formed on both sides, and 9 is an N+ type emitter layer selectively formed on the intrinsic base layer 8a. 10 is a second interlayer insulating film.

Further, 11b is a P-type first layer polycrystalline silicon film, 12b is an N-type second layer polycrystalline silicon film, 13 is a silicide film, and 14 is a third interlayer insulating film. 15 is an aluminum wiring, 16 is a barrier metal layer, and 17, 18, and 19 are each of these aluminum wirings 15.
and a barrier metal layer 16. 20 is the first CVD
The oxide films 21a to 21e are patterned resist films, and the oxide films 22a and 22b are the first and second patterned resist films, respectively.
The second thermal oxide films 23a and 23b are respectively
These are the third CVD oxide films.

Next, a manufacturing flow of a conventional bipolar semiconductor integrated circuit device having a two-layer polycrystalline silicon structure having the above configuration will be described.

First, on a P-type semiconductor substrate 1,
An N+ type buried layer 2 is formed and an N− type epitaxial layer 3 is grown thereon, and then trench grooves are selectively formed through the epitaxial layer 3, the buried layer 2, and the surface layer of the semiconductor substrate 1. After digging, a P+ type channel cut layer 4 is formed in the semiconductor substrate 1 at the bottom of the trench, and the inside of the trench is filled with an isolation insulating layer 5 for isolation between elements. continue,
After forming a first interlayer insulating film 6 on the entire surface of the epitaxial layer 3, using a resist film 21a formed by photolithography and patterned as desired as a mask, the first interlayer insulating film 6 is formed on the entire surface of the epitaxial layer 3. By selectively etching and removing the insulating film 6, an N+ type collector wall layer 7, a P+ type intrinsic base layer 8a, and a P+ type external base layer 8b are formed selectively in a later step. N+
Each corresponding portion corresponding to the emitter layer 9 of the mold is opened (see FIG. 10).

[0010] Also, the resist film 21 used for the mask
After removing a, a first CVD oxide film 20 is formed on the entire surface of the epitaxial layer 3 including the first interlayer insulating film 6, and again using a resist film 21b patterned by photolithography as a mask. Then, an N-type impurity, in this case phosphorus, is ion-implanted at a high concentration (see FIG. 11).

Next, after removing the resist film 21b again, heat treatment is performed to form the N+ type collector wall layer 7.
and P that is selectively formed in the subsequent process.
After partially and selectively etching the first CVD oxide film 20 on the corresponding regions which will become the + type intrinsic base layer 8a and the P+ type external base layer 8b, CVD is performed.
By using a method, a first layer polycrystalline silicon film 11b, which will be made P-type in a later process, is applied to the entire surface in a thickness of, for example, about 20%
The second interlayer insulating film 10 is formed on the entire surface by the CVD method (see FIG. 12).

Furthermore, in order to form each of the base and emitter regions, the second interlayer insulating film 10 and the first layer are again formed using the resist film 21c patterned by photolithography as a mask. Each corresponding portion of the polycrystalline silicon film 11b is removed by selective anisotropic etching until the surface of the epitaxial layer 3 is exposed (see FIG. 13).

After forming the first thermal oxide film 22a on the exposed surface of the epitaxial layer 3, a P-type impurity, in this case boron, is added to a high concentration in order to form a P+ type intrinsic base layer 8a. Ion implantation to high concentration (see Figure 14)
.

Subsequently, after heat treatment is performed to form a P+ type intrinsic base layer 8a, the second interlayer insulating film 10 and First CVD oxide film 2
0 to the N+ type collector wall layer 7.
Selective anisotropic etching is performed until the surface is exposed (see FIG. 15).

Furthermore, after the resist film 21d is removed again, a second CVD oxide film 23a is formed (FIG. 16).
reference).

Thereafter, the second CVD oxide film 23a is anisotropically etched until the N+ type collector wall layer 7 and the P+ type intrinsic base layer 8a are exposed, thereby forming a collector contact opening. On the side wall of the emitter opening, a frame-shaped oxide film, the so-called side wall oxide film 23b, is formed on the side wall of the emitter opening.
After forming sidewall oxide films 22b and 23b in the same manner, a second layer polycrystalline silicon film 12b, which is made to be N-type, is formed on the entire surface by CVD.
A film is formed to a thickness of, for example, about 3000 angstroms, and an N-type impurity, in this case arsenic, is ion-implanted at a high concentration into the entire surface (see FIG. 17).

[0017] Again, using the resist film 21e patterned by photolithography as a mask, the corresponding portion of the second layer polycrystalline silicon film 12b is patterned and formed by anisotropic etching, and with the same mask,
After performing anisotropic etching until the first layer polycrystalline silicon film 11b is exposed, a P-type impurity, in this case boron, is ion-implanted into the entire surface at a high concentration (see FIG. 1).
8).

Furthermore, the resist film 2 used for the mask
After removing layer 1e, heat treatment is performed to form an external base layer 8b and an emitter layer 9, respectively, and the first layer,
For example, a silicide film 1 such as TiSi2 is formed on the exposed portion of each polycrystalline silicon film 11b, 12b of the second layer.
3 (see FIG. 19).

Thereafter, a third interlayer insulating film 14 is formed on the entire surface of these layers by CVD, and contact holes are selectively opened in each corresponding portion by dry etching using a resist pattern mask (not shown). let me,
and each barrier metal layer 16 in each corresponding part,
By forming the aluminum wiring 15, a base electrode 17, an emitter electrode 18, and a collector electrode 19 are formed respectively (see FIG. 20).

[0020]

[Problems to be Solved by the Invention] However, in the configuration of a conventional bipolar semiconductor integrated circuit device having a two-layer polycrystalline silicon structure manufactured through the above-mentioned steps,
Polycrystalline silicon films are used to draw out the base electrode and emitter electrode, and in this conventional case, the first layer of polycrystalline silicon film for drawing out the base electrode is formed by CVD. After that, the corresponding portion of the polycrystalline silicon film is opened by etching to expose the silicon surface corresponding to the portion where the emitter layer will be formed.
An emitter layer is formed on this exposed silicon surface, and a second layer of polycrystalline silicon film for drawing out the emitter electrode is formed on the silicon surface portion of the emitter layer by CVD.

Therefore, when etching the polycrystalline silicon film here, the surface of the polycrystalline silicon film formed by the CVD method is generally uneven, and moreover, etching is performed along the grain interfaces in the polycrystalline silicon film. As the rate increases, the exposed silicon surface in the area where the emitter layer is formed tends to have an uneven shape, which causes recombination current to occur on the uneven silicon surface during transistor operation. There was a problem with that.

On the other hand, the polycrystalline silicon film here is produced by forming crystal grains through the growth of clusters.
In this case, it is known that the polycrystalline silicon film has many clusters, so its crystal grains are small and there are many grain interfaces, and the grain interfaces lack conductivity compared to the crystal grains themselves. As a result, polycrystalline silicon has poor conductivity when compared to single silicon, and when polycrystalline silicon is used to lead out the emitter electrode, there is a problem in that the emitter resistance becomes high.

The present invention was made to solve these conventional problems, and its purpose is to prevent as much as possible the occurrence of unevenness on the silicon surface of the emitter layer. This is a method for manufacturing a semiconductor integrated circuit device of this type, which suppresses recombination current during transistor operation and reduces emitter resistance at the lead-out portion of the emitter electrode. An object of the present invention is to provide a method for manufacturing a bipolar semiconductor integrated circuit device having a polycrystalline silicon structure.

[0024]

[Means for Solving the Problems] In order to achieve the above object, a method for manufacturing a semiconductor integrated circuit device according to the first aspect of the present invention includes a bipolar transistor having a two-layer polycrystalline silicon structure on a semiconductor substrate. In the semiconductor integrated circuit device comprising: a first layer of the two-layer polycrystalline silicon structure;
A step of forming a first layer amorphous silicon film for base electrode extraction corresponding to the layer by CVD method, and a step of forming a first layer amorphous silicon film on the first layer amorphous silicon film so that the first layer amorphous silicon film is not transformed into a polycrystalline silicon film. a step of forming an interlayer insulating film by a CVD method at a high temperature;
selectively opening the silicon surface until it is exposed; forming a base layer and an emitter layer in sequence on the exposed silicon surface; and converting the first layer amorphous silicon film into a first layer polycrystalline silicon The method is characterized in that it includes at least a step of transforming into a film.

Further, a method for manufacturing a semiconductor integrated circuit device according to a second aspect of the present invention is a semiconductor integrated circuit device comprising a bipolar transistor having a two-layer polycrystalline silicon structure on a semiconductor substrate. A second layer amorphous silicon film for drawing out the emitter electrode corresponding to the second layer of the two-layer polycrystalline silicon structure is placed on the exposed silicon surface which becomes the electrode drawing surface of the layer.
a step of forming an amorphous silicon film by a CVD method at a temperature at which the second layer amorphous silicon film is not transformed into a second layer polycrystalline silicon film; a step of implanting impurities of a desired conductivity type into the second layer amorphous silicon film; Forming an emitter layer in the silicon plane through a second layer amorphous silicon film into which impurities have been implanted, and transforming the second layer amorphous silicon film into a second layer polycrystalline silicon film. It is characterized by:

[0026]

[Operation] Therefore, in the method of manufacturing a semiconductor integrated circuit device to which the first aspect of the present invention is applied, the first layer amorphous silicon film for drawing out the base electrode is formed by the CVD method, and the first layer amorphous silicon film is An interlayer insulating film is formed on the film by CVD at a temperature at which it will not be transformed into a polycrystalline silicon film, and the corresponding portion of the interlayer insulating film and the emitter layer of the first amorphous silicon film that will become the electrode extraction surface is After selectively opening the silicon surface until it is exposed, a base layer is formed on the exposed silicon surface, and the first layer amorphous silicon film is transformed into the first layer polycrystalline silicon film. Therefore, it is possible to prevent the occurrence of irregularities on the silicon surface on which the emitter layer is formed, and to effectively suppress recombination current during operation of the transistor.

Further, in the method for manufacturing a semiconductor integrated circuit device to which the second aspect of the present invention is applied, a second layer for drawing out the emitter electrode is formed on the exposed silicon surface which becomes the electrode drawing surface of the emitter layer. CVD is carried out at a temperature that does not transform an amorphous silicon film into a polycrystalline silicon film.
method, implanting impurities of a required conductivity type into the second layer amorphous silicon film, forming an emitter layer within the silicon plane through the second layer amorphous silicon film, and Since the film is transformed into a second layer polycrystalline silicon film, a second layer for drawing out the emitter electrode is used here.
The conductivity of the layered polycrystalline silicon film is improved and the emitter resistance can be effectively reduced.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a method for manufacturing a semiconductor integrated circuit device according to the present invention will be described in detail with reference to FIGS. 1 to 9.

FIGS. 1 to 9 show a method for manufacturing a semiconductor integrated circuit device to which an embodiment of the present invention is applied. Here, the main method for manufacturing a bipolar semiconductor integrated circuit device using a two-layer polycrystalline silicon film is shown. 1 to 9, the same reference numerals as those in the conventional apparatus shown in FIGS. 10 to 21 are the same or the same. It represents a considerable portion.

In this embodiment as well, first, the structure of a bipolar semiconductor integrated circuit device having a two-layer polycrystalline silicon structure according to this embodiment will be described.

That is, in the device configurations shown in FIGS. 1 to 9, reference numeral 1 is a P- type semiconductor substrate, and 2 and 3 are N+ type semiconductor substrates laminated in sequence on the semiconductor substrate 1. A buried layer and an N-type epitaxial layer. 4 is a P+ formed in the semiconductor substrate 1;
type channel cut layer, 5 is the epitaxial layer 3,
This is an isolation insulating layer formed to reach the channel cut layer 4 through the buried layer 2 and the surface layer of the semiconductor substrate 1 for isolation between elements. Reference numeral 6 denotes a first interlayer insulating film selectively formed on the epitaxial layer 3.

Further, 7 is an N+ type collector wall layer selectively formed in the epitaxial layer 3,
Similarly, 8a is a P+ type intrinsic base layer selectively formed in the epitaxial layer 3, and 8b is the intrinsic base layer 8a.
9 is a P+ type external base layer selectively formed on both sides, and 9 is an N+ type emitter layer selectively formed on the intrinsic base layer 8a. 10 is a second interlayer insulating film.

Further, 11a is a P-type first layer polycrystalline silicon film transformed from an amorphous material for extracting the base electrode, and 12a is an N-type second layer polycrystalline silicon film transformed from an amorphous material for emitter electrode extraction. 13 is a silicide film, and 14 is a third interlayer insulating film. 15 is an aluminum wiring, 16 is a barrier metal layer, and 17, 18, and 19 are each of these aluminum wirings 15.
, a base electrode, an emitter electrode, and a collector electrode consisting of a barrier metal layer 16. 20 is a first CVD oxide film, 21b, 21c, and 21e are patterned resist films, 22a and 22b are first and second thermal oxide films, respectively, and 23a and 23b are second resist films, respectively. , third CVD oxide films. And again, 2
4 and 25 are first and second layer amorphous silicon films, respectively.

Next, a manufacturing flow of a bipolar type semiconductor integrated circuit device having a two-layer polycrystalline silicon structure in an embodiment having the above structure will be described.

First, on the P-type semiconductor substrate 1,
An N+ type buried layer 2 is formed and an N− type epitaxial layer 3 is grown thereon, and then trench grooves are selectively formed through the epitaxial layer 3, the buried layer 2, and the surface layer of the semiconductor substrate 1. After digging, a P+ type channel cut layer 4 is formed in the semiconductor substrate 1 at the bottom of the trench, and the inside of the trench is filled with an isolation insulating layer 5 for isolation between elements. Subsequently, a first interlayer insulating film 6 is formed on the entire surface of the epitaxial layer 3, and a resist film formed by photolithography and patterned as desired is used as a mask to form the first interlayer insulating film 6. By selectively etching and removing the interlayer insulating film 6, an N+ type collector wall layer 7 and a P+ type intrinsic base layer 8a, which are selectively formed in a later step, are formed.
Then, corresponding portions corresponding to the P+ type external base layer 8b and the N+ type emitter layer 9 are opened. After removing the resist film used as the mask, a first CVD oxide film 20 is formed on the entire surface of the epitaxial layer 3 including the first interlayer insulating film 6, and patterning is again performed by photolithography. resist film 21
Using b as a mask, apply N-type impurities to the entire surface.
Here, phosphorus is ion-implanted at a high concentration (see Figure 1).
. In other words, up to this stage, the process is exactly the same as in the conventional example described above.

Next, after removing the resist film 21b again, heat treatment is performed to form the N+ type collector wall layer 7.
and P that is selectively formed in the subsequent process.
After partially and selectively etching the CVD oxide film 20 on the corresponding regions that will become the + type intrinsic base layer 8a and the P+ type external base layer 8b, a base layer is formed over the entire surface by CVD method. A first layer amorphous silicon film 24 for leading out the electrodes is formed to a thickness of, for example, about 2000 angstroms, patterned as desired, and further, this first layer amorphous silicon film 24 is formed by a CVD method. The second amorphous silicon film 24 is heated at a temperature such that the first layer amorphous silicon film 24 does not transform into polycrystalline silicon, for example, at a temperature of about 550°C or less.
An interlayer insulating film 10 is formed (see FIG. 2).

In order to form each of the base and emitter regions, the interlayer insulating film 10 and the first layer amorphous silicon film are again formed using the resist film 21c patterned by photolithography as a mask. 24, that is, each corresponding portion that will eventually become the electrode extraction opening surface of the collector wall layer and the emitter layer, is selectively anisotropically treated until the three surfaces of the epitaxial layer are exposed. Etch and remove (
(see Figure 3). That is, during this selective etching removal, the silicon surface (epitaxial layer 3
In the case of amorphous silicon, since there are no grains, the etching rate does not increase along the grain interface as in the case of polycrystalline silicon, and the etching rate does not increase along the grain interface as in the case of the conventional example described above. When compared to the corresponding silicon surface exposed by etching silicon, the unevenness can be reduced as much as possible and effectively, and as a result, the silicon surface with improved unevenness can be used for transistors. This makes it possible to effectively suppress recombination current during operation.

After forming the first thermal oxide film 22a on the exposed surface of the epitaxial layer 3, a P type impurity, in this case boron, is added to a high concentration in order to form a P+ type intrinsic base layer 8a. Ions are implanted to a certain concentration (see Figure 4). By this heat treatment, the first layer amorphous silicon film 24 is transformed into a P-type first layer polycrystalline silicon film 11a.

Subsequently, after heat treatment is performed to form a P+ type intrinsic base layer 8a, the second
selectively anisotropically etching and removing respective portions of the interlayer insulating film 10 and the first CVD oxide film 20 until the surface of the N+ type collector wall layer 7 is exposed;
And after removing the resist film used as a mask, the second C
A VD oxide film 23a is formed (see FIG. 5).

Thereafter, the second CVD oxide film 23a is anisotropically etched until the N+ type collector wall layer 7 and the P+ type intrinsic base layer 8a are exposed, thereby forming a collector contact opening. A frame-shaped oxide film, so-called sidewall oxide film 23b is formed on the sidewall of the emitter opening, and sidewall oxide films 22b and 23b are similarly formed on the sidewall of the emitter opening, and then by CVD method, A second layer amorphous silicon film 25 for drawing out the emitter electrode is coated on the entire surface, for example, with a thickness of about 5
It is formed to a thickness of about 3000 angstroms at a temperature below about 50° C., and N-type impurities, in this case arsenic, are ion-implanted at a high concentration into the entire surface (see FIG. 6).

[0041] Again, using the resist film 21e patterned by photolithography as a mask, the corresponding portion of the second layer amorphous silicon film 25 is patterned and formed by anisotropic etching. After performing anisotropic etching until the first layer polycrystalline silicon film 11a transformed from the first layer amorphous silicon film 24 is exposed, the entire surface is ionized with a P-type impurity, in this case boron, at a high concentration. (See Figure 7).

Furthermore, the resist film 2 used for the mask
After removing the layer 1e, heat treatment is performed at a temperature of about 900° C. to form an external base layer 8b and an emitter layer 9, respectively, and convert the second layer amorphous silicon film 25 into an N-type second layer multilayer. a P-type first layer polycrystalline silicon film 11a, which is transformed into a crystalline silicon film 12a, and both of which are transformed from amorphous;
A silicide film 13 of, for example, TiSi2 is selectively formed on the exposed portion of the N-type second layer polycrystalline silicon film 12a (see FIG. 8). Therefore, like this, the second
By transforming the layered amorphous silicon film into an N-type second layer polycrystalline silicon film, the number of clusters can be suppressed, resulting in larger crystal grains and fewer grain interfaces, resulting in improved conductivity. Therefore, emitter resistance can be reduced.

Thereafter, a third interlayer insulating film 14 is formed on these entire surfaces by CVD, and contact holes are selectively opened in the corresponding portions by dry etching using a resist pattern mask (not shown). After that, each barrier metal layer 16 in each corresponding part is
By forming the aluminum wiring 15, a base electrode 17, an emitter electrode 18, and a collector electrode 19 are formed respectively (see FIG. 21). In other words, as described above, a two-layer polycrystalline silicon structure is constructed in which the occurrence of unevenness on the silicon surface of the emitter layer is prevented as expected, suppressing recombination current and reducing emitter resistance. A bipolar semiconductor integrated circuit device can be manufactured.

[0044] In the above embodiments, the case where it is applied to an NPN bipolar type semiconductor integrated circuit device has been described, but it can be similarly applied to a PNP bipolar type semiconductor integrated circuit device, and similar effects and effects can be obtained. Of course you can get it.

[0045]

[Effects of the Invention] As described above in detail through the examples,
According to the method for manufacturing a semiconductor integrated circuit device according to the first aspect of the present invention, in a semiconductor integrated circuit device comprising a bipolar transistor having a two-layer polycrystalline silicon structure on a semiconductor substrate, A first layer amorphous silicon film is formed by the CVD method, and an interlayer insulating film is formed on the first layer amorphous silicon film by carbon dioxide at a temperature that does not transform the first layer amorphous silicon film into a polycrystalline silicon film.
The interlayer insulating film and the corresponding portion of the emitter layer of the first amorphous silicon film, which will become the electrode extraction surface, are selectively opened until the silicon surface is exposed. Since the base layer is formed on the silicon surface and the first layer amorphous silicon film is transformed into the first layer polycrystalline silicon film, the amorphous silicon film is formed more easily than the polycrystalline silicon film. There are few irregularities on the surface, and
In the case of an amorphous silicon film, since there are no grains, the etching rate does not increase along the grain interface as it does with polycrystalline silicon, and unlike the conventional example described above, the etching rate does not increase along the grain interface. When compared to the silicon surface exposed by etching, the occurrence of unevenness can be reduced as much as possible and as a result,
A silicon surface with improved unevenness in this manner can satisfactorily and effectively suppress recombination current during transistor operation.

Further, according to the method for manufacturing a semiconductor integrated circuit device according to the second aspect of the present invention, two
In a semiconductor integrated circuit device constituted by a bipolar transistor having a layered polycrystalline silicon structure, a second layer amorphous silicon film for drawing out the emitter electrode is placed on the exposed silicon surface which becomes the electrode drawing surface of the emitter layer, CVD at a temperature that does not transform into a polycrystalline silicon film.
method, implanting impurities of a required conductivity type into the second layer amorphous silicon film, forming an emitter layer within the silicon plane through the second layer amorphous silicon film, and Since the film is transformed into a second layer polycrystalline silicon film, the number of clusters can be suppressed by transforming the second layer amorphous silicon film into an N-type second layer polycrystalline silicon film. The crystal grains are large and the grain interfaces are reduced, and as a result, unlike the case where a polycrystalline silicon film is grown from the beginning, the polycrystalline silicon that has been transformed from amorphous for drawing out the emitter electrode is grown. The conductivity of the film is improved, and as a result, the emitter resistance can be effectively reduced.

Furthermore, the number of manufacturing steps in each of the first and second invented methods is exactly the same as in the conventional method, and there is no need to increase the number of steps, and it is easy to implement. It has excellent features such as:

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view schematically showing a first step of a method for manufacturing a bipolar semiconductor integrated circuit device using a two-layer polycrystalline silicon film according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view schematically showing a second step of the method according to the embodiment.

FIG. 3 is a cross-sectional view schematically showing the third step of the method according to the above embodiment.

FIG. 4 is a cross-sectional view schematically showing the fourth step of the method of the above embodiment.

FIG. 5 is a cross-sectional view schematically showing the fifth step of the method according to the embodiment.

FIG. 6 is a cross-sectional view schematically showing the sixth step of the method according to the embodiment.

FIG. 7 is a cross-sectional view schematically showing the seventh step of the method according to the above embodiment.

FIG. 8 is a cross-sectional view schematically showing the eighth step of the method according to the embodiment.

FIG. 9 is a cross-sectional view schematically showing the ninth step of the method of the embodiment.

FIG. 10 is a cross-sectional view schematically showing a first step of a method for manufacturing a bipolar semiconductor integrated circuit device using a two-layer polycrystalline silicon film according to a conventional example.

FIG. 11 is a cross-sectional view schematically showing a second step of the conventional method.

FIG. 12 is a cross-sectional view schematically showing the third step of the conventional method.

FIG. 13 is a cross-sectional view schematically showing the fourth step of the conventional method.

FIG. 14 is a cross-sectional view schematically showing the fifth step of the conventional method.

FIG. 15 is a cross-sectional view schematically showing the sixth step of the conventional method.

FIG. 16 is a cross-sectional view schematically showing the seventh step of the conventional method.

FIG. 17 is a cross-sectional view schematically showing the eighth step of the conventional method.

FIG. 18 is a cross-sectional view schematically showing the ninth step of the conventional method.

FIG. 19 is a cross-sectional view schematically showing the tenth step of the conventional method.

FIG. 20 is a cross-sectional view schematically showing the eleventh step of the conventional method.

[Explanation of symbols]

1 P- type semiconductor substrate 2 N+ type buried layer 3 N- type epitaxial layer 4 P+ type channel cut layer 5 Isolation insulating layer 6 First interlayer insulating film 7 N+ type collector wall layer 8a P+ type intrinsic layer Base layer 8b P+ type external base layer 9 N+ type emitter layer 10 Second interlayer insulating film 11a P type first polycrystalline silicon film 12a transformed from amorphous N type second polycrystalline silicon film transformed from amorphous Silicon film 13 Silicide film 14 Third interlayer insulating film 15 Aluminum wiring 16 Barrier metal layer 17 Base electrode 18 Emitter electrode 19 Collector electrode 20 First CVD oxide film

Claims (2)

[Claims] 1. In a semiconductor integrated circuit device comprising a bipolar transistor having a two-layer polycrystalline silicon structure on a semiconductor substrate, a base electrode for leading out a base electrode corresponding to the first layer of the two-layer polycrystalline silicon structure. forming a first layer amorphous silicon film by the CVD method, and forming an interlayer insulating film by the CVD method on the first layer amorphous silicon film at a temperature at which the first layer amorphous silicon film is not transformed into a polycrystalline silicon film. a step of selectively opening the interlayer insulating film and the corresponding portion of the first layer amorphous silicon film that will become the electrode extraction surface of the emitter layer until the silicon surface is exposed; A semiconductor integrated circuit comprising at least the steps of: sequentially forming a base layer and an emitter layer on a silicon surface, and transforming the first layer amorphous silicon film into a first layer polycrystalline silicon film. Method of manufacturing the device. 2. In a semiconductor integrated circuit device comprising a bipolar transistor of a two-layer polycrystalline silicon structure on a semiconductor substrate, the two-layer A second layer amorphous silicon film for leading out the emitter electrode corresponding to the second layer of the polycrystalline silicon structure is formed by CVD at a temperature at which the second layer amorphous silicon film is not transformed into a second layer polycrystalline silicon film. and the step of
a step of implanting an impurity of a required conductivity type into a layer amorphous silicon film, forming an emitter layer within the silicon surface through the second layer amorphous silicon film into which the impurity is implanted, and forming an emitter layer within the silicon surface; A method of manufacturing a semiconductor integrated circuit device, comprising at least the step of transforming an amorphous silicon film into a second layer polycrystalline silicon film.