JP2680358B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention mainly relates to a method for manufacturing a transistor for an analog operation circuit in a high-speed logic operation or in a high frequency region.

(Prior Art) A transistor for high-speed logic operation or circuit operation in a high-frequency region suppresses base transit time by shallow diffusion, and reduces collector-substrate junction capacitance by an insulator element isolation technique. Furthermore, the fine lithographic technique and the self-alignment technique have suppressed the parasitic capacitance between the base and the collector and between the base and the emitter, and have also reduced the base resistance to improve the performance.

U.S. Pat. No. 4,243,362 discloses a method of manufacturing a high-speed bipolar device using a self-alignment technique and a polysilicon double diffusion technique, the outline of which will be described with reference to FIGS.

That is, an epitaxial layer 52 is deposited on a second conductivity type (p type) semiconductor substrate 50 in which a first conductivity type (n type) impurity region 51 (hereinafter referred to as a buried region) is formed. An island region is set by the formed plurality of separation regions 53. After forming the diffusion layer 54 of the second conductivity type in this island region,
A second conductivity type impurity is added to the deposited undoped polycrystalline silicon 55, and an insulator layer 56 is further grown to obtain FIG. 5A.

Next, as shown in FIG. 5b, the insulating layer 56 and the polycrystalline silicon are formed.
Highly accurate so-called RIE (Reactive Ion Etching) 55
After the opening, the added impurity is introduced and diffused into the epitaxial layer 52 to set the base region 57 (see FIG. 5c). As a result, as shown in FIG. 5c, the portion of the epitaxial layer 52 corresponding to the opening acts as the internal base 58, and the emitter 59 is formed therein.

Furthermore, the Inter National Electron Me held in 1985
“A High-Speed Bipolar LAI Process using Self A” presented by Kazuya Kikuchi in eting, p, p 420-423.
ligned Double Diffusion Polysilicon Technology "will be described with Figure 6 a to e. This process is that a combination of silicon nitride (Si ₃ N ₄₎ layer and a polycrystalline silicon differs from the method shown in Figure 5.

After the undoped polycrystalline silicon layer 61 is deposited on the silicon semiconductor substrate 60, the second conductivity type B is introduced into the polycrystalline silicon layer 61 by the ion implantation method as shown in FIG. 6a. At the same time, the heat treatment is performed at 950 ° C. for 30 minutes, but B is introduced into the silicon semiconductor substrate 60 through the polycrystalline silicon layer 61. As a result, a base region 62 having a depth of 150 nm is formed as apparent from FIG.

FIG. 6c shows a state in which arsenic is ion-implanted into the polycrystalline silicon layer 61 to form the emitter 63. However, by performing a heat treatment step at 900 ° C. for 30 minutes, the polycrystalline silicon is Arsenic is introduced and diffused into the silicon semiconductor substrate 60 through the layer 61 to form an emitter 64 having a depth of 50 nm as shown in FIG. 6d. FIG. 6e shows a cross-sectional view of the completed device, but its description is omitted because it has little relation to the present invention.

A base region having a width of 100 nm is set by this series of steps. As described above, according to this method, the base and the emitter of the silicon semiconductor substrate can be formed without any special influence by the two ion implantation steps performed on the specific position of the polycrystalline silicon.

(Problems to be Solved by the Invention) In the double diffusion method using polycrystalline silicon according to the method shown in FIG. 5, RIE is used. However, the silicon semiconductor layer facing the polycrystalline silicon, that is, the intrinsic There is a defect that the RIE method damages the operating region and the device deteriorates.

In the other method disclosed in IDEM, the impurities contained in the oxide film are taken into the oxide film by the oxidation step of polycrystalline silicon, so that the sheet resistance of the polycrystalline silicon layer that is also used for extracting the base electrode is increased, There is a drawback that the base resistance increases.

The present invention provides a novel method for manufacturing a semiconductor device that eliminates such drawbacks. In particular, a method that does not damage the intrinsic operating region and has high processing accuracy is used, and further, the sheet resistance of the electrode extraction layer is reduced. Can be low enough.

(Structure of the Invention) The present invention relates to a step of forming an island region by a plurality of isolation regions provided in a first conductivity type semiconductor layer, and the first conductivity type semiconductor layer including an intrinsic operation region to be formed in this island region. A step of forming a convex dummy pattern in which a first insulating layer, a first polycrystalline silicon layer, and a second insulating layer are laminated in this order on the surface portion; and a first step of forming the convex dummy pattern A step of depositing a third insulator layer on the exposed surface of the polycrystalline silicon layer and the surface portion of the first conductivity type semiconductor layer, and a third insulation layer covering the surface portion of the first conductivity type semiconductor layer. A step of removing, a step of coating the exposed surface of the first conductive type semiconductor layer including the convex dummy pattern with a second polycrystalline silicon layer containing an impurity exhibiting a second conductive type, and the convex dummy This second polycrystalline silicon corresponding to the side and top of the pattern A step of removing the element layer, a step of depositing a fourth insulator layer on the exposed surface of the second polycrystalline silicon layer, and a third insulator corresponding to the side surface and the top surface of the convex dummy pattern. Removing the first insulating layer and the second insulating layer by an anisotropic etching process to expose the first polycrystalline silicon layer and planarize the fourth insulating layer; Introducing an impurity having a second conductivity type contained in the crystalline silicon layer into the first conductivity type semiconductor layer to form an external base; and removing the first polycrystalline silicon layer to form a recess. A step of forming a second conductivity type inner base surrounded by the outer base through the first insulator layer exposed by the formation of the recess in the first conductivity type semiconductor layer; After depositing a third polycrystalline silicon layer on the Forming a residual film, forming an opening in the exposed first insulator layer portion, depositing a doped polycrystalline silicon layer containing an impurity exhibiting the first conductivity type into the opening, A step of introducing an impurity having a first conductivity type contained in the doped polycrystalline silicon layer into the second conductivity type inner base layer to form an emitter.

(Operation) The present invention discloses a method of manufacturing a semiconductor device that requires high-speed operation by skillfully using an anisotropic etching process and a convex dummy pattern. This is because recent semiconductor devices that are required to operate at high speed employ a method of suppressing X _J in the impurity region, which is indispensable for the formation of PN junctions. Covered by. However, also in the present invention, a so-called Shallow Junction in which X _J is formed in a range of about 2 μm to 0.05 μm is applied, and therefore the influence of various steps must be eliminated.

In the present invention, from the viewpoint of preventing the adverse effect of the RIE method with good processing accuracy, the convex dummy pattern is adopted, and furthermore, in order to avoid the oxidation of the doped polycrystalline silicon, an oxide layer is provided on its side surface. The method was adopted to prevent the increase in sheet resistance caused by the conventional technique.

That is, the intrinsic operation region is formed in the first conductivity type epitaxial layer, that is, the semiconductor layer that forms the island region obtained by installing the element isolation region, and the convex dummy pattern is formed in the semiconductor layer including the region. It this is,
The first dummy layer, the first polycrystalline silicon layer, and the second insulator layer form the convex dummy pattern, and these are formed by the RIE method with high processing accuracy.
Damage to the conductive semiconductor layer was prevented as much as possible.

As a means for forming a functional element in the first conductive type semiconductor layer forming the island region, first, the convex dummy pattern is made substantially flat by an etch back method. This etch back step is performed twice as shown in FIGS. 1d and 1e, and before that, a second polycrystalline silicon layer 11 (see FIG. 1d) is coated,
After this etch back step, as shown in FIG.
After the insulating layer 13 is deposited, an etch back process is performed again to remove the insulating layer 9 covering the top surface of the convex dummy pattern 6.

Further, the first polycrystalline silicon layer 8 is removed to form the concave portion, but before that, the second conductive type impurities are introduced and diffused into the first conductive type semiconductor layer to form the external bases 15, 15. A third polycrystalline silicon layer 18 is deposited and patterned in the recess, and a film 18 is left on the sidewall of the third polycrystalline silicon layer 18 and is used as a mask through the opening formed in the exposed first insulating layer 7. Arsenic is introduced into the first conductivity type semiconductor layer and diffused to form an emitter. The internal base is formed before forming the emitter.

As described above, in the present invention, the damage is prevented by the RIE process, and the side wall method is applied to the convex dummy pattern to suppress the adverse effect due to the oxidation of the polycrystalline silicon layer. Therefore, the characteristics required as a transistor for an analog operation circuit in a high speed logic operation or a high frequency region are satisfied.

(Embodiment) An embodiment of the present invention will be described in detail with reference to sectional views of the steps of FIGS. 1A to 1G and other embodiments of FIGS. 2 to 4. 4
A semiconductor substrate 1 containing a second conductivity type impurity such as B of about 10 ¹⁴ cm ^-3 is prepared, and the surface of the semiconductor substrate 1 is selectively made of arsenic or the like.
A first conductivity type region 2 is formed by introducing and diffusing conductivity type impurities by an ion implantation method. Thereafter depositing a first conductivity type impurity of about 1 × 10 ¹⁶ cm ^-3 semiconductor layer 3 having a thickness of 1~2μm containing phosphorus or the like by epitaxial growth method. The so-called auto-doping (Auto Doping) generated by heating during this process
The first conductivity type buried region 2 is installed near the boundary between the first conductivity type semiconductor layer 3 and the second conductivity type semiconductor substrate 1 by Dopping) or the like, and functions as a so-called first conductivity type buried region 2. The insulator 4 is used to form the island region 5 in the first conductivity type semiconductor layer 3 because a relatively thick element isolation region is required. Of course, other methods such as a diffusion method are also applicable. it can.

In the present invention, the convex dummy pattern 6 including the position corresponding to the intrinsic operation region in the island region 5 is formed. The specific method is to form a silicon dioxide layer, that is, the first insulator layer 7 on the surface portion of the first conductivity type semiconductor layer 3 by a thermal oxidation method or the like, and then use LPCVD method to form a substantially rectangular film having a thickness of 500 to 1000 angstroms. -Shaped first polycrystalline silicon layer 8 and thickness
500 to 1000 angstroms, eg silicon nitride layer Si ₃
Deposit N ₄ 9, the second insulator layer 9. Subsequently, a publicly known photo engraving process is performed to form the convex dummy pattern 6, and the sectional view shown in FIG. 1A is obtained.

When the convex dummy pattern 6 is exposed to an oxidizing atmosphere,
A third insulating layer 10 made of silicon dioxide is coated on the exposed portion of the conductive type semiconductor layer 3 and on the side surface of the polycrystalline silicon layer 8 to obtain the sectional structure shown in FIG. 1b.

Further, RIE is performed from CF ₄ and H _{2 under} the conditions of a flow rate of 20 sccm to 10 sccm, a power of 350 W, and a pressure of 1.3 Pascal to remove only the third insulating layer 10 covering the exposed portion of the first conductivity type semiconductor layer 3. As a result, the sectional structure shown in FIG.

Subsequently, a second polycrystalline silicon layer 11 of the second conductivity type, for example B, having a thickness of 500 to 1000 Å is deposited on the entire surface by LPCVD, and a resist layer 12 is further formed as shown in FIG. 1d. After applying it to C1, radicals such as C1 (Radi
The second polycrystalline silicon layer 11 deposited on the top surface and side surfaces of the convex dummy pattern 6 is removed by performing RIE including cal).

Then, as is apparent from FIG.
After coating the fourth insulator layer 13 made of silicon oxide, a resist layer 14 is applied. However, the resist layer 14 is thinned only on the top surface of the convex dummy pattern 6. Further CF
RIE using a gas such as ₄ results in a sectional structure shown in FIG. This is the structure after the end of the second etch back step, covering the side surface of the first polycrystalline silicon layer 8 and
In addition to the third insulating layer 10 located between the first insulating layer 13 and the first polycrystalline silicon layer 8, a flat fourth insulating layer 13 remains.

As a result, the top surface of the first polycrystalline silicon layer 8 is slightly projected from the fourth insulator layer 13. The RIE conditions in the second etch back step are the same as those in the first time, and the etching rate (Etching Rate) of the resist is smaller than that of the insulating layer and silicon dioxide deposited by CVD. The crystalline silicon layer 8 is not etched and the RI
E process is completed.

Then, B is thermally diffused from the second-conductivity-type B-doped second polycrystalline silicon layer 11 to the second-conductivity-type semiconductor layer 3 at a surface concentration of about 1 × 10 ₂₀ cm ⁻³ or more to obtain the second conductivity. External base of mold 1
Install 5,15. Furthermore, by moving the radicals generated by plasma using microwaves to a position other than the generation site,
CDE (Chemical Dry) capable of isotropic or anisotropic etching
By Etching) apparatus, CF _{4/0 2} by isotropic etching process using a by removing the first polycrystalline silicon layer 8 recesses (not shown) is formed.

Further, as shown in FIG. 1g, the second conductivity type, eg, B, is passed through the first insulator layer 7 located at the bottom of the recess.
The conductivity type semiconductor layer 3 is injected to complete the inner base 16 having a peak concentration of about 10 ¹⁸ cm ⁻³ surrounded by the outer base.

Furthermore, the process shifts to the step of forming the emitter region 17 essential to the transistor, that is, the intrinsic operating region. After partially opening the first insulator layer 7 located at the bottom of the recess, depositing the third polycrystalline silicon 18 doped with arsenic, and then performing the anisotropic etching process by RIE to form the first insulator. A residual film 18 overlying the layer 7 is placed on the side wall occupying the thickness direction of the recess.

Arsenic is introduced into the base layer 16 and diffused using the remaining film 18 as a mask to form an emitter 17 having a surface concentration of about 10 ²¹ cm ^-3 .
Prior to the arsenic-introduced diffusion, a polycrystalline layer 19 is deposited by arsenic doping so as to cover the opening and the fourth insulating layer 13 and serve as a diffusion source.

FIG. 2 shows an example of using polycide for extracting the base electrode, but the same parts will be described by the same reference numerals.

During the formation of the polycide layer 20, the gap between FIG.
The metal forming the silicide layer 21, such as Mo or Ti, is deposited.
and the polycrystalline silicon layer 22 is continuously or selectively formed by a subsequent heat treatment step. The other structure and manufacturing method are the same as those of the bipolar element shown in FIG.

In the step of forming the polycide layer 20, the silicide layer 21 may be planarized by using it in combination with a resist and the second polycrystalline silicon layer 11 may be selectively covered before the formation of the second insulator layer 23.

FIG. 3 shows an example in which the present invention is applied to a MOS transistor, and the VTH control channel region 25 is previously installed by ion implantation or the like. Further, a chemically pure gate oxide film 26 is formed before the formation of the first doped polycrystalline silicon layer 8, and this convex second doped polycrystalline silicon layer 11 can be used as a gate electrode.

The formation of the source / drain regions 27 and 28 necessary for exhibiting the function as the MOS type transistor is performed by using the second doped polycrystalline silicon layer 11 as a diffusion source.

In the MOS transistor shown in FIG. 4, lightly doped layers 28 and 29 are provided, and a sidewall 30 is provided at a position opposite to the layers 28 and 29, and a convex shape formed continuously from the sidewall 30 is provided. Second doped polycrystalline silicon layer 11
And is used as a diffusion source for the source and drain as described above.

Further, the gate oxide film formed adjacent to and connected to the MOS type transistor is formed before the second doped polycrystalline silicon layer 11 is provided in order to ensure a chemically clean film.

(Advantages of the Invention) A high-speed transistor can be installed by a self-alignment method without damaging an emitter functioning as an intrinsic region, and further, a sheet resistance of a lead-out electrode to which a silicide is applied can be reduced to 10 ohm / square. The material of the extraction electrode is
The present invention is not limited to this, and doped polycrystals can be applied as described above. Again, the sheet resistance is
You can avoid the situation where the ohms rise to 1K ohms. There is also an advantage that the characteristics required for the semiconductor device can be achieved relatively easily.

[Brief description of the drawings]

1A to 1G are sectional views showing each step of an embodiment according to the present invention, FIGS. 2 to 4 are sectional views of other embodiments, FIGS. 5A to 5C, and 6A to 6C. 3E is a sectional view showing a step of the conventional technique. 1: semiconductor substrate, 2: buried region, 3: first conductivity type semiconductor layer, 4: isolation region, 5: island region, 6: convex dummy pattern, 7: first insulator layer, 8: first multi-layer Crystalline silicon 9: second insulating layer, 10: third insulating layer 11: second polycrystalline silicon, 12, 14: resist 13: fourth insulating layer, 15, 16: base layer 17: Emitter region, 18: Remaining film (third polycrystalline silicon) 19: Doped polycrystalline layer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP 61-172369 (JP, A) JP 63-17558 (JP, A) JP 61-102063 (JP, A) JP 62- 291176 (JP, A) JP-A-59-175766 (JP, A)

Claims (1)

(57) [Claims] 1. A step of forming an island region by a plurality of isolation regions provided in a first conductivity type semiconductor layer, and a surface portion of the first conductivity type semiconductor layer including an intrinsic operation region to be formed in the island region, A step of forming a convex dummy pattern in which a first insulating layer, a first polycrystalline silicon layer and a second insulating layer are laminated in this order; and a first polycrystalline silicon forming the convex dummy pattern Depositing a third insulator layer on the exposed surface of the layer and the surface portion of the first conductivity type semiconductor layer; and removing the third insulator layer covering the surface portion of the first conductivity type semiconductor layer surface. A step of coating the exposed surface of the first conductive type semiconductor layer including the convex dummy pattern with a second polycrystalline silicon layer containing an impurity exhibiting the second conductive type, and a side surface and a top of the convex dummy pattern. Remove this second polycrystalline silicon layer corresponding to the face A step of depositing a fourth insulator layer on the exposed surface of the second polycrystalline silicon layer, the third insulator layer and the second insulator layer corresponding to the side surface and the top surface of the convex dummy pattern. Removing the first insulating layer by an anisotropic etching process to expose the first polycrystalline silicon layer and planarize the fourth insulating layer; and Introducing an impurity having the second conductivity type into the semiconductor layer of the first conductivity type to form an extrinsic base; removing the first polycrystalline silicon layer to form a recess; Forming a second conductivity type inner base surrounded by the outer base on the first conductivity type semiconductor layer through the first insulator layer exposed by the recess formation; Leaving a third polysilicon layer on the sidewalls of the recess after depositing a polysilicon layer Forming an opening, providing an opening in the exposed first insulator layer portion, depositing a doped polycrystalline silicon layer containing an impurity exhibiting the first conductivity type in the opening, and the second And diffusing an impurity having a first conductivity type contained in the doped polycrystalline silicon layer into a conductivity type internal base layer to form an emitter.