JP3278493B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a heterojunction bipolar transistor.

[0002]

2. Description of the Related Art Bipolar transistors (hereinafter referred to as Bip transistors)
Tr) is composed of an emitter base and a collector, and its operation is based on a so-called amplifying action in which the value of the collector current greatly changes due to a slight difference in the base current. That is, by applying a forward voltage between the emitter and the base and injecting a hole from the base to the emitter, the amount of electrons injected from the emitter to the base and reaching the collector is controlled. The ratio between the collector current due to the electrons and the base current due to the hole is an approximate current amplification factor _hFE .

FIG. 16 is a sectional view showing the structure of a conventional homozygous BipTr. In the drawing, reference numeral 1 denotes a semiconductor substrate (hereinafter, referred to as a substrate) made of, for example, a p-type silicon single crystal, 2 denotes an n ⁺ -type buried layer serving as a collector wall formed so as to be embedded in the substrate 1, and 3 denotes a buried layer. An n ⁻ -type epitaxial layer serving as a collector formed on the n ⁺ -type buried layer 2, 4 is an isolation oxide film for electrically isolating elements from each other, and 5 is a p-type channel cut diffusion layer below the isolation oxide film 4. , 6 contact the lower n ⁺ -type buried layer 2 to form an n ⁺ -type collector lead-out layer formed in the n ^-- type epitaxial layer 3, 7 denotes a base diffusion layer, and 7a and 7b denote base diffusion layers. Among them, a p-type intrinsic base region and a p-type base lead-out region, 8 is a base electrode made of p-type polycrystalline silicon, 9 is an n ⁺ -type emitter diffusion layer, and 10 is an n-type polycrystalline silicon. Emitter electrode. 11 to 14 are silicon oxide films;
Reference numeral 13 denotes an insulating oxide film between the emitter electrode 10 and the base electrode 8, reference numeral 14 denotes a side wall, reference numeral 15 denotes a passivation film, and reference numeral 16 denotes a metal wiring layer.

Since the junction capacitance formed by the collector 3 and the base 7a greatly hinders the high-speed operation of the BipTr, it is desirable to reduce this area as much as possible.
Further, the resistance of the base 7a is reduced, and
It is also necessary to reduce the width of a so as to shorten the traveling time of electrons to increase the speed. For this reason, the conventional BipTr configured as described above requires the base electrode 8 in the manufacturing method.
An opening pattern for forming the emitter 9 is formed, and a side wall 14 is formed on the side wall of the base electrode 8 in a self-aligned manner, so that the area of the base 7a and the base electrode 8,
A method of shortening the distance between the emitters 9 is generally adopted. In the formation of the emitter 9, shallow coupling is formed by diffusing arsenic or phosphorus implanted into the emitter electrode 10 of polycrystalline silicon into the underlying silicon substrate 1.

However, in the conventional BipTr, when the width of the base 7a is reduced with miniaturization and high speed operation, a depletion layer between the emitter 9 and the base 7a and a depletion layer between the base 7a and the collector 3 are formed. Then, punch-through occurs, and the resistance of the base 7a is increased in a narrow portion of the base 7a. Therefore, by increasing the impurity concentration in the base 7a, the extension of the depletion layer to the base 7a side is suppressed to prevent punch through, and the base 7a
It can be lowered a resistance, n-type impurity concentration and the base in the emitter 9 - scan 7a within p-type ratio of the impurity concentration approximately determined by BipTr the current amplification factor h _FE is, were those lowered.

As a method for solving such a problem, a heterojunction Bi using a silicon germanium (SiGe) base having a narrower band gap than silicon has been conventionally used.
pTr is considered. In this heterojunction BipTr, the difference between the band gaps of silicon germanium and silicon having a narrow band gap is made sufficiently larger than the difference between the conduction band gaps, so that the impurity concentration in the base can be increased. , base for the electronic - since the barrier can make lower, electrons and Ho - - energy of the scan-side can be kept high current ratio Le, it does not lead to deterioration of the current amplification factor h _FE. Therefore, the base resistance can be kept low and the base width can be narrowed, so that it is possible to cope with high-speed operation and realize a high f _T (cutoff frequency).

A BipTr using silicon germanium as a base is, for example, an IEEE, Electron Device L.
etters, Vol. 10, No. 12, 1989, P, 5
34, the structure of which is shown in FIG. In the figure, 1-3 and 6 are the same as the BipTr conventional homojunction shown in FIG. 16, 17 off I - field oxide film, 18 p ⁺ -type polycrystalline consisting of silicon base - scan electrode, 19 SiGe composed of p-type silicon germanium
A base layer, 20 is a silicon oxide film, 21 is a silicon nitride film, and 22 is an emitter layer made of n ⁺ -type polycrystalline silicon. The structure of this heterojunction BipTr extends over the base electrode 18. An SiGe base layer 19 is provided, and an emitter layer 22 is formed using a silicon oxide film 20 and a silicon nitride film 21 thereon as an insulating film.
This is formed on the upper layer 19 of the semiconductor device.

The heterojunction BipT thus configured is
The method for manufacturing r will be described below with reference to FIGS.
First, a field oxide film 17 is formed on the entire surface of the substrate 1 on which the n ⁺ type buried layer 2 and the n type epitaxial layer 3 have been formed, and the SiGe base layer 19 and the base A region for forming the electrode 18 is opened. After depositing the p ⁺ -type polycrystalline silicon film 18a followed over the entire surface of the substrate 1, the Fi - in the opening of the field oxide film 17 p ⁺
The base region is opened by selectively removing the type polycrystalline silicon film 18a (FIG. 18). Next, on the entire surface of the substrate 1, p
A silicon germanium film 19a having a type impurity introduced therein is grown. At this time, at least the n-type epitaxial layer 3
Is formed so that the silicon germanium film 19a grows epitaxially. Thereafter, a silicon oxide film 20 is deposited on the entire surface of the silicon germanium 19a (FIG. 19).

Next, a silicon oxide film 20, a silicon germanium film 19a and a p ⁺ type polycrystalline silicon film 18a
Are successively selectively removed by etching, and the SiGe base layer 19 and the base electrode 18 are formed by patterning (FIG. 20). Next, a silicon nitride film 21 is deposited on the entire surface of the substrate 1, and this silicon nitride film 21 and the underlying film are deposited.
By selectively etching and removing the field oxide film 17, an opening 23 is formed in the silicon nitride film 21 and the field oxide film 17 to form the n-type epitaxial layer 3.
Expose the surface. Subsequently, an n-type impurity is introduced into the substrate 1 through the opening 23 to form an n ⁺ -type collector lead-out layer 6 (FIG. 21).

Next, the silicon oxide film 20 in the base region is formed.
Then, the silicon nitride film 21 is selectively etched away, and an opening 24 is provided at the center of the base region to expose the SiGe base layer 19 (FIG. 22). Next, an n ⁺ -type polysilicon film is deposited on the entire surface of the substrate 1 so as to fill the opening 24, and is patterned to form an emitter layer 22 (FIG. 23). Next, the silicon nitride film 21, the silicon oxide film 20, and the SiGe base layer 19 are sequentially etched to form an opening on the base electrode 18 (see FIG. 17), and thereafter metal wiring is performed. To complete the BipTr.

[0011]

In the above-described conventional heterojunction BipTr, a self-alignment is not used in the manufacturing method, so that a margin for lithography is required. This increases the base area,
The parasitic capacitance formed by the base layer 19 and the collector 3 becomes large, which hinders the high-speed operation of the BipTr. When the opening 24 is formed by etching the silicon oxide film 20 and the silicon nitride film 21 to form the emitter layer 22, the surface of the exposed underlying SiGe base layer 19 is damaged. Therefore, the emitter layer 2
When the junction 2 is formed to form the junction between the emitter 22 and the base 19, there is a problem that the reliability of the BipTr is deteriorated, for example, a level is generated at the interface and a leak current is generated.

[0012] The present invention has been made to solve the above problems, without reducing the current amplification factor h _FE of BipTr, base - can increase the impurity concentration of the scan, high f _T A semiconductor device capable of realizing a reduction in leakage current due to generation of an interface state between an emitter and a base, and miniaturization by reducing a base area.
It is an object of the present invention to obtain a semiconductor device capable of achieving high speed, and to provide a manufacturing method suitable for the semiconductor device.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor device having a second conductivity type formed on a semiconductor substrate having a silicon region serving as a collector of a first conductivity type and an insulating region. A conductive type intrinsic base region, a base extraction layer formed adjacent to the outside and having the same conductivity type as the intrinsic base region and having a higher concentration, and formed on the intrinsic base region; An emitter layer of the first conductivity type,
A semiconductor device having an inter-base insulating film and an emitter electrode connected to the emitter layer, wherein the intrinsic base region has a lower portion of silicon germanium (hereinafter referred to as S).
iGe) base layer and upper silicon (hereinafter referred to as S
i) and a base layer.
On the base layer, the emitter layer made of a silicon film is formed at the center, and the Si base layer is formed on the emitter layer, and the base extraction layer is formed on the collector from the insulating region. The base extraction layer formed over the collector and having the upper portion of the collector is formed by high-concentration Si base diffusion.
Layer and the high concentration SiGe base thereon - scan layer and the high concentration Si base thereon - is constituted by a scan layer, the insulating region on the portion of the base - scan lead layer is a heavily doped polycrystalline SiGe layer thereof And the upper high-concentration polycrystalline Si layer.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a semiconductor substrate having a silicon region of a first conductivity type and an insulating region; As the crystal grows, silicon germanium of the second conductivity type and silicon of the first conductivity type are continuously grown to form a SiGe thin film and polycrystalline Si.
A first step of forming a Ge thin film and a Si thin film and a polycrystalline Si thin film thereon, and a silicon oxide film, a silicon nitride film thereon, and a Emitter composed of silicon oxide film
A second step of forming a base-forming pattern, and ion implantation of impurities of the second conductivity type into the Si thin film and the polycrystalline Si thin film other than the emitter-base forming pattern region. A third step of introducing, and then forming a sidewall made of a silicon oxide film on the side wall of the emitter base forming pattern, and forming the side wall of the emitter base forming pattern and the side wall. Si above the region
The SiG in and below the thin film and the polycrystalline Si thin film
a fourth step of introducing an impurity of the second conductivity type into the e thin film and the polycrystalline SiGe thin film by ion implantation;
Then, the semiconductor substrate is subjected to a heat treatment to activate the introduced impurities, thereby to form a second conductivity type intrinsic base region comprising a SiGe base layer and a Si base layer thereon.
And a high-concentration diffusion of the second conductivity type comprising a high- concentration SiGe base layer, an upper and lower high-concentration Si base layer, a high-concentration polycrystalline SiGe layer, and a high-concentration polycrystalline Si layer thereon Forming a layer, thereby forming a first conductive type silicon film.
A fifth step of defining the emitter region, and then removing the silicon oxide film and the sidewall at the top of the emitter base formation pattern, and then forming the high-concentration polycrystalline Si layer and the high-concentration polycrystalline Si layer. By selectively removing the high-concentration polycrystalline SiGe layer, the high-concentration diffusion layer is patterned.
A sixth step of forming a base extraction layer by performing
Then, a silicon oxide film sufficiently thicker than the silicon oxide film under the silicon nitride film is formed on a portion of the emitter base forming pattern which is not covered with the silicon nitride film. A seventh step of forming an emitter-base insulating film covering the exposed portions of the surface and side surfaces of the base layer and the base extraction layer, and thereafter removing the silicon nitride film and the silicon oxide film therebelow. And

According to a third aspect of the present invention, there is provided a semiconductor device comprising:
The intrinsic base region is composed of two layers, a lower SiGe base layer and an upper Si base layer.
On the Ge base layer, an emitter layer made of a silicon film is formed at the center portion, and the Si base layer is formed on the emitter layer, and the base extraction layer is formed on the collector region from above the collector. The upper layer is formed of a high-concentration polycrystalline Si film, and the lower layer is formed of a high-concentration SiGe base layer on the collector and a high-concentration S
High concentration polycrystalline SiG on i-base layer and insulating region
It is composed of an e layer and a high concentration polycrystalline Si layer thereon.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device, a semiconductor substrate having a first conductivity type silicon region and an insulating region is epitaxially grown on the silicon region and multi-layered on the insulating region. As the crystal grows, silicon germanium of the second conductivity type and silicon of the first conductivity type are continuously grown to form a SiGe thin film and polycrystalline Si.
A first step of forming a Ge thin film and a Si thin film and a polycrystalline Si thin film thereon, and a silicon oxide film, a silicon nitride film thereon, and a Emitter composed of silicon oxide film
A second step of forming a base-forming pattern, and ion implantation of impurities of the second conductivity type into the Si thin film and the polycrystalline Si thin film other than the emitter-base forming pattern region. A third step of introducing, and then forming a sidewall made of a silicon oxide film on the side wall of the emitter base forming pattern, and excluding the region of the emitter base forming pattern and the side wall. A fourth step of selectively growing a second-conductivity-type high-concentration polycrystalline silicon film on the Si thin film and the polycrystalline Si thin film, and then activating the introduced impurities by heat-treating the semiconductor substrate; Forming an intrinsic base region of the second conductivity type and a high-concentration diffusion layer of the second conductivity type;
A fifth step of defining a region, and then removing the silicon oxide film and the sidewall at the top of the emitter base formation pattern, and then patterning the high concentration diffusion layer.
A sixth step of forming a base extraction layer by performing
Then, a silicon oxide film sufficiently thicker than the silicon oxide film under the silicon nitride film is formed on a portion of the emitter base forming pattern which is not covered with the silicon nitride film. A seventh step of forming an emitter-base insulating film covering the exposed portions of the surface and side surfaces of the base layer and the base extraction layer, and thereafter removing the silicon nitride film and the silicon oxide film therebelow. And

According to a fifth aspect of the present invention, there is provided a semiconductor device comprising:
A metal silicide layer is formed on an emitter electrode and a base extraction layer.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor, after the formation of the emitter electrode, the emitter-base insulating film other than the emitter electrode region is removed and the emitter electrode and the base extraction layer are removed. A metal silicide layer is selectively formed.

[0019]

In the semiconductor device according to the present invention, as described above, the intrinsic base region where the junction with the collector and emitter layers is formed is a heterojunction formed of silicon germanium having a narrower band gap than silicon. It can be increased impurity concentration of the source region, - the intrinsic base without reducing the current amplification factor h _FE of BipTr
High f _T can be realized. In addition, S serving as a SiGe base layer
Since the iGe thin film and the Si thin film serving as the emitter layer are continuously grown, the generation of the interface state between the emitter and the base can be prevented, and the leak current can be reduced. Further, since a sidewall is formed on the emitter / base forming pattern and is used as an implantation mask for forming the base lead layer, the distance between the emitter layer and the base lead layer is self-aligned. And the area of the intrinsic base region is reduced, so that miniaturization and high speed can be promoted.

After the formation of the sidewalls, a polycrystalline silicon film is selectively grown, and this polycrystalline silicon film is
Since the base extraction layer is used as an upper layer, the thickness of the base extraction layer can be increased, and the resistance of the base extraction layer can be reduced.

Further, since the metal silicide layer is formed on the emitter electrode and the base extraction layer, the resistance of the emitter electrode and the base extraction layer can be reduced.

[0022]

[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. In addition, the point which overlaps with the conventional technology is
The description thereof will be omitted as appropriate. FIG. 1 shows the structure of a semiconductor device according to Embodiment 1 of the present invention,
FIG. 4 is a cross-sectional view illustrating an n-transistor.

In the figure, 1 to 3 and 6 are the same as those of the prior art, 25 is a silicon oxide film as an insulating region,
26 is a p-type SiGe base layer, and 27 is a p-type SiGe base layer.
A p-type Si base layer formed on the base layer 26; 28, an intrinsic base region composed of the p-type SiGe base layer 26 and the Si base layer 27; 29, a high-concentration SiGe base. P ⁺ -type SiGe base layers as layers, 30 and 31 are p ⁺ -type SiG
a p ⁺ -type Si base layer 32 as a high-concentration Si base layer formed on the upper and lower layers of the e-base layer 29, respectively;
The p ⁺ -type SiGe base - p ⁺ -type polycrystalline SiGe layer as heavily doped polycrystalline SiGe layer on the scan layer 29 is formed on the silicon oxide film 25 adjacent, 33 p ⁺ -type polycrystalline SiGe layer 32 on p ⁺ -type polycrystalline Si layer as a heavily doped polycrystalline Si layer formed, 34 is composed of base with p ⁺ -type region of 29 to 34 - is a scan lead layer. 35 is an n-type Si emitter layer as an emitter layer; 36 is an insulating silicon oxide film as an emitter-base insulating film; 37 is an n ⁺ -type polycrystalline Si emitter electrode; 38 is a passivation film; It is a metal wiring layer.

A method of manufacturing the BipTr thus configured will be described below with reference to FIGS. First, an n ⁺ type buried layer 2, an n type epitaxial layer 3,
An oxide film 25 and a collector lead layer 6 are formed (FIG. 2). The subsequent manufacturing method will be described with reference to only the portion A in FIG. Next, a p-type impurity of about 1
0 ¹⁸ ~10 ²⁰ cm ^-3 included the _{Si 1-x Gex (x =} 0.
1 to 0.3) The thin film 40 and the n-type impurity are about 10 ¹⁶ to 10 ¹⁸
The Si thin film 41 containing cm ⁻³ is continuously grown epitaxially. At this time, the portions where the underlayer is the silicon oxide film 25 become the polycrystalline Si _1-x Gex thin film 42 and the polycrystalline Si thin film 43, respectively. The silicon oxide film 44, the silicon nitride film 45 and the silicon oxide film 4
6 are sequentially deposited (FIG. 3).

Next, a photoresist film 4 is formed on the entire surface of the substrate 1.
7 is formed and patterned by photolithography. Using the resist pattern 47 as a mask, the underlying silicon oxide film 46, silicon nitride film 45, and silicon oxide film 44 are sequentially removed by anisotropic etching to form an emitter base forming pattern 48 of the three films. To form Thereafter, p-type B ions or BF ₂ ions are implanted from above the substrate 1 into the Si thin film 41 and the polycrystalline Si thin film 43 with an implantation amount of about 10 ¹⁴ cm ⁻² (FIG. 4). Next, after removing the photoresist film 47, the substrate 1
A silicon oxide film is deposited to a thickness of about 200 nm on the entire upper surface, and the entire surface of the silicon oxide film is anisotropically etched to form an emitter. A side wall 49 is formed on the side wall of the base forming pattern 48. Thereafter, a p-type B ions or BF ₂ ions from the substrate 1, 10 ¹⁵ to 1
The Si thin film 41 and the polycrystalline Si thin film 4 are implanted at a dose of 0 ¹⁶ cm ^-2.
3, and underlying Si _1-x Gex thin film 40, polycrystalline S
Ions are implanted into the i _1-x Gex thin film 42 (FIG. 5).

Next, the substrate 1 is heat-treated to activate the implanted p-type impurities, so that only the lower layer portion of the emitter-base forming pattern 48 of the Si thin film 41 is n-type.
The n-type Si emitter 35 remains as a mold and becomes a p-type Si base layer 27 under the sidewall 49, and a p-type base layer under the n-type Si emitter layer 35 and the p-type Si base layer 27. A base layer 26 is formed to form an intrinsic base region 28, and ap ⁺ type diffusion layer is formed outside these regions.
The p ⁺ -type diffusion layer comprises a p ⁺ -type Si base layer 31, a p ⁺ -type SiGe base layer 29 thereon, and a p ⁺ -type base layer 3 thereon.
0 and p ⁺ -type polycrystalline SiGe on silicon oxide film 25
It comprises a layer 32 and a p ⁺ -type polycrystalline Si layer 33 thereon. Thereafter, after removing the uppermost silicon oxide film 46 and the side wall 49 of the emitter-base forming pattern 48, a photoresist film 50 is formed on the entire surface of the substrate 1 and patterned by photolithography. I do. By using the resist pattern 50 as a mask, the underlying p ⁺ -type polycrystalline Si layer 33 and the p ⁺ -type polycrystalline SiGe layer 32 are removed by etching, whereby the p ⁺ -type diffusion layer is patterned.
To form a base extraction layer 34 (FIG. 6).

Next, after removing the photoresist film 50,
The surface of the substrate 1 is oxidized at 600 to 800 ° C.
A silicon oxide film 36 which is sufficiently thicker than the silicon oxide film 44 of the base forming pattern 48 is formed. This silicon oxide film 36 is not formed in the portion covered with the silicon nitride film 45, but is formed on the base including the p ⁺ -type polycrystalline SiGe layer 32.
It is formed on the side surface of the extraction layer 34 (FIG. 7). next,
The silicon nitride film 45 and the silicon oxide film 44 in the emitter base forming pattern 48 are sequentially etched and removed to form an opening 51 exposing the surface of the n-type Si emitter layer 35. A polycrystalline Si film doped with n ⁺ -type impurities is deposited on the entire surface of the substrate 1 so as to fill the opening 51. Thereafter, a photoresist film is formed on the entire surface of the n ⁺ -type polycrystalline Si film, patterned by photolithography, and the underlying n ⁺ -type polycrystalline Si film is removed by etching using the resist pattern 52 as a mask. Thus, an n ⁺ -type polycrystalline Si emitter electrode 37 is formed (FIG. 8).

Next, after removing the photoresist film 52,
A passivation film 38 is deposited on the entire surface of the substrate 1. Thereafter, contact holes are formed so as to be connected to the n ⁺ -type polycrystalline Si emitter electrode 37, the p ⁺ -type base extraction layer 34, and the n ⁺ -type collector extraction layer 6, respectively.
An electrode wiring layer 39 is formed (see FIG. 1).

[0029] BipTr configured in this way, the intrinsic base - for heterozygous BipTr used in source region 28 a narrow silicon germanium bandgap than silicon, without reducing the current amplification factor h _FE of BipTr The density of the intrinsic base region 28 can be increased,
High f _T can be realized. Also, a p-type SiGe base layer 26
Since the SiGe thin film 40 to be formed and the Si thin film 41 to be the n-type Si emitter layer 35 are continuously grown, the generation of the interface state between the emitter and the base can be prevented, and the leak current can be reduced. Also, an emitter-base forming pattern 48 is formed.
Side wall 49 is formed on the base extraction layer 3
4, the distance between the n-type Si emitter layer 35 and the base extraction layer 34 is finely determined by a self-alignment process that was impossible with the conventional heterojunction BipTr. Intrinsic base region 2
8 can also be reduced. For this reason, the area of the parasitic capacitance formed by the base 28 and the collector 3 is reduced, and miniaturization and high-speed operation can be promoted.

Embodiment 2 FIG. FIG. 9 is a sectional view showing the structure of a BipTr according to the second embodiment of the present invention. Example 1 above
The base extraction layer 34 is formed to be thick, and the upper part of the base extraction layer 34 is formed of a high-concentration polycrystalline S
A p ⁺ -type polycrystalline Si film 53 serving as an i-film is formed. The lower layer portion is a p ⁺ -type SiGe base layer 54 serving as a high-concentration SiGe base layer on the collector 3 and a high-concentration Si base layer thereon.
P ⁺ -type Si base layer 55 as a source layer, p ⁺ -type polycrystalline SiGe layer 56 as a high-concentration polycrystalline SiGe layer on silicon oxide film 25, and p ⁺ It is composed of a ⁺ type polycrystalline silicon layer 57. Other parts are the same as in the first embodiment.

Hereinafter, the manufacturing method will be described with reference to FIGS. First, in the same manner as in the first embodiment, an emitter-base forming pattern 48 is formed and steps up to ion implantation of a p-type impurity are performed (see FIGS. 2 to 4). Next, after a sidewall 49 is formed in the same manner as in the first embodiment, p ^{+ is formed} on the Si thin film 41 and the polycrystalline Si thin film 43 other than the emitter-base forming pattern 48 and the region of the sidewall 49.
The type polycrystalline Si film 53 is selectively grown. The p ⁺ -type polycrystalline Si film 53 is obtained by introducing a p-type impurity during the growth of the polycrystalline Si film or by implanting p-type impurity ions after the growth (FIG. 10).

Next, by subjecting the substrate 1 to a heat treatment,
P-type impurity in p ⁺ -type polycrystalline Si film 53 and Si thin film 41
The n-type Si emitter layer 35, the intrinsic base region 28, and the p ⁺ -type diffusion layer are formed by diffusing the p-type impurity already implanted in the polycrystalline Si thin film 43. Then Example 1
Similarly, silicon oxide film 46 and side wall 49
Then, the p ⁺ -type diffusion layer is patterned to form a base extraction layer 34 (FIG. 11). Next, a silicon oxide film 36 is formed in the same manner as in Example 1 (FIG. 12), and after removing the silicon nitride film 45 and the silicon oxide film 44 by etching, an n ⁺ -type polycrystalline Si emitter electrode 37 is formed (FIG. 13). ).

In the second embodiment, the p ⁺ -type polycrystalline Si film 5
By forming 3, the base lead-out layer 34 can be formed thicker than in the first embodiment. Therefore, the effect of lowering the resistance of the base extraction layer 34 is further obtained in addition to the effect of the first embodiment.

Embodiment 3 FIG. FIG. 14 is a sectional view showing the structure of a BipTr according to the third embodiment of the present invention. This corresponds to the n ⁺ -type polycrystalline Si emitter electrode 37 in the first embodiment.
And a TiSi ₂ layer 58 as a metal silicide layer formed on the base extraction layer 34. This Bi
The manufacturing method of pTr is the same as that of Example 1 except that n ⁺ -type polycrystalline S
After the formation of the i-emitter electrode 37 (see FIG. 8), the silicon oxide film 36 is etched using the resist pattern 52 for forming the emitter electrode 37 as a mask to form TiS.
The i ₂ layer 58 is selectively formed only on the silicon and polysilicon surfaces. In order to selectively form the TiSi ₂ layer 58, first, a Ti film is deposited on the entire surface of the substrate 1 and an annealing process is performed on the substrate 1 at a temperature of 600 to 700 ° C. TiSi only in certain areas
A layer is formed. Thereafter, the unreacted Ti film is removed and the substrate 1 is annealed again at about 800 ° C. to obtain n ⁺
A TiSi ₂ layer 58 is formed on type polycrystalline Si emitter electrode 37 and base extraction layer 34 (FIG. 15).

In the third embodiment, by forming the TiSi ₂ layer 58, the effect of the first embodiment can be further enhanced.
In addition, it has the effect of reducing the resistance of the base extraction layer 34.

[0036]

As described above, according to the present invention, a heterojunction BipT using silicon germanium as a base is provided.
For the production of r in the process using the self-aligned, base without reducing the current amplification factor h _FE - scan impurity concentration can increase the high f _T of that of the semiconductor device can be realized, the base - scan area reduction Miniaturization and high speed can be achieved, and the SiGe thin film serving as the base and the Si thin film serving as the emitter are continuously grown, thereby preventing the generation of the interface state between the base and the emitter. Reduces leakage current and improves reliability. Also, on the silicon area
Epitaxial growth, polycrystalline growth on insulating region
Thus, the second conductivity type silicon germanium and the first conductivity type
Of silicon is continuously grown to form a SiGe thin film
Polycrystalline SiGe thin films and Si thin films on them
Since a polycrystalline Si thin film is formed, the S
It is not necessary to etch only the i thin film,
It will be easier.

Further, since the base extraction layer is formed thicker by forming a high-concentration polycrystalline Si film on the upper part of the base extraction layer, the resistance of the base extraction layer is further reduced. Can be achieved.

Further, since the metal silicide layer is selectively formed on the emitter electrode and the base extraction layer,
Further, the resistance of the emitter electrode and the base extraction layer can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing one step of a method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to Embodiment 1 of the present invention.

FIG. 4 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing one step of a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention;

FIG. 6 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing one step of a method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a sectional view showing a structure of a semiconductor device according to Embodiment 2 of the present invention;

FIG. 10 is a sectional view showing one step of a method for manufacturing a semiconductor device according to Embodiment 2 of the present invention;

FIG. 11 is a sectional view showing one step of a method for manufacturing a semiconductor device according to Embodiment 2 of the present invention;

FIG. 12 is a sectional view showing one step of a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention;

FIG. 13 is a sectional view showing one step of a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention;

FIG. 14 is a sectional view showing a structure of a semiconductor device according to Embodiment 3 of the present invention;

FIG. 15 is a sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention;

FIG. 16 is a cross-sectional view showing the structure of a conventional homozygous BipTr.

FIG. 17 is a cross-sectional view showing a structure of a conventional hetero BipTr.

FIG. 18 is a cross-sectional view showing one step of a conventional method for manufacturing a heterojunction BipTr.

FIG. 19 is a cross-sectional view showing one step of a conventional method for manufacturing a heterojunction BipTr.

FIG. 20 is a cross-sectional view showing one step of a conventional method for manufacturing a heterojunction BipTr.

FIG. 21 is a cross-sectional view showing one step of a conventional method for manufacturing a heterojunction BipTr.

FIG. 22 is a cross-sectional view showing one step of a conventional method for manufacturing a heterojunction BipTr.

FIG. 23 is a cross-sectional view showing one step of a conventional method for manufacturing a heterojunction BipTr.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 3 silicon region serving as collector 25 silicon oxide film serving as insulating region 26 SiGe base layer 27 Si base layer 28 intrinsic base region 29 p + ^type SiGe serving as high-concentration SiGe base layer
Base layer 30, 31 p ⁺ -type Si base layer as high-concentration Si base layer 32 p ⁺ -type polycrystalline S as high-concentration polycrystalline SiGe layer
iGe layer 33 p ⁺ -type polycrystalline Si layer as high-concentration polycrystalline Si layer 34 base extraction layer 35 n-type Si emitter layer as emitter layer 36 silicon oxide film as emitter-base insulating film 37 emitter Electrode 40 SiGe thin film 41 Si thin film 42 Polycrystalline SiGe thin film 43 Polycrystalline Si thin film 44 Silicon oxide film 45 Silicon nitride film 46 Silicon oxide film 48 Emitter-base forming pattern 49 Side wall 53 High-concentration polycrystalline Si film P ⁺ -type polycrystalline Si film 54 as p ⁺ -type SiGe as high-concentration SiGe base layer
Base layer 55 p ⁺ -type Si base layer as high-concentration Si base layer 56 p ⁺ -type polycrystalline S as high-concentration polycrystalline SiGe layer
iGe layer 57 p ⁺ -type polycrystalline Si layer as high-concentration polycrystalline Si layer 58 TiSi ₂ layer as metal silicide layer

Claims (6)

(57) [Claims] 1. A semiconductor substrate having a silicon region serving as a collector of a first conductivity type and an insulating region, an intrinsic base region of a second conductivity type formed on the collector, and an outer region adjacent to the intrinsic base region. A base extraction layer formed of the same conductivity type as the intrinsic base region and having a higher concentration, an emitter layer of the first conductivity type formed on the intrinsic base region, and an emitter base. In a semiconductor device having an inter-insulating film and an emitter electrode connected to the emitter layer, the intrinsic base region is a lower portion of a silicon germanium (hereinafter referred to as SiGe) base layer and an upper portion of a silicon layer. And a base layer (hereinafter referred to as Si). The emitter layer is formed of a silicon film at the center of the SiGe base layer, and the Si base layer is formed of a silicon film. Formed, and Lead layer is formed over on the insulating region from on the collector, the collector on the portion of the base - scan lead layer is a high concentration Si
A base diffusion layer , a high-concentration SiGe base layer thereon and a high-concentration Si base layer thereon, and the base extraction layer above the insulating region is a high-concentration polycrystal. S
A semiconductor device comprising an iGe layer and a high-concentration polycrystalline Si layer thereon. 2. A silicon germanium of a second conductivity type on a semiconductor substrate having a silicon region of a first conductivity type and an insulating region so as to be epitaxially grown on the silicon region and polycrystalline on the insulating region. A first step of continuously growing silicon and first conductivity type silicon to form a SiGe thin film and a polycrystalline SiGe thin film, and a Si thin film and a polycrystalline Si thin film thereon, A second step of forming an emitter base forming pattern comprising a silicon oxide film, a silicon nitride film thereon, and a silicon oxide film thereon, in a region where an emitter layer is to be formed; and A third step of ion-implanting impurities of the second conductivity type into the Si thin film and the polycrystalline Si thin film other than the source forming pattern region, and then the emitter base forming pattern. A sidewall made of a silicon oxide film is formed on the side wall of the turn, and is formed in and below the Si thin film and the polycrystalline Si thin film other than the emitter base forming pattern and the region of the side wall. A fourth step of introducing a second conductivity type impurity into the SiGe thin film and the polycrystalline SiGe thin film by ion implantation, and then heat-treating the semiconductor substrate.
By activating the introduced impurities, an intrinsic base of the second conductivity type comprising the SiGe base layer and the Si base layer thereon is activated.
A second conductivity type comprising a high- concentration SiGe base layer, a high-concentration Si base layer above and below the high- concentration SiGe base layer, a high-concentration polycrystalline SiGe layer, and a high-concentration polycrystalline Si layer thereon. Forming a concentration diffusion layer, thereby forming silicon of the first conductivity type;
A fifth step of defining an emitter region consisting of a film , and then removing the silicon oxide film and the sidewall at the top of the emitter base formation pattern, and then removing the high-concentration polycrystalline Si layer and High-concentration polycrystalline SiGe
A sixth step of patterning the high-concentration diffusion layer to form a base extraction layer by selectively removing the layer; and then, forming the emitter-base pattern by the silicon nitride. Forming a silicon oxide film sufficiently thicker than the silicon oxide film under the silicon nitride film on a portion not covered by the film to expose surfaces and side surfaces of the Si base layer and the base extraction layer. Emitter covering part
2. The method according to claim 1, further comprising a seventh step of forming an inter-base insulating film, and thereafter removing said silicon nitride film and said silicon oxide film thereunder. 3. A semiconductor substrate having a silicon region serving as a collector of a first conductivity type and an insulating region, an intrinsic base region of a second conductivity type formed on the collector, and an outer region adjacent to the base region. A base extraction layer formed of the same conductivity type as the intrinsic base region and having a higher concentration, an emitter layer of the first conductivity type formed on the intrinsic base region, and an emitter base. In a semiconductor device having an inter-insulating film and an emitter electrode connected to the emitter layer, the intrinsic base region is composed of a lower SiGe base layer and an upper Si base layer. And the above Si
On the Ge base layer, an emitter layer made of a silicon film is formed at the center, and the Si base layer is formed on the emitter layer. The base extraction layer is formed on the collector from the insulating region. The upper layer is formed of a high-concentration polycrystalline Si film, and the lower layer is formed of a high-concentration SiGe base layer on the collector and a high-concentration S
High concentration polycrystalline SiG on i-base layer and insulating region
A semiconductor device comprising an e layer and a high-concentration polycrystalline Si layer thereon. 4. A silicon germanium of the second conductivity type on a semiconductor substrate having a silicon region of the first conductivity type and an insulating region so as to be epitaxially grown on the silicon region and polycrystalline on the insulating region. A first step of continuously growing silicon and first conductivity type silicon to form a SiGe thin film and a polycrystalline SiGe thin film, and a Si thin film and a polycrystalline Si thin film thereon, A second step of forming an emitter base forming pattern comprising a silicon oxide film, a silicon nitride film thereon, and a silicon oxide film thereon, in a region where an emitter layer is to be formed; and A third step of ion-implanting a second conductivity type impurity into the Si thin film and the polycrystalline Si thin film other than the source forming pattern region, and then forming an emitter base forming pattern. A sidewall made of a silicon oxide film is formed on the side wall of the second conductive type on the Si thin film and the polycrystalline Si thin film other than the emitter base forming pattern and the region of the side wall. A fourth step of selectively growing a high-concentration polycrystalline silicon film, and then heat-treating the semiconductor substrate to activate the introduced impurities, thereby forming an intrinsic base region of the second conductivity type and a second conductivity type. A high-concentration diffusion layer is formed , whereby the first conductivity type
A fifth step of defining the emitter region, and then removing the uppermost silicon oxide film and the sidewalls of the emitter base formation pattern, and patterning the high concentration diffusion layer to form a base. A sixth step of forming a base extraction layer, and then forming a portion of the emitter base forming pattern which is not covered with the silicon nitride film more sufficiently than the silicon oxide film below the silicon nitride film. Forming a thick silicon oxide film to cover exposed portions of the surface and side surfaces of the Si base layer and the base extraction layer;
4. The method of manufacturing a semiconductor device according to claim 3, further comprising a seventh step of forming an inter-base insulating film, and thereafter removing said silicon nitride film and said silicon oxide film thereunder. 5. The semiconductor device according to claim 1, wherein a metal silicide layer is formed on the emitter electrode and the base extraction layer. 6. After the emitter electrode is formed, the emitter-base insulating film other than the emitter electrode region is removed, and a metal silicide layer is selectively formed on the emitter electrode and the base extraction layer. 6. The method for manufacturing a semiconductor device according to claim 5, wherein