JP3207883B2 - Manufacturing method of bipolar semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline semiconductor thin film electrode and the like used for a transistor of a bipolar integrated circuit and a semiconductor region containing a high concentration of impurities formed in a single crystal semiconductor substrate. The present invention relates to a method for manufacturing a bipolar semiconductor device capable of improving electrical characteristics in connection of the semiconductor device.

[0002]

2. Description of the Related Art In the field of silicon semiconductor bipolar technology, it has become common to use polysilicon (polycrystalline silicon) as a fine wiring material or a diffusion source for a shallow junction. As a method for forming an emitter region having a fine planar dimension, electrode extraction using polysilicon has become an essential technology (polysilicon emitter technology).

[0003] As a typical method of forming an emitter region in the polysilicon emitter structure, there are the following three methods. (1) A method of forming an emitter region by diffusing impurities from polysilicon serving as an electrode. In this method, an impurity is diffused from the polysilicon by introducing an impurity into polysilicon serving as an electrode and then performing a heat treatment to form an emitter region.

For example, arsenic having a dose of 1 × 10 ¹⁶ / cm ² implanted into polysilicon having a thickness of about 300 nanometers is thermally diffused at 900 ° C. for 30 minutes.
A shallow emitter region with a junction depth of about 50 nanometers is formed. Using the same polysilicon, arsenic is heat-treated at 1000 ° C, which is a relatively high temperature, for 20 minutes, and diffused to form an emitter region with a junction depth of about 180 nanometers. An emitter region having excellent properties is formed. However, forming such a deep emitter requires high-temperature and long-time heat treatment.
High-temperature and long-time heat treatment usually affects the semiconductor region such as the base region formed in the preceding process, and is diffused too deeply, realizing a transistor structure suitable for high-speed operation. Not done. In other words, such a high-speed junction having a high junction depth (a junction depth of about
180 nanometers) In the process of heat treatment for forming the emitter region (at a temperature of 1000 ° C. for 20 minutes), the base region formed by ion implantation of boron or the like is also diffused. However, there is a problem that the junction depth becomes large, such as 400 to 500 nanometers or more. Further, the minimum size of the emitter diffusion window is 1
When the diameter becomes smaller than μm, the diffusion of the emitter impurities becomes difficult, and this problem becomes more serious.

[0005] For example, using the current commercially available ion implanter, the most stable and minimal variation in the implantation acceleration energy (for example, acceleration energy 25 KeV), p
When the base region of the mold is formed, the junction depth of the base region can be reduced to approximately 180 nm by heat treatment (at a temperature of 1000 ° C for 20 minutes) to form an emitter region of approximately 180 nanometers. 500 nanometers. Therefore, the base width is the difference in junction depth (about 500 nano-meters) junction depth of the emitter region (about 180 nano-meters) of the base region, preparative La Njisuta of about 320 nano-meters is formed Will be. A typical collector cutoff frequency (ft) of this 320 nanometer base transistor is about 5 GHz.
z, but the collector cutoff frequency (ft
= 10 GHz), it is necessary to form a base region having a small base width (about 100 to about 200 nanometers). Also, in this case, the junction depth of the emitter region to be formed by diffusion from polysilicon is about 300 nanometers. Long time heat treatment is required, and in fact, the depth of the base is undesirably considerably increased, so that a transistor having a small base width (about 100 to about 200 nanometers) cannot be realized. .

(2) A method of depositing polysilicon to be an electrode after forming an emitter region by ion implantation. The method of forming the emitter region, the impurities such as arsenic (As) in the p-type base region directly to a system for ion implantation, for example, a 1 × 10 ¹⁶ / cm ² of arsenic implantation acceleration energy 50keV After direct ion implantation, temperature
Perform heat treatment at 1000 ° C. Immediately after implantation, the depth of the emitter region is about 100 nanometers, and after 20 minutes of heat treatment, the depth of the emitter region is about 200 nanometers. (1)
Arsenic at 1000 ℃ by the method of forming the emitter region shown in
The depth of the emitter when diffused from polysilicon under the conditions of 20 minutes was about 180 nanometers, but the same conditions (1000 ° C for 20 minutes) Is performed, the depth of the emitter region is about 260 nanometers, and an emitter region having a junction depth of 80 nanometers deeper than the method of forming the emitter region shown in (1) is formed. In this case, the amount of arsenic, which is an impurity in the emitter region, is preferably increased by directly ion-implanting, so that the emitter resistance can be reduced. However, when impurities such as arsenic are directly ion-implanted into the p-type base, there is a problem that the surface is roughened. When the surface is roughened in this way, a thin silicon oxide film (hereinafter referred to as a "natural oxide film") naturally formed between the polysilicon and the single-crystal silicon when depositing polysilicon for extracting an electrode in a later step. There is a problem that the growth of the oxide becomes unstable and the thickness of the natural oxide film fluctuates, thereby increasing the variation in the series resistance of the emitter region.

(3) A method of forming an emitter region by ion-implanting an impurity through a non-single-crystal semiconductor thin film such as polysilicon. The method of forming this emitter region is such that an n-type impurity such as arsenic (As) is doped with P-type impurity through a thin film such as polysilicon.
In this case, ion implantation is performed into the base region of the mold. In this case, the method of forming the emitter region shown in (2), that is, arsenic is directly ion-implanted into silicon (acceleration energy 50
20 keV) compared to the method of performing
By setting V to about 70 keV, almost the same impurity distribution as that of the emitter region formed by the method of forming the emitter region shown in (2) can be obtained. In addition, the thin silicon oxide film that naturally exists between polysilicon and single-crystal silicon can be crushed to some extent by ion implantation of impurities. This can reduce the series resistance of the emitter region.

[0008]

As a first object of the present invention, there is an adverse effect due to a naturally formed thin silicon oxide film (hereinafter referred to as "natural oxide film") between polysilicon and single crystal silicon. . This natural oxide film grows to a thickness of about 2 nanometers or less when depositing a non-single-crystal thin film of polysilicon, amorphous silicon, etc., and is diffused into the emitter region by increasing the thickness. The depth of the impurity, that is, the depth of the junction becomes shallow or deep, and becomes unstable. In addition, when the thickness of the natural oxide film is increased, the series resistance of the emitter region is increased, and there is a problem that the transistor characteristics are deteriorated or vary. As the size of the emitter window becomes smaller, it becomes more difficult to remove the natural oxide film before depositing the non-single-crystal thin film, and accordingly, between the transistors in the same wafer or between the wafers in the same batch. Variations in electrical characteristics increase.

This problem is caused by forming the emitter region having a deep junction by ion implantation using the emitter formation method shown in the prior art (2), and then forming a non-single-crystal electrode of polysilicon, amorphous silicon, or the like on the emitter region. When pulling out of it, it adds even more difficulty. In other words, when polysilicon is deposited on a silicon surface containing a high concentration of surface impurities such as arsenic, natural polysilicon formed on the silicon surface is greater than when polysilicon is deposited on a silicon surface containing a low concentration of impurities. The oxide grows thicker, thus further worsening the ohmic contact between the emitter region and the deposited polysilicon, and rapidly increasing the series resistance of the emitter region.

A second object of the present invention is to form a relatively deep junction at a predetermined depth with a relatively low diffusion temperature and a short time. If a junction having a desired depth such as an emitter can be formed at a relatively low diffusion temperature and in a short time, a transistor having a narrow base width and excellent in high speed can be realized without changing the profile of impurities such as a base. For example, to form an emitter region having a junction depth of about 300 nanometers requires a long heat treatment at 1000 ° C. for about 60 minutes. The base region to be formed is also deeply diffused under the influence of the heat treatment in forming the emitter region. Therefore, there is a problem that a transistor structure suitable for high-speed operation cannot be realized.

In the conventional method of forming an emitter region shown in (3), when the impurity is ion-implanted into the p-type base region through the non-single-crystal semiconductor thin film such as polysilicon. The variation in the thickness of the non-single-crystal semiconductor thin film directly affects the junction depth of the emitter region,
Since the base width, which is the difference between the junction depth of the base region formed by ion implantation and the junction depth of the emitter formed in the preceding process, fluctuates, the electrical characteristics of the formed transistors vary. is there.

In view of the above problems, it is an object of the present invention to form an electrode by depositing a non-single-crystal semiconductor thin film such as polysilicon on the surface of an emitter region formed in a semiconductor substrate such as single-crystal silicon. By removing the adverse effect of the natural oxide film formed between the emitter region and the non-single-crystal semiconductor thin film, the emitter region and the base region having a desired junction depth can be formed by a short-time heat treatment at a relatively low diffusion temperature. It is an object of the present invention to provide a method for manufacturing a bipolar semiconductor device in which the transistor has stable electrical characteristics and can realize a transistor structure suitable for high-speed operation.

[0013]

[Means for Solving the Problems]

A method for manufacturing a bipolar semiconductor device according to the first aspect is as follows. A base extraction electrode thin film made of a second conductivity type semiconductor thin film is formed on a first conductivity type single crystal first semiconductor region serving as a collector. A first insulating film is formed on the base extraction electrode thin film.
At least one opening is formed in the first semiconductor region by selectively etching the base extraction electrode thin film and the first insulating film sequentially. An external base region made of a semiconductor region of the second conductivity type is formed in the first semiconductor region immediately below the base extraction electrode thin film. A second insulating film is formed on the side wall of the base extraction electrode thin film. A second conductivity type semiconductor region for connecting an external base region to the first semiconductor region by injecting a second conductivity type impurity into the opening obliquely into the opening using the second insulating film as a mask. Is formed. A non-single-crystal first semiconductor thin film is formed on the entire surface. This first
By implanting impurities of the first conductivity type through the semiconductor thin film, a second semiconductor region of the first conductivity type serving as an emitter is formed in the first semiconductor region. By implanting an impurity of the second conductivity type through the first semiconductor thin film, a third semiconductor region of the second conductivity type serving as a base is formed.
A second semiconductor thin film is formed on the first semiconductor thin film. The first semiconductor thin film and the second semiconductor thin film formed on the opening are patterned so as to serve as an emitter electrode, and the second semiconductor thin film contains a first conductivity type impurity.

A method of manufacturing a bipolar semiconductor device according to a second aspect is as follows. A base extraction electrode thin film made of a second conductivity type semiconductor thin film is formed on a first conductivity type single crystal first semiconductor region serving as a collector. A first insulating film is formed on the base extraction electrode thin film.
At least one opening is formed in the first semiconductor region by selectively etching the base extraction electrode thin film and the first insulating film sequentially. An external base region made of a semiconductor region of the second conductivity type is formed in the first semiconductor region immediately below the base extraction electrode thin film. A second insulating film is formed on the side wall of the base extraction electrode thin film, and a third insulating film is formed on the opening. By implanting an impurity of the second conductivity type through the third insulating film on the opening, the first
For connecting an external base region to a semiconductor region of
A link base region made of a conductive semiconductor region is formed. The fourth insulating film is left on the side wall of the base extraction electrode thin film. An amorphous first semiconductor thin film is formed on the entire surface. By implanting impurities of the first conductivity type through the first semiconductor thin film, a second semiconductor region of the first conductivity type serving as an emitter is formed in the first semiconductor region. By implanting an impurity of the second conductivity type through the first semiconductor thin film, a third semiconductor region of the second conductivity type serving as a base is formed. A second semiconductor thin film is formed on the first semiconductor thin film. The first semiconductor thin film and the second semiconductor thin film formed on the opening are patterned so as to serve as an emitter electrode, and the second semiconductor thin film contains a first conductivity type impurity.

A method for manufacturing a bipolar semiconductor device according to a third aspect is as follows. A first semiconductor thin film is formed on a first-conductivity single-crystal first semiconductor region serving as a collector. By implanting a first conductivity type impurity through the first semiconductor thin film, a first conductivity type second semiconductor region serving as an emitter is formed. By implanting impurities of the second conductivity type through the first semiconductor thin film, a third semiconductor region of the second conductivity type serving as a base is formed. A second semiconductor thin film is formed on the first semiconductor thin film. A semiconductor film pattern for an emitter electrode is formed by patterning the first semiconductor thin film and the second semiconductor thin film.
The second semiconductor region of the first conductivity type except for the portion where the semiconductor film pattern for the emitter electrode is formed is selectively removed, and the second semiconductor region serving as an emitter is provided immediately below the semiconductor film pattern for the emitter electrode. Is formed. A sidewall-shaped insulating film is left on the side surface of the remaining semiconductor region. By using the insulating film and the semiconductor film pattern for the emitter electrode as a mask, a second conductive type fourth semiconductor region serving as an external base is formed by injecting a second conductive type impurity into the third semiconductor layer region. Then, the fourth semiconductor region is connected to the third semiconductor region.

A method of manufacturing a bipolar semiconductor device according to a fourth aspect is as follows. A first semiconductor thin film is formed on a first-conductivity single-crystal first semiconductor region serving as a collector. By implanting an impurity of the first conductivity type through the first semiconductor thin film, a second semiconductor region of the first conductivity type serving as an emitter is formed. By implanting impurities of the second conductivity type through the first semiconductor thin film, a third semiconductor region of the second conductivity type serving as a base is formed. First
A second semiconductor thin film is formed on the semiconductor thin film. By patterning the first semiconductor thin film and the second semiconductor thin film, a semiconductor film pattern for extracting an emitter electrode is formed. The second semiconductor region of the first conductivity type except for the portion where the semiconductor film pattern for the emitter electrode is formed is selectively removed, and the second semiconductor region serving as an emitter is provided immediately below the semiconductor film pattern for the emitter electrode. Is formed. Using the semiconductor film pattern for the emitter electrode as a mask, an impurity of the second conductivity type is implanted into the second semiconductor region to form a fifth semiconductor region of the second conductivity type serving as a link base. The sidewall-shaped insulating film is left on the side surface of the remaining semiconductor region. By using the insulating film and the semiconductor film pattern for the emitter electrode as a mask, a second conductive type fourth semiconductor region serving as an external base is formed by injecting a second conductive type impurity into the first semiconductor region. Then, the fourth semiconductor region and the residual semiconductor region are connected via the fifth semiconductor region.

A method of manufacturing a bipolar semiconductor device according to a fifth aspect is as follows. A first semiconductor thin film is formed on a first-conductivity single-crystal first semiconductor region serving as a collector. By implanting a first conductivity type impurity through the first semiconductor thin film, a first conductivity type second semiconductor region serving as an emitter is formed. By implanting impurities of the second conductivity type through the first semiconductor thin film, a third semiconductor region of the second conductivity type serving as a base is formed. A second semiconductor thin film is formed on the first semiconductor thin film. A semiconductor film pattern for an emitter electrode is formed by patterning the first semiconductor thin film and the second semiconductor thin film.
The second semiconductor region of the first conductivity type except for the portion where the semiconductor film pattern for the emitter electrode is formed is selectively removed, and the second semiconductor serving as an emitter is provided immediately below the semiconductor film pattern for extracting the emitter electrode. Forming a residual semiconductor region of the region; The sidewall-shaped first insulating film is left on the side surface of the remaining semiconductor region. A second conductive type fifth semiconductor region serving as a link base by injecting a second conductive type impurity into the first semiconductor layer region using the first insulating film and the semiconductor pattern for the emitter electrode as a mask. Is formed, and the fifth semiconductor region is connected to the remaining semiconductor region. A sidewall-shaped second insulating film is left on the side surface of the first insulating film. By implanting impurities of the second conductivity type into the first semiconductor layer region using the semiconductor pattern for the emitter electrode and the first and second insulating films as a mask, the fourth of the second conductivity type serving as an external base is formed. A semiconductor region is formed, and the fourth semiconductor region is connected to the fifth semiconductor region.

According to a sixth aspect of the present invention, in the method of manufacturing a bipolar semiconductor device according to the third, fourth or fifth aspect, a metal-semiconductor alloy film is selectively formed on a surface of the fourth semiconductor region. It is characterized in that a forming step is added.

[0020]

According to the structure of the present invention, the following effects are obtained. (1) Impurities of the first conductivity type and the second conductivity type are ion-implanted through a thin first semiconductor thin film of polysilicon or the like, so as to eliminate the influence of a natural oxide film and to be relatively low. A second semiconductor region of a first conductivity type serving as an emitter having a shallower depth than a conventional one and a third semiconductor region of a second conductivity type serving as a base can be formed in a short time at a diffusion temperature;
Since the base width can be reduced, a bipolar transistor with high speed can be formed.

(2) First film having a small thickness such as polysilicon
By injecting impurities through the semiconductor thin film of
A natural oxide film formed between a first semiconductor thin film such as polysilicon and a first semiconductor region in a single crystal semiconductor substrate is
Since it can be broken to some extent, the ohmic contact between the second semiconductor thin film serving as the extraction electrode and the second semiconductor region of the first conductivity type serving as the emitter can be improved, whereby the series resistance of the emitter can be reduced.

(3) Impurities of the first conductivity type and the second conductivity type are ion-implanted through the same first semiconductor thin film such as polysilicon, and the second and third semiconductor regions serving as an emitter and a base are implanted. Is formed, it is possible to prevent variations in the base width due to variations in the thickness of the first semiconductor thin film. That is, when the first semiconductor thin film is deposited thinly, both the emitter and the base are formed deeply, and when the first semiconductor thin film is deposited thickly, the emitter and the base are also formed shallowly. Even if the thickness fluctuates, it hardly affects the variation in the base width (base depth-emitter depth).

(4) According to the structure of the first or second aspect , impurities of the first conductivity type and the second conductivity type are ion-implanted through the first semiconductor thin film to form the emitter region and the active base. Before forming the second semiconductor region of the first conductivity type and the third semiconductor region of the second conductivity type to be regions, the impurities of the second conductivity type are self-aligned immediately below the second insulating film through the opening. In this case, the active base region and the external base region can be reliably connected by forming the link base region.

(5) According to the third , fourth , fifth, or sixth aspect of the present invention, the second emitter serving as an emitter is provided.
The first semiconductor thin film at the time of ion implantation for forming the semiconductor region and the third semiconductor region serving as a base is flat without any steps, and the second semiconductor thin film is formed after forming the second semiconductor region and the third semiconductor region. Is patterned to form a residual semiconductor region which becomes a substantial emitter. Therefore, the junction depth at the peripheral portion of the residual semiconductor region serving as the emitter and the peripheral portion of the third semiconductor region serving as the base can be formed as in the central portion, and particularly, the electrical characteristics generated when the dimensional width of the emitter is reduced. Changes can be reduced.

(6) According to the structure of the fifth aspect , the sidewall is formed in two steps of the first insulating film and the second insulating film, and the first insulating film is masked at the first time. A fifth semiconductor region serving as a link base having an appropriate impurity concentration and profile is formed in a self-aligned manner by the ion implantation used in the first step. A fourth semiconductor region to be a region is formed in a self-aligned manner. Therefore, by adjusting the thicknesses of the sidewall-shaped first and second insulating films, the third semiconductor region serving as a base and the fourth base serving as an external base can be maintained while maintaining the reliability of the bipolar semiconductor device. The semiconductor regions can be reliably connected via the fifth semiconductor region serving as a link base.

(7) According to the constitution of claim 6, in the constitution of claim 3, 4 or 5 , a metal-semiconductor alloy film is formed on the surface of the fourth semiconductor region serving as an external base. In addition, the contact resistance to the electrode can be reduced. As a result, the area of the contact region can be reduced, and accordingly, high integration and reduction of the parasitic capacitance can be realized, which can contribute to an increase in the speed of the bipolar semiconductor device.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the following embodiments, the present invention will be described.
Discusses basic bipolar semiconductor device fabrication methods
I will tell. 1 to 6 are cross-sectional views in the order of steps showing main parts of an npn-type bipolar transistor to which a method of manufacturing a bipolar semiconductor device as a basis of the present invention is applied. FIG.
As shown in FIG. 3, n ^{+ is formed} on a p-type silicon semiconductor substrate 100.
Buried layer 102, ap ⁺ -type buried layer 105 serving as a channel stopper for electrically isolating elements from each other,
N having a desired film thickness of the semiconductor region ^- after the formation of the type of the epitaxial semiconductor layer 104, LP- on the surface
An Si ₃ N ₄ film (not shown) for use in a LOCOS method (local oxidation method) is deposited by a CVD method (a low-pressure CVD method). Thereafter, the Si ₃ N _{4 in the} element isolation oxide film formation region
By removing the film and oxidizing the surface, an element isolation oxide film 106 having a desired thickness is formed. After removing the Si ₃ N ₄ film in other regions, the epitaxial semiconductor layer 10 is removed.
4 After forming an injection protection oxide film 108 made of a thin silicon oxide film having a thickness of about 30 nanometers on the The collector wall diffusion layer 110 is formed by ion-implanting impurities and performing heat treatment diffusion. Then, after further forming a resist pattern 201, the resist pattern 201 is used as a mask and a low energy of about 15 keV and a dose of 1
By implanting boron of about 3 × 10 ¹² cm ⁻² , a p-type link base 112 for connecting an active base region to be formed later and a graft base region is formed.

Next, as shown in FIG. 2, the resist pattern 201 is removed, and a silicon oxide film 122 serving as an insulating film is entirely formed on the element isolation oxide film 106 and the injection protection oxide film 108 by LP-CVD. After the deposition, a resist pattern 202 is formed by an ordinary photomask process, and the injection protection oxide film 108 and the silicon oxide film 122 are etched to form an opening 300.

Next, as shown in FIG. 3, after the resist pattern 202 is removed, a silicon thin film (first semiconductor thin film) 124 of, eg, a polysilicon film having a thickness of about 30 nanometers is deposited. By implanting arsenic with a dose of 1 to 3 × 10 ¹⁵ cm ^{-2 at} an acceleration energy of 60 to 80 keV through the silicon thin film 124, an n-type emitter having a junction depth of about 180 nanometers is implanted. A region (second semiconductor region) 116 is formed. Then, continuously, through the silicon thin film 124, the dose amount is 1 to 3.
× 10 ¹³ cm ^-2 of boron is accelerated at an energy of 40-50k
The depth of the junction is about 400 by ion implantation at eV.
A nanometer p-type active base region (third semiconductor region) 114 is formed.

Next, as shown in FIG.
Then, a polysilicon thin film 126 having a thickness of about 300 nanometers to be a second semiconductor thin film is formed on the silicon thin film 126, and arsenic having a dose of 1 × 10 ¹⁶ cm ^-2 is accelerated in the polysilicon thin film 126 by an acceleration energy. After ion implantation at 40 keV, a resist pattern 203 is formed by a photomask process. Thereafter, using the resist pattern 203 as a mask, the polysilicon thin film is isotropically etched to form an emitter leading electrode.

Next, as shown in FIG. 5, after removing the resist pattern 203, a silicon oxide film for a side wall is deposited and anisotropically etched to form a side wall silicon oxide film 128. Next, as shown in FIG. 6, the external base region 11 is formed by ion implantation.
5 is formed, and a BPSG film 140 serving as a protective film is deposited on the entire surface, and then flattened by heat treatment. After the emitter, collector and base contact windows are formed in the BPSG film 140, the metal wiring 142 is formed.

The npn-type bipolar transistor formed as described above can increase the current amplification factor, obtain a good ohmic contact, and has a base width of about 200 nanometers, which is excellent in high-speed operation. Active base area
114 could be formed. For example, FIG. 36 shows an active region formed by directly implanting boron at an acceleration energy of 25 keV into a first semiconductor region serving as a collector before forming an emitter region in the method of forming an emitter region shown in the conventional example (3). In the method of forming the base region and the method of forming an emitter / base according to the present invention, the active base region is formed by ion-implanting boron at 40 keV through the silicon thin film 124 serving as the first semiconductor thin film after forming the emitter region. FIG. 4 is a diagram showing profiles of impurity concentrations of arsenic (As) and boron (B) with the formed one, from the surface of a polysilicon thin film 126 having a thickness of about 300 nanometers which becomes a second semiconductor thin film. In the figure, a is a bipolar semiconductor device on which the present invention is based.
Location and concentration of arsenic in the conventional example, b is the concentration of boron in the conventional example, c is indicative of the concentration of boron bipolar semiconductor device that is a basis of the present invention. Here, the conditions for forming the emitter region, the same ion implantation conditions in bipolar semiconductor device and a conventional example both underlying the present invention (As, dose 2 ×
10 ¹⁵ cm ^-2 and acceleration energy 70 keV), and the boron implantation dose is 4 × 10 ¹³ cm ^-2 . The heat treatment conditions are also the basis of the present invention.
Over La semiconductor device and a conventional example both the same (850 ° C., 3
0 minutes). As shown in FIG. 36, in both cases, the diffusion depth of the emitter region is about 180 nanometers, and the base width of the conventional example is about 320 nanometers. The junction depth of the emitter region is the same as that of the conventional example, but the base width is about 250 nanometers, indicating that the active base region 114 of the narrower base is formed.

Further, by further reducing the acceleration energy of arsenic and boron ion implantation, the junction depth between the emitter region 116 and the active base region 114 can be made smaller, and the base width can be further increased to about 100 nanometers. The structure can be realized. Further, arsenic and boron are implanted through a silicon thin film 124 serving as a first semiconductor thin film having a small film thickness such as polysilicon for an extraction electrode, so that the influence of the connection resistance of the natural oxide film is eliminated. Emitter region of desired depth with extremely low diffusion temperature and short time
116 can be formed. Furthermore, the conventional example (3)
Compared to the method of forming only the emitter region by ion implantation through a semiconductor thin film as shown in (1), the variation in the thickness of the semiconductor thin film causes variations in the base width which greatly affects the characteristics of the bipolar transistor. It is less likely to affect. That is, the basis of the present invention
In a bipolar semiconductor device , the emitter region 116 and the active base region 114 are formed by ion-implanting n-type and p-type impurities through the same silicon thin film 124. Even when the film thickness in the same batch and the same wafer in the thin film production varies, the silicon thin film 124
The thinly deposited portion can be formed deep in both the emitter region 116 and the base region 114, and the thickly deposited silicon thin film 124 corresponds to the emitter region 116 and the base region 114.
Since both are formed shallow, the base width, which is the difference between the depth of the active base region 114 and the depth of the emitter region 116, is not significantly affected by variations in the silicon thin film 124.

[0034] (First Embodiment) Next, a method for manufacturing a bipolar semiconductor device of the present invention n
First Embodiment A first embodiment applied to a pn-type bipolar transistor will be described with reference to FIGS. The first embodiment is a first example in which the method of manufacturing a bipolar semiconductor device according to the present invention is applied to a double polysilicon-self-aligned emitter technique. 7 to 13 are cross-sectional views in the order of steps showing main parts of an npn-type bipolar transistor to which the method for manufacturing a bipolar semiconductor device according to the first embodiment of the present invention is applied.

As shown in FIG. 7, the present invention is based on
Similarly to the bipolar semiconductor device , an n ⁺ -type buried layer 102 on a p-type silicon semiconductor substrate 100, a p ⁺ -type buried layer 105 serving as a channel stopper for electrically isolating elements from each other, and a first semiconductor region. After an n ⁻ -type epitaxial semiconductor layer 104 having a desired thickness is formed, an element isolation oxide film 106 having a desired thickness is formed on the surface thereof by using a LOCOS method (local oxidation method). Then, on the epitaxial semiconductor layer 104, a thin silicon oxide film 108 having a thickness of about 30 nanometers serving as an injection protection oxide film is formed, and a collector wall diffusion layer 110 is formed.

Here, the bipolar which is the basis of the present invention
Unlike a semiconductor device , after forming a resist pattern 204, the implantation protection oxide film 108 on the surface of the base / emitter formation region X is removed by selectively etching using the resist pattern 204. Next, as shown in FIG. 8, after removing the resist pattern 204, a polysilicon thin film 123 serving as a base lead electrode thin film is formed on the surface, and a dose amount of 1 to 3 is formed in the polysilicon thin film 123.
× 10 ¹⁵ cm ^-2 of boron with acceleration energy of 40-50k
Ion implantation is performed at eV. Then, on the surface of the polysilicon thin film 123, an inter-silicon silicon oxide film 127 serving as a first insulating film is formed. Thereafter, a resist pattern 205 for forming a base electrode is formed on the surface of the inter-polysilicon oxide film 127 by a photomask process. In addition,
The inter-polysilicon oxide film 127 is an interlayer insulating film between the polysilicon thin film 123 and a polysilicon thin film which will be formed later as a thin film for an emitter lead-out electrode.

Next, as shown in FIG. 9, using the resist pattern 205 as a mask, the silicon oxide film 12 between polysilicon is formed.
An opening (not shown) is formed on the epitaxial semiconductor layer 104 by selectively and sequentially etching the silicon thin film 123 and the polysilicon thin film 123. After that, resist pattern 20
5 is removed, and a silicon oxide film is deposited on the entire surface. Then, by patterning the silicon oxide film by anisotropic etching, the silicon oxide film between polysilicon is formed.
By leaving the silicon oxide film on the side walls of the polysilicon film 127 and the polysilicon thin film 123, a side wall silicon oxide film 129 to be a second insulating film is formed. At this time,
Due to the side wall silicon oxide film 129 left on the side wall of the polysilicon thin film 123, the opening 500 of the base / emitter formation region X becomes narrower than the opening formed by the resist pattern 205, and the size of the emitter is self-aligned. Smaller. In the step shown in FIG. 8, the boron implanted into the polysilicon thin film 123 diffuses into the inter-polysilicon oxide film 127 and the sidewall silicon oxide film 129, and gradually by a heat treatment or the like in a later step. Finally, an external base region 115 is formed by diffusing from the polysilicon thin film 123.

Next, as shown in FIG. 10, a resist pattern 206 is formed by a photomask process, and a dose of 1 to 3 × 10 ¹² cm ⁻ by ion implantation from an oblique direction of about 25 degrees at an acceleration energy 15keV ^two boron, epitaxial semiconductor layer
104, a link base area 113 serving as an internal base area.
To form The link base region 113 connects the external base region 115 within the opening, that is, connects the external base region 115 to an active base region to be formed later.

Next, as shown in FIG. 11, groups of the present invention
The resist pattern 206 is removed in the same manner as the basic bipolar semiconductor device, and a silicon thin film (first semiconductor thin film) 124 having a thickness of about 30 nanometers made of polysilicon to be the first semiconductor thin film is formed on the surface. After the deposition, the dose amount is 1 to 3 × 10 ¹⁵ cm through the silicon thin film 124.
An n-type emitter region (second semiconductor region) 116 having a junction depth of about 180 nanometers is formed by ion implantation of ^-2 arsenic at an acceleration energy of 60 to 80 keV. Furthermore, boron having a dose of 1 to 3 × 10 ¹³ cm ⁻² is supplied through the silicon thin film 124 at an acceleration energy of 4 × 10 ¹³ cm ^−2.
By ion implantation at 0 to 50 keV, a depth of about 40
A p-type active base region (third semiconductor region) 114 of nanometer is formed.

Next, as shown in FIG. 12, groups of the present invention
A polysilicon thin film 126 having a thickness of about 300 nanometers serving as a second semiconductor thin film is deposited on the silicon thin film 124 in the same manner as the bipolar semiconductor device serving as the foundation. , Dose amount 1 × 10 ¹⁶ cm
^-2 arsenic is ion-implanted at an acceleration energy of 40 keV. Thereafter, the silicon thin film 124 and the polysilicon thin film 126 are etched using the resist pattern 207 to form an emitter leading electrode.

[0041] Then, as shown in FIG. 13, of the present invention
As in the case of the basic bipolar semiconductor device , a BPSG film 140 serving as a protective film is deposited on the entire surface and flattened by a heat treatment. A metal wiring pattern 142 is formed. Thus, the silicon thin film 124
By applying the method of forming the emitter region 116 and the base region 114 by ion implantation of arsenic and boron through the double polysilicon-self-aligned emitter technology, a very high speed bipolar transistor can be realized. it can. Also, the active base area
When forming a link base region for connecting the 114 and the external base region 115, the link base region 117 can be formed immediately below the sidewall silicon oxide film 129 by injecting boron obliquely.

Second Embodiment Next, a method of manufacturing a bipolar semiconductor device according to the present invention will be described with reference to FIGS.
A second embodiment applied to a pn-type bipolar transistor will be described with reference to FIGS. In the second embodiment, the bipolar semiconductor device manufacturing method of the present invention is applied to a double polysilicon-self-aligned emitter technology.
This is the second example. 14 to 20 show np to which a method of manufacturing a bipolar semiconductor device according to a second embodiment of the present invention is applied.
FIG. 4 is a cross-sectional view illustrating a main part of an n-type bipolar transistor in process order.

As shown in FIG. 14, the present invention
Similarly to a bipolar semiconductor device , an n ⁺ -type buried layer 102, a p ⁺ -type buried layer 105 as a channel stopper for electrically isolating elements from each other, and a first n having a desired film thickness to be the semiconductor region ^- after the formation of the type of the epitaxial semiconductor layer 104, an element isolation oxide film 106 having a desired thickness by using the LOCOS method (local oxidation method) on the surface. Then, on the epitaxial semiconductor layer 104, a film thickness of about 30 nm
Injection protection oxide film 10 consisting of thin silicon oxide film for meter
8 and a collector wall diffusion layer 110 is formed.
Then, a desired resist pattern (not shown) is formed, and using this resist pattern as a mask, the injection protective oxide film 108 on the surface of the base / emitter formation region X is removed by etching. Then, after depositing a polysilicon thin film 123 serving as a base extraction electrode thin film on the surface,
A dose amount of 1 to 3 × 10 ¹⁵
C.- ² ions of boron are implanted at an acceleration energy of 40 to 50 keV. Then, on the surface of the polysilicon thin film 123,
Inter-polysilicon oxide film 127 serving as a first insulating film
Is deposited. Thereafter, a resist pattern 208 for forming a base electrode is formed by a photomask process, and an opening 400 is formed by selectively etching the interpolysilicon oxide film 127 and the polysilicon thin film 123 sequentially. The inter-polysilicon oxide film 127 is an interlayer insulating film between the polysilicon thin film 123 and a polysilicon thin film for an emitter lead-out electrode to be formed later.

Next, as shown in FIG. 15, after removing the resist pattern 208, the surface of the opening 400, that is, the surface of the epitaxial semiconductor layer 104 is thermally oxidized.
An injection protection oxide film 131 serving as a third insulating film is formed, and a sidewall thermal oxide film 130 serving as a second insulating film is formed on the side wall of the polysilicon thin film 123. Further, in the step shown in FIG. 14 by thermal oxidation, boron implanted into the polysilicon thin film 123 is diffused to form an external base region 115.

Next, as shown in FIG. 16, after a desired resist pattern 209 is formed, the resist pattern 209 is used as a mask to accelerate through the injection protection oxide film 131 in the base / emitter formation region X. Energy about 15k
A p-type link base region 117 is formed by ion-implanting boron with a low energy of eV and a dose of 1 to 3 × 10 ¹² cm ⁻² . This link base area 117 is
This is for connecting an active base region to be formed later and the external base region 115.

Next, as shown in FIG. 17, a silicon oxide film is deposited on the entire surface, and the silicon oxide film is patterned by anisotropic etching to form a silicon oxide film 127 between polysilicon and a sidewall / thermal oxide film. By removing so as to remain on the side wall of the polysilicon thin film 130,
Side wall silicon oxide film 12 serving as fourth insulating film
Form 9 '. At this time, due to the formation of the sidewall silicon oxide film 129 ', the opening 500 of the emitter region becomes narrower than the size of the opening 400 formed by the resist pattern 208 shown in FIG. . In the step shown in FIG. 14, boron implanted into the polysilicon thin film 123 diffuses into the inter-polysilicon silicon oxide film 127 and the sidewall silicon oxide film 129 ′, and is further subjected to a heat treatment in a later step. By gradually diffusing from the polysilicon thin film 123,
Finally, an external base region 115 as shown in FIG. 17 is obtained.

Next, as shown in FIG. 18, groups of the present invention
In the same manner as the bipolar semiconductor device serving as the foundation , for example, a silicon thin film (first semiconductor thin film) having a thickness of about 30 nanometers
The arsenic having a dose of 1 to 3 × 10 ¹⁵ cm ⁻² is accelerated through the silicon thin film 124 at an acceleration energy of 60 cm ^2.
By ion implantation at ~ 80 keV, an n-type emitter region (second semiconductor region) 116 having a junction depth of about 180 nanometers is formed. And more continuously,
Dose 1 to 3 × 10 ¹³ c via the silicon thin film 124
By implanting boron of m ^{−2 at} an acceleration energy of 40 to 50 keV, a p-type active base region (third semiconductor region) 114 having a junction depth of about 400 nanometers is formed.

Next, as shown in FIG. 19, groups of the present invention
A polysilicon thin film 126 having a thickness of about 300 nanometers as a second semiconductor thin film is deposited on the silicon thin film 124 in the same manner as the bipolar semiconductor device serving as a foundation. Arsenic of × 10 ¹⁶ cm ⁻² is ion-implanted at an acceleration energy of 40 keV. Thereafter, the silicon thin film 124 and the polysilicon thin film 126 are etched using the resist pattern 211 to form an emitter leading electrode.

[0049] Then, as shown in FIG. 20, of the present invention
As in the case of the basic bipolar semiconductor device , a BPSG film 140 serving as a protective film was deposited on the entire surface, planarized by heat treatment, and contact windows for the emitter, collector and base were formed in the BPSG film 140. Thereafter, a metal wiring pattern 142 is formed. Thus, the silicon thin film
Applying the method of forming emitter region 116 and active base region 114 by implanting arsenic and boron through 124 to a double polysilicon-self-aligned emitter technique achieves a very fast bipolar transistor. be able to. Here, when forming the link base region 117 for connecting the active base region 114 and the external base region 115, before forming the sidewall silicon oxide film 129 ′, the epitaxial semiconductor layer 104 serving as the first semiconductor region is formed in advance. An injection protection oxide film 131 is formed on the surface of the
Ion implantation of boron through the silicon layer 129, the surface of the epitaxial semiconductor layer 104 is not roughened, and the link base region 1 is formed immediately below the sidewall silicon oxide film 129 '.
17 can be formed.

For example, FIG. 37 shows a lamp annealing (RAT; Rapid Thermal Anneal) as in the second embodiment.
Npn having an emitter size (S _e ) of 0.3 μm × 1.6 μm formed by heat treatment at a temperature of 850 ° C.
Shows the Gummel characteristics of the transistor, and FIG. 38 is the collector current I of the current amplification factor h _FE of the npn transistor
9 shows a change with respect to c. FIG. 37 and FIG.
As shown in FIG. 8, the emitter size is 0.3 μm × 1.6.
Despite its extremely small size of μm, no leakage current in the low current region is observed, and the current amplification factor h _FE maintains a high value of 200 to 300 over a wide range of the collector current.

Further, Table 1 summarizes various parameters of the npn transistor formed as in the conventional example (3) and the npn transistor formed as in the second embodiment of the present invention. It is.

[0052]

[Table 1]

In Table 1, Se is the emitter size, h _FE is the current amplification factor, BV _ceo is the withstand voltage between the collector and the emitter, BV _ebo is the withstand voltage between the emitter and the base,
C _eb indicates the capacitance between the emitter and the base, C _cb indicates the capacitance between the collector and the base, and f _Tmax indicates the maximum collector cutoff frequency. As shown in Table 1, although the heat treatment temperature (850 ° C.) is the same, the base of the npn transistor to which the manufacturing method of the second embodiment of the present invention is applied is compared with the conventional example (3). The width can be made narrow, and the capacity can be reduced. As a result, the maximum collector cutoff frequency f _Tmax can be improved to 20 GHz, and a high-speed device can be realized. Further, as can be seen from the impurity profile shown in FIG. 36, the boron concentration in the active base region can be maintained at a high value even though the base width is narrow, so that the current amplification factor h _{FE is} almost constant. At the same time, the pressure resistance has not dropped.

Further, in the npn transistor according to the conventional method (3) in which only the emitter region is formed by ion implantation through a semiconductor thin film, when the emitter window area is reduced from 4 μm ² to 2 μm ² , the current is amplified. The in-plane variation of the rate h _{FE in} the wafer surface is a factor of about 1.5 times, which is a factor of reducing the yield of LSI. However, the emitter region 11 shown in the second embodiment of the present invention is not limited.
6 and the active base region 114 are formed by ion implantation through a semiconductor thin film, the npn transistor has, for example, an emitter window area of 1.2.
Even when the current amplification factor h _FE is reduced from 0.6 μm ² to 0.6 μm ² , the in-wafer variation of the current amplification factor h _FE hardly decreases, and the LSI
Not lower the yield.

FIG. 39 shows an npn transistor formed as in the second embodiment, an npn transistor formed as in conventional example (1), and a conventional example (3).
FIG. 11 is a diagram showing the dependence of the emitter resistance on the emitter window area in the npn transistor formed as described above. In the figure, the symbol ■ represents np according to the second embodiment.
Symbol n indicates an npn transistor according to the conventional example (1), and symbol □ indicates an npn transistor according to the conventional example (3).

As shown in FIG. 39, the npn transistors according to the conventional examples (1) and (3) have an emitter window area of 2
When the diameter is reduced to about μm ^2, the emitter resistance is increased due to the influence of the natural oxide film, and transistor characteristics cannot be obtained. However, the npn transistor according to the second embodiment has the emitter region 116 and the active base region. 1
Even if the 14 emitter windows are reduced to about 0.6 μm ² , they can be formed without being affected by the natural oxide film.

Although the silicon thin film 124 made of polysilicon is used as the first semiconductor thin film, an amorphous semiconductor such as amorphous silicon may be used. The use of amorphous silicon has the advantage that when implanting arsenic or the like for forming the emitter, so-called channeling can be prevented and an emitter having a uniform depth can be formed. In addition, the order of ion implantation of arsenic and boron can be either of them.However, if arsenic is implanted first, the implanted region becomes amorphous, and boron is implanted later. When implanting, channeling is less likely to occur, and the base region can be formed uniformly.

FIG. 40 shows a method of manufacturing a bipolar semiconductor device according to a second embodiment of the present invention.
s) and the impurity concentration profile of arsenic (As) and boron (B) in the npn transistor when the implantation order of boron (B) is changed. Silicon thin film 12
FIG. 6 is a diagram showing the surface of FIG. In FIG. 40, d is the arsenic concentration, and e is boron (B) ion-implanted to form the active base region 114 and then arsenic (A).
s) is ion-implanted to form boron (B) when the emitter region 116 is formed, and f is arsenic (As) ion-implanted to form the emitter region 116 and then boron (B) is ion-implanted. The active base region 11
4 shows the concentration of boron (B) when No. 4 was formed. Here, ion implantation conditions for the emitter region 116 and the active base region 114 (As, dose 2 × 10 ¹⁵ cm ⁻² , acceleration energy 70 keV) (B, dose 4 × 10 ¹³ c)
m ⁻² , acceleration energy 40 keV) and heat treatment conditions are the same (850 ° C., 30 minutes). If arsenic is implanted first as shown by the symbol f in FIG. 40, the implanted region becomes amorphous, and channeling is less likely to occur when boron is implanted later. A base region 114 could be formed.

Third Embodiment Next, a method of manufacturing a bipolar semiconductor device according to the present invention will be described with reference to FIG.
A third embodiment applied to a pn-type bipolar transistor will be described with reference to FIGS. 21 to 26
FIG. 10 is a sectional view in the order of steps showing a main part of an npn-type bipolar transistor to which the method for manufacturing a bipolar semiconductor device according to the third embodiment of the present invention is applied.

As shown in FIG. 21, the specific resistance is 1 to 10 [Ω].
.Cm] on a p-type silicon semiconductor substrate 100, an n ⁺ -type buried layer 102, a p ⁺ -type buried layer (not shown) as a channel stopper for electrically isolating elements from each other, and a first semiconductor. N ^{− of} about 1.3 μm in thickness
After forming the epitaxial semiconductor layer 104 of the mold type, the surface thereof is applied with a thickness of about 500 by LOCOS (local oxidation).
A nanometer isolation oxide film 106 is formed. Then, on the epitaxial semiconductor layer 104, a film thickness of about 30 nm
Injection protection oxide film 10 consisting of thin silicon oxide film for meter
Then, a desired resist pattern (not shown) is formed, and a collector wall diffusion layer 110 is formed using the resist pattern as a mask. Then, the injection protection oxide film 108 is removed by etching.

Next, as shown in FIG.
30 nm silicon thin film (first semiconductor thin film) 124
Is deposited to form a desired resist pattern 210.
By using this resist pattern as a mask, arsenic with a dose of 1 to 3 × 10 ¹⁵ cm ⁻² is ion-implanted at an acceleration energy of 60 to 80 keV through the silicon thin film 124 so that the junction depth is about 180 nm. Forming an n-type emitter region (second semiconductor region) 116 of the meter;
Further continuously, boron having a dose of 1 to 3 × 10 ¹³ cm ⁻² is accelerated through the silicon thin film 124 at an acceleration energy of 40 to
By implanting ions at 50 keV, a p-type active base region having a depth of about 400 nanometers (third semiconductor region)
Form 114.

Next, as shown in FIG.
On top of 124, a film thickness of about 300 nano-
After depositing the polysilicon thin film 126 of the meter, arsenic of 1 × 10 ¹⁶ cm ⁻² is ion-implanted into the polysilicon thin film 126 at an acceleration energy of 40 keV. Thereafter, a resist pattern 211 is formed, and the silicon thin film 124 and the polysilicon thin film 124 are formed using the resist pattern as a mask.
By etching 126, a semiconductor film pattern 800 for an emitter electrode is formed. Here, it is not essential to form the polysilicon thin film 126 serving as the second semiconductor thin film, but by forming the polysilicon thin film 126, the semiconductor film pattern 800 for the emitter electrode can be formed.
Is increased, and arsenic is further implanted into the polysilicon thin film 126, so that hole carriers moving from the emitter region 116 serving as the second semiconductor region to the silicon thin film 124 and the polysilicon thin film 126 have a high concentration. The barrier effect of recombination at the crystal grain boundaries of the arsenic-containing polysilicon thin film 126 is enhanced, whereby the base current can be reduced and the current amplification factor can be increased.

Next, as shown in FIG. 24, using the resist pattern 211 as a continuous mask, an n-type emitter region (second region) having a junction depth of about 180 nanometers at a portion which will later become an external base region is used. Is removed, and a residual semiconductor region 116A serving as an emitter region is left only under the polysilicon electrode. Next, as shown in FIG.
Insulating film that deposits a silicon oxide film with a thickness of, for example, 150 nanometers and becomes a sidewall by anisotropic etching.
Form 128C. Further, a resist pattern 212 is formed, and using the insulating film 128C and the resist pattern 212 as a mask, a p-type external base region 1 serving as a fourth semiconductor region is formed.
15a is formed by boron ion implantation at a dose of 10 ¹⁵ to 10 ¹⁶ cm ⁻² .

Then, as shown in FIG. 26, a BPSG film 140 serving as a protective film is deposited on the entire surface, and is flattened by heat treatment.
After forming each contact window of the base, a metal wiring pattern 142 is formed. Fourth Embodiment Next, a method for manufacturing a bipolar semiconductor device according to the present invention will be described with reference to n.
A fourth embodiment applied to a pn-type bipolar transistor will be described with reference to FIGS. 21 to 24 and FIGS. 27 to 29. 27 to 29 are cross-sectional views in the order of steps showing main parts of an npn-type bipolar transistor to which the method for manufacturing a bipolar semiconductor device according to the fourth embodiment of the present invention is applied.

[0065] First, the first, second, third and fourth steps similar to the steps of the third embodiment described with reference to FIGS. 21 to 24. As a result, an emitter electrode semiconductor film pattern 800 composed of the silicon thin film 124 and the polysilicon thin film 126 is formed on the remaining semiconductor region 116A serving as the emitter region. Is removed, that is, by removing the emitter region 116 at a portion which will be an external base region in a later step, the polysilicon thin film 126 is removed.
A residual semiconductor region 116A serving as an emitter region is formed directly under the semiconductor device.

[0066] Thereafter, as shown in FIG. 27, the resist pattern 212 as a mask, a dose of 10 ¹² to 10 a p-type link base region 113a serving as the fifth semiconductor region such that the impurity concentration less than the external base ¹⁴ cm ^-2
Formed by boron ion implantation. At this time, n
Boron, which is a p-type impurity, is also introduced into the collector wall diffusion layer 110, which is a semiconductor region of the p-type. However, since the concentration of the n-type impurity introduced into the collector wall diffusion layer 110 is 100 times or more, Collector wall diffusion layer 110
Has little effect on the characteristics of

Next, as shown in FIG. 28, a silicon oxide film is deposited to a thickness of, for example, 150 nanometers, and an insulating film 128C serving as a side wall is formed by anisotropic etching. Further, a resist pattern 212 is formed, and the insulating film is formed.
Using the 128C and the resist pattern 212 as a mask, the fourth
Is formed by boron ion implantation at a dose of 10 ¹⁵ to 10 ¹⁶ cm ⁻² . Then, as shown in FIG. 29, the originating
A BPSG film 140 serving as a protective film is deposited on the entire surface and flattened by a heat treatment, similarly to the bipolar semiconductor device on which the light source is based .
After forming each contact window of the base, a metal wiring pattern 142 is formed.

As described above, the link base region 113a having an appropriate impurity concentration and profile is formed before the sidewall is formed, and the external base region is formed after the sidewall is formed.
Since the emitter region 115a is formed in a self-aligned manner by ion implantation, the emitter region 116A and the link base region 113 are appropriately separated from each other so that high-concentration impurities do not come into contact with each other, thereby improving reliability. Also, the active base region 114 and the external base region 115 can be reliably connected via the link base region 113.

( Fifth Embodiment) Next, a method of manufacturing a bipolar semiconductor device according to the present invention will be described with reference to FIGS.
A fifth embodiment applied to a pn-type bipolar transistor will be described with reference to FIGS. 21 to 24 and FIGS. 30 to 32 are cross-sectional views in the order of steps showing main parts of an npn-type bipolar transistor to which the method of manufacturing a bipolar semiconductor device according to the fifth embodiment of the present invention is applied.

First, the same steps as the first, second, third and fourth steps of the third and fourth embodiments described with reference to FIGS. 21 to 24 are performed. As a result, an emitter electrode semiconductor film pattern 800 composed of the silicon thin film 124 and the polysilicon thin film 126 is formed on the remaining semiconductor region 116A serving as the emitter region. Is removed, that is, by removing the emitter region 116 in a portion that will become an external base region in a later step, a residual semiconductor region that becomes an emitter region immediately below the polysilicon thin film 126 is removed.
Form 116A.

[0071] Thereafter, as shown in FIG. 3 0, a silicon oxide film is deposited at a film thickness of, for example 100 nanometers, a semiconductor film for side and the emitter electrode of the residual semiconductor region 116A as the emitter region by anisotropic etching A first insulating film 128A serving as a sidewall is formed on a side surface of the pattern 116A. Then, a resist pattern 212 is further formed, and using the resist pattern 212 and the first insulating film 128A as a mask, a p-type link base which becomes a fifth semiconductor region having a lower impurity concentration than an external base region formed in a later step. The region 113a is formed by boron ion implantation at a dose of 10 ¹² to 10 ¹⁴ cm ⁻² . By forming the ring base region 113a by ion implantation using the first insulating film 128A as a mask in this manner, it is possible to suppress the ring base region 113a from entering the residual semiconductor region 116A which is to be an emitter region. Thus, the contact area between the ring base region 113a, which is a high-concentration region, and the residual semiconductor region 116A can be reduced, reduction in breakdown voltage and generation of hot carriers can be realized, and reliability can be improved.

Next, as shown in FIG. 31, a silicon oxide film is deposited to a thickness of, for example, 50 nanometers, and a sidewall-shaped second insulating film is formed on the side surface of the first insulating film 128A by anisotropic etching. A film 128B is formed. Further, a resist pattern 213 is formed, and using this resist pattern 213 and the first and second insulating films 128A and 128B as a mask, a p-type external base region 115a to be a fourth semiconductor region is dosed by 1
It is formed by ion implantation of boron of 0 ¹⁵ to 10 ¹⁶ cm ^-2 . Here, the second insulating film 128B is replaced with the first insulating film 128A.
In this case, the boron ion-implanted region is separated from the residual semiconductor region 116A serving as the emitter region, and the ring base region 113a is prevented from disappearing when the external base region 115a is formed.

Then, as shown in FIG. 32, a BPSG film 140 serving as a protective film is deposited on the entire surface and planarized by heat treatment, and contact windows for an emitter, a collector and a base are formed on the BPSG film 140. After that, a metal wiring pattern 142 is formed. In this manner, the first and second sidewall insulating films 128A and 128B are formed in two steps, and the first step is to perform ion implantation using the first insulating film 128A as a mask to obtain an appropriate impurity concentration. And a link base region 113a having a profile and
At the third time, the external base region 115a is formed in a self-aligned manner by ion implantation using the second insulating film 128B. Therefore, by adjusting the thicknesses of the first and second insulating films 128A and 128B, the residual semiconductor region 116A serving as an emitter region and the link base region 113a are appropriately separated from each other so that high-concentration impurities do not come into contact. And the reliability is improved. Also, the active base region 114 and the external base region 115a can be reliably connected via the link base region 113a.

( Sixth Embodiment) Next, a method of manufacturing a bipolar semiconductor device according to the present invention will be described with reference to FIGS.
A sixth embodiment applied to a pn-type bipolar transistor will be described with reference to FIGS. 21 to 24 and FIGS. 33 to 35 are cross-sectional views in the order of steps showing main parts of an npn-type bipolar transistor to which the method of manufacturing a bipolar semiconductor device according to the sixth embodiment of the present invention is applied.

First, the first, second, and third embodiments of the third , fourth, and fifth embodiments described with reference to FIGS.
Then, the same step as the fourth step is performed. As a result, a silicon thin film is formed on the residual semiconductor region 116A serving as the emitter region.
A semiconductor film pattern 800 for an emitter electrode comprising a thin film 124 and a polysilicon thin film 126 is formed.
Is removed, that is, the emitter region 116 in a portion that will become an external base region in a later step is removed, thereby forming a residual semiconductor region 116A as an emitter region immediately below the polysilicon thin film 126.

Thereafter, as shown in FIG. 33, a silicon oxide film is deposited to a thickness of, for example, 100 nanometers, and a first insulating film 128A serving as a side wall is formed by anisotropic etching. Further, a resist pattern 212 is formed, and using this resist pattern 212 as a mask, a P-type link base region 113a serving as a fifth semiconductor region is formed with a dose of 10 ¹² to 10 ¹⁴ so as to have a lower impurity concentration than the external base.
It is formed by ion implantation of boron of cm ⁻² .

Next, as shown in FIG. 34, a silicon oxide film is deposited to a thickness of, for example, 50 nanometers, and a second insulating film serving as a sidewall is formed on the side surface of the first insulating film 128A by anisotropic etching. A film 128B is formed. Furthermore, a metal thin film (titanium) is formed, for example, to a thickness of 50 nm, and heat treatment is performed at a high temperature for a short time (for example, Rapid Thermal Anea at a temperature of 1000 ° C. for 10 seconds).
An alloy reaction between titanium and silicon is caused by the ling method), and the contact interface between titanium and the polysilicon thin film 126, the external base region 115a, and the collector wall diffusion layer 110 is silicified in a self-aligned manner, and further wet etching is performed. Then, titanium which has not been silicided on the silicon oxide film is removed to form a silicide film 600 to be a metal-semiconductor alloy film. Further, a resist pattern 213 is formed, and using this resist pattern 213 as a mask, a p-type external base region 115a to be a fourth semiconductor region is formed by boron ion implantation at a dose of 10 ¹⁵ to 10 ¹⁶ cm ^-2. I do. By forming such a silicide film 600, the contact resistance of each of the base, collector and emitter electrodes can be reduced. As a result, the area of the contact region can be reduced, and accordingly, high integration and reduction of the parasitic capacitance can be realized, which can contribute to an increase in the speed of the bipolar semiconductor device.

Then, as shown in FIG. 35, a BPSG film 140 serving as a protective film is deposited on the entire surface and flattened by heat treatment, and contact windows of an emitter, a collector and a base are formed on the BPSG film 140. After, metal wiring 14
Form 2. Thus, the third , fourth , fifth and fifth
In the sixth embodiment, when the emitter region 116 and the active base region 114 are formed by ion implantation through the silicon thin film 124, the underlying region of the silicon thin film 124 is only the first semiconductor region 104 serving as a collector. The feature is that there is no step. Bipolar half underlying the present invention
Conductor device, bipolar semiconductor of first and second embodiments
In the case of the device , at the time of deposition of the silicon thin film 124, the surface portion has an insulating film or the like that defines the emitter dimensions, and the silicon thin film 124 is not formed flat. Silicon thin film 12 viewed from the direction
4 is apparently increased compared to the central portion of the emitter region 116. This may affect the junction depth between the emitter region 116 and the active base region 114 formed by the ion implantation and cause a variation in electrical characteristics. The effect is greater for smaller dimensions.
Therefore, as in the third , fourth , fifth and sixth embodiments, the silicon thin film 124 is formed without any steps, and the emitter region 114 and the active base region 116 are formed first by ion implantation. By performing patterning for defining the width of the emitter region later, no matter how small the width of the emitter region becomes,
In addition, the silicon thin film 124 at the time of ion implantation for forming the active base region 114 has no steps and is flat, so that the junction depth at the peripheral portion of the emitter region can be formed as in the central portion. As a result, an npn transistor whose electrical characteristics do not change even when the width of the emitter region is reduced can be formed.

In the third , fourth , fifth, and sixth embodiments, the silicon thin film 124 serving as an emitter
The emitter region 116 and the active base region 114 are formed by ion implantation through the silicon thin film 124, and a polysilicon thin film 126 which is a part of the emitter electrode is formed, for example, to a thickness of 300 nm. If a conductor film such as a metal silicon film (tungsten silicide, molybdenum silicide) or the like is used instead of the above, the contact resistance can be further reduced.

[0080] Further, the process of silicide formation shown in the sixth embodiment, can be shared with the silicidation process of the gate-source and drain of CMOS, it is easily applied to BiCMOS process, to the sixth embodiment The illustrated silicide formation process can be applied to the third and fourth embodiments.

[0081]

According to the method of manufacturing a bipolar semiconductor device of the present invention, impurities of the first conductivity type and the second conductivity type are implanted through the same first semiconductor thin film such as polysilicon to form the emitter and the emitter. By forming the second and third semiconductor regions serving as bases, the base width can be made smaller than before by a relatively low diffusion temperature and a short time while eliminating the influence of the natural oxide film. Variations in base width due to variations in film thickness can be prevented.
Therefore, the non-single-crystal second semiconductor thin film serving as an extraction electrode used for a transistor of a bipolar integrated circuit, and the second semiconductor containing high-concentration impurities serving as an emitter serve as an extraction electrode.
Electrical characteristics in connection with the remaining semiconductor region patterned by patterning the second semiconductor region or the second semiconductor region can be improved, the speed and the integration can be improved, and the thickness of the first semiconductor thin film can be improved. Can be suppressed from affecting the electrical characteristics.

Further, according to the method of manufacturing a bipolar semiconductor device according to claim 1 or 2 , impurities of the first conductivity type and the second conductivity type are ion-implanted through the first semiconductor thin film, and the emitter and the impurity are implanted. Before forming the first and second conductive type second semiconductor regions and the second conductive type third semiconductor region, the second semiconductor film is formed directly below the second insulating film through an opening formed in the first semiconductor region. By forming a link base region by introducing a conductive type impurity in a self-aligned manner, the third semiconductor region serving as a base and the external base region can be reliably connected. Further, claim 3 , claim 4 ,
According to the method of manufacturing a bipolar semiconductor device according to claim 5 or 6 , the first semiconductor thin film at the time of ion implantation for forming the second semiconductor region serving as the emitter and the third semiconductor region serving as the base is: After forming the second semiconductor region and the third semiconductor region, the second semiconductor region is patterned after forming the second semiconductor region and the third semiconductor region, thereby forming a residual semiconductor region serving as a substantial emitter. Therefore, the junction depth at the peripheral portion of the residual semiconductor region serving as the emitter and the peripheral portion of the third semiconductor region serving as the base can be formed as in the central portion, and particularly, the electrical characteristics generated when the dimensional width of the emitter is reduced. Changes can be reduced. According to the manufacturing method of the bipolar semiconductor device according to claim 5, to form a side wall in two of the first insulating film and the second insulating film, the first time the first insulating film A fifth semiconductor region serving as a link base having an appropriate impurity concentration and profile is formed in a self-aligned manner by ion implantation used for a mask, and a second semiconductor region is formed externally by ion implantation using a second insulating film as a mask for the second time. A fourth semiconductor region serving as a base region is formed in a self-aligned manner. Therefore, by adjusting the thicknesses of the sidewall-shaped first and second insulating films, the third semiconductor region serving as a base and the fourth base serving as an external base can be maintained while maintaining the reliability of the bipolar semiconductor device. The semiconductor regions can be reliably connected via the fifth semiconductor region serving as a link base.
According to the method of manufacturing a bipolar semiconductor device of the sixth aspect , in the method of manufacturing a bipolar semiconductor device of the third, fourth or fifth aspect , the metal-semiconductor alloy is formed on the surface of the fourth semiconductor region serving as an external base. By forming the film, the contact resistance to the electrode can be reduced. As a result, the area of the contact region can be reduced,
Accordingly, high integration and reduction of parasitic capacitance can be realized, which can contribute to speeding up of the bipolar semiconductor device.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first step of a method for manufacturing a bipolar semiconductor device on which the present invention is based .

FIG. 2 is a cross-sectional view showing a second step of the method for manufacturing the same bipolar semiconductor device.

FIG. 3 is a cross-sectional view showing a third step of the method for manufacturing the same bipolar semiconductor device.

FIG. 4 is a cross-sectional view showing a fourth step of the method for manufacturing the same bipolar semiconductor device.

FIG. 5 is a cross-sectional view showing a fifth step of the method for manufacturing the same bipolar semiconductor device.

FIG. 6 is a sectional view showing a final step of the manufacturing method of the bipolar semiconductor device.

FIG. 7 is a cross-sectional view showing a first step of the method for manufacturing the bipolar semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing a second step of the method for manufacturing the same bipolar semiconductor device.

FIG. 9 is a cross-sectional view showing a third step of the method for manufacturing the same bipolar semiconductor device.

FIG. 10 is a sectional view showing a fourth step of the method for manufacturing the same bipolar semiconductor device.

FIG. 11 is a cross-sectional view showing a fifth step of the method for manufacturing the same bipolar semiconductor device.

FIG. 12 is a sectional view showing a sixth step of the method for manufacturing the same bipolar semiconductor device.

FIG. 13 is a cross-sectional view showing a final step of the method for manufacturing the same bipolar semiconductor device.

FIG. 14 is a cross-sectional view showing a first step of a method for manufacturing a bipolar semiconductor device according to the second embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a second step of the method for manufacturing the same bipolar semiconductor device.

FIG. 16 is a cross-sectional view showing a third step of the method for manufacturing the same bipolar semiconductor device.

FIG. 17 is a cross-sectional view showing a fourth step of the method for manufacturing the same bipolar semiconductor device.

FIG. 18 is a sectional view showing a fifth step of the method for manufacturing the same bipolar semiconductor device.

FIG. 19 is a cross-sectional view showing a sixth step of the method for manufacturing the same bipolar semiconductor device.

FIG. 20 is a sectional view showing the final step of the method for manufacturing the same bipolar semiconductor device.

FIG. 21 is a cross-sectional view showing a first step of the method of manufacturing the bipolar semiconductor device according to the third , fourth , fifth, and sixth embodiments of the present invention.

FIG. 22 is a cross-sectional view showing a second step of the method for manufacturing the same bipolar semiconductor device.

FIG. 23 is a cross-sectional view showing a third step of the method for manufacturing the same bipolar semiconductor device.

FIG. 24 is a sectional view showing a final step of the method for manufacturing the same bipolar semiconductor device.

FIG. 25 is a cross-sectional view showing a fifth step of the method for manufacturing the bipolar semiconductor device according to the third embodiment of the present invention.

FIG. 26 is a cross-sectional view showing the final step of the method for manufacturing the same bipolar semiconductor device.

FIG. 27 is a cross-sectional view showing a fifth step of the method for manufacturing a bipolar semiconductor device according to the fourth embodiment of the present invention.

FIG. 28 is a cross-sectional view showing a sixth step of the method for manufacturing the same bipolar semiconductor device.

FIG. 29 is a cross-sectional view showing a final step of the method for manufacturing the same bipolar semiconductor device.

FIG. 30 is a sectional view showing a fifth step of the method for manufacturing the bipolar semiconductor device according to the fifth embodiment of the present invention;

FIG. 31 is a cross-sectional view showing a sixth step of the method for manufacturing the same bipolar semiconductor device.

FIG. 32 is a cross-sectional view showing the final step of the method for manufacturing the same bipolar semiconductor device.

FIG. 33 is a cross-sectional view showing a fifth step of the method for manufacturing the bipolar semiconductor device according to the sixth embodiment of the present invention.

FIG. 34 is a cross-sectional view showing a sixth step of the method for manufacturing the same bipolar semiconductor device.

FIG. 35 is a sectional view showing a final step of the method for manufacturing the same bipolar semiconductor device.

FIG. 36 is a diagram showing impurity profiles of an emitter region and an active base region of an npn transistor to which a manufacturing method of a bipolar semiconductor device as a basis of the present invention is applied and an npn transistor to which a conventional manufacturing method is applied.

FIG. 37 is a diagram showing Gummel characteristics of an npn transistor to which the method for manufacturing a bipolar semiconductor device according to the second embodiment of the present invention is applied;

FIG. 38 is a diagram showing characteristics of a current amplification factor h _FE of an npn-type transistor with respect to a collector current Ic to which a method of manufacturing a bipolar semiconductor device according to a second embodiment of the present invention is applied.

FIG. 39 shows an npn transistor to which the manufacturing method of the bipolar semiconductor device according to the second embodiment of the present invention is applied, an npn transistor to which the manufacturing method of the conventional example (1) is applied, and a manufacturing of the conventional example (3). FIG. 10 is a diagram showing the emitter window area dependence of the emitter resistance of an npn-type transistor to which the method is applied.

FIG. 40 is a diagram showing an impurity profile when the order of ion implantation of arsenic (As) and boron (B) is changed in the method of manufacturing the bipolar semiconductor device according to the second embodiment of the present invention.

[Explanation of symbols]

104 Epitaxial semiconductor layer (first semiconductor region) 124 Silicon thin film (first semiconductor thin film) 116 Emitter region (second semiconductor region) 114 Active base region (third semiconductor region) 126 Polysilicon thin film (second Semiconductor thin film) 123 Polysilicon thin film (thin film for base lead electrode) 127 Inter-polysilicon oxide film (first insulating film) 500 Opening 115 External base region 129 Sidewall silicon oxide film (second insulating film) 113 Ring Base region 400 Opening 130 Sidewall thermal oxide film (second insulating film) 131 Injection protective oxide film (third insulating film) 116A Residual semiconductor region 128C Insulating film 115a External base region (fourth semiconductor region) 113a Ring base Region (fifth semiconductor region) 128A First insulating film 128B Second insulating film 600 Silicide film (metal-semiconductor alloy film) 800 Semiconductor film for emitter electrode turn

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Atsushi Hori 1006 Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-2-3916 (JP, A) JP-A-61- 131546 (JP, A) JP-A-58-77253 (JP, A) JP-A-57-96548 (JP, A) JP-A-62-188370 (JP, A) JP-A-61-14757 (JP, A) JP-A-3-19328 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/73-29/732 H01L 21/331

Claims (6)

(57) [Claims] 1. A first conductivity type single crystal material serving as a collector
A second conductive type semiconductor thin film is formed on the first semiconductor region.
Forming a base extraction electrode thin film, and forming a first insulating film on the base extraction electrode thin film.
Removing the base extraction electrode thin film and the first insulating film.
The first half is selectively etched sequentially.
Forming at least one or more openings in the conductor region
And the first semiconductor region immediately below the base extraction electrode thin film.
An external base region comprising a semiconductor region of the second conductivity type in the region.
Forming a region, and forming a second insulating film on a side wall of the base extraction electrode thin film.
Forming a second conductive film in the opening using the second insulating film as a mask.
By injecting electric type impurities obliquely,
Connecting the external base region to the first semiconductor region;
Base region comprising second conductivity type semiconductor region for
Forming a region and forming a non-monocrystalline first semiconductor thin film over the entire surface
And an impurity of the first conductivity type is injected through the first semiconductor thin film.
Forming an emitter in the first semiconductor region.
For forming a second semiconductor region of the first conductivity type to be formed
And an impurity of the second conductivity type is injected through the first semiconductor thin film.
The third half of the second conductivity type serving as a base.
Forming a conductor region, and forming a second semiconductor thin film on the first semiconductor thin film
A step, the first semiconductor thin film and a second half formed on the opening
Patterning of conductive thin film to become emitter electrode
And an impurity of the first conductivity type in the second semiconductor thin film.
And a method of manufacturing a bipolar semiconductor device. 2. A monocrystalline silicon of the first conductivity type serving as a collector.
A second conductive type semiconductor thin film is formed on the first semiconductor region.
Forming a base extraction electrode thin film, and forming a first insulating film on the base extraction electrode thin film.
Removing the base extraction electrode thin film and the first insulating film.
The first half is selectively etched sequentially.
Forming at least one or more openings in the conductor region
And the first semiconductor region immediately below the base extraction electrode thin film.
An external base region comprising a semiconductor region of the second conductivity type in the region.
Forming a region, and forming a second insulating film on a side wall of the base extraction electrode thin film.
Forming a third insulating film over the opening; and forming a second conductive type impurity through the third insulating film over the opening.
Is injected into the first semiconductor region.
Semiconductor region of second conductivity type for connecting external base region
Forming a link base region comprising a region, and forming a fourth insulating film on a side wall of the base lead electrode thin film.
Leaving a step and forming a non-monocrystalline first semiconductor thin film on the entire surface
And an impurity of the first conductivity type is injected through the first semiconductor thin film.
Forming an emitter in the first semiconductor region.
For forming a second semiconductor region of the first conductivity type to be formed
And an impurity of the second conductivity type is injected through the first semiconductor thin film.
The third half of the second conductivity type serving as a base.
Forming a conductor region, and forming a second semiconductor thin film on the first semiconductor thin film
A step, the first semiconductor thin film and a second half formed on the opening
Patterning of conductive thin film to become emitter electrode
And an impurity of the first conductivity type in the second semiconductor thin film.
And a method of manufacturing a bipolar semiconductor device. 3. A single-crystal of the first conductivity type serving as a collector.
Forming a first semiconductor thin film on the first semiconductor region;
At this time, the first conductivity type impurity is injected through the first semiconductor thin film.
The second half of the first conductivity type which becomes an emitter when
Forming a conductive region, and injecting a second conductive type impurity through the first semiconductor thin film.
The third semiconductor of the second conductivity type which becomes the base
Forming a body region, and forming a second semiconductor thin film on the first semiconductor thin film
And patterning the first semiconductor thin film and the second semiconductor thin film.
Ri due to Ningu semiconductor film pattern of the emitter electrode for
Of forming a semiconductor film pattern for an emitter electrode
And selectively removing the second semiconductor region of the first conductivity type.
Immediately below the semiconductor film pattern for the emitter electrode.
The remaining semiconductor region of the second semiconductor region serving as the emitter;
Forming a region and forming sidewall-shaped insulation on the side surfaces of the remaining semiconductor region.
Leaving a film, and forming the insulating film and the semiconductor film pattern for the emitter electrode.
Is used as a mask to remove impurities of the second conductivity type from the third semiconductor.
A second conductive material that becomes an external base by being implanted into the region
Forming a fourth semiconductor region of a mold type;
And a step of connecting the third semiconductor region to the third semiconductor region . 4. A first conductivity type single crystal material serving as a collector.
Forming a first semiconductor thin film on the first semiconductor region;
At this time, the first conductivity type impurity is injected through the first semiconductor thin film.
The second half of the first conductivity type which becomes an emitter when
Forming a conductive region, and injecting a second conductive type impurity through the first semiconductor thin film.
The third semiconductor of the second conductivity type which becomes the base
Forming a body region, and forming a second semiconductor thin film on the first semiconductor thin film
And patterning the first semiconductor thin film and the second semiconductor thin film.
Semiconductor for extracting the emitter electrode
Step of forming a film pattern and a portion where a semiconductor film pattern for the emitter electrode is formed
And selectively removing the second semiconductor region of the first conductivity type.
Immediately below the semiconductor film pattern for the emitter electrode.
The remaining semiconductor region of the second semiconductor region serving as the emitter;
Forming a region, and using the semiconductor film pattern for the emitter electrode as a mask.
Implanting a second conductivity type impurity into the second semiconductor region;
To form a fifth semiconductor region of the second conductivity type serving as a link base.
Forming and forming sidewall-shaped insulation on side surfaces of the residual semiconductor region.
Leaving a film, and forming the insulating film and the semiconductor film pattern for the emitter electrode.
A second conductivity type impurity using the first semiconductor
A second conductive material that becomes an external base by being implanted into the region
Forming a fourth semiconductor region of a mold type;
And the residual semiconductor region via the fifth semiconductor region.
And manufacturing the bipolar semiconductor device. 5. A first conductivity type single crystal material serving as a collector.
Forming a first semiconductor thin film on the first semiconductor region;
At this time, the first conductivity type impurity is injected through the first semiconductor thin film.
The second half of the first conductivity type which becomes an emitter when
Forming a conductive region, and injecting a second conductive type impurity through the first semiconductor thin film.
The third semiconductor of the second conductivity type which becomes the base
Forming a body region, and forming a second semiconductor thin film on the first semiconductor thin film
And patterning the first semiconductor thin film and the second semiconductor thin film.
The semiconductor film pattern for the emitter electrode.
Of forming a semiconductor film pattern for an emitter electrode
And selectively removing the second semiconductor region of the first conductivity type.
Then, the semiconductor film pattern for extracting the emitter electrode is removed.
Immediately below the second semiconductor region serving as the emitter.
Forming a conductor region; and forming a sidewall-shaped first on a side surface of the residual semiconductor region.
Leaving the first insulating film and the semiconductor pattern for the emitter electrode.
And a second conductivity type impurity using the first half as a mask.
Inject into the conductor area to become the link base
A fifth semiconductor region of two conductivity type is formed, and the fifth semiconductor region is formed.
Connecting a body region and the residual semiconductor region; and forming a second sidewall-shaped second side wall on the side surface of the first insulating film.
Leaving an insulating film; a semiconductor pattern for the emitter electrode;
Using the second insulating film as a mask and impurities of the second conductivity type
The external base is implanted into the first semiconductor region.
Forming a fourth semiconductor region of a second conductivity type,
Connecting the fourth semiconductor region to the fifth semiconductor region.
And a method for manufacturing a bipolar semiconductor device. 6. The method according to claim 6, wherein a surface of said fourth semiconductor region is selectively formed.
It is noteworthy that a process for forming a metal-semiconductor alloy film has been added.
The method for manufacturing a bipolar semiconductor device according to claim 3, 4 or 5, wherein