JPS6273667A - Manufacturing semiconductor element - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a high-speed bipolar transistor that operates even in an ultra-high frequency region.

[Prior Art] Generally, in order to provide an integrated circuit with good electrical characteristics, it is required that each element constituting the integrated circuit has good operating speed characteristics and good power consumption characteristics. In particular, bipolar circuits, which are often used in parts that require high speeds such as computer central processing units and communication integrated circuits, are becoming more and more complex as systems themselves become more complex. Needs improvement.

FIG. 3 shows a cross section of a conventional bipolar transistor using a PN junction. The method of separating elements using junction surfaces, which has been used up to now in the manufacture of bipolar integrated circuits, takes into account the effects of lateral diffusion and the presence of depletion regions, and reduces the size of the portion (11) shown in Figure 3. cannot be reduced beyond a certain limit, so there are many restrictions on reducing the device area.

Therefore, it was not possible to further reduce the resistance and capacitance components of the element itself, and it was not possible to obtain very good results in terms of operating speed and power consumption.

Bipolar transistor manufacturing techniques have recently been developed to solve the above problems. The oxide film (S
iOz) and the polycrystalline silicon layer (2
The transistor obtained by combining the self-alignment of the emitter (22) and base (24) according to 1) is called ps^(Pol
ysilicon 5elf -ali3end) It is called a transistor.

By applying this technology to manufacture integrated circuits, it is possible to reduce the area of the device, and the emitter (22), base (24)
Since the junction is formed with a shallow depth, the resistance and capacitance components present in the device are reduced, resulting in better results in terms of operating speed, power consumption, and degree of integration.

Figure 4 shows a bipolar NP fabricated by the PSA method.
FIG. 3 is a cross-sectional view of an N transistor. In addition, when manufacturing a PS^ bipolar NPN I-run sister whose emitter and base are self-aligned using polycrystalline silicon,
In order to reduce the series resistance component present in the base region, a portion (23) in FIG.
A P"inactive base region with a high concentration of impurities is formed as shown in FIG. On the contrary, the speed will decrease.To solve this problem, transistors made using new manufacturing methods will be developed.

This is shown in Figure 5.
31) The oxide film (32) with a thickness of 1,500 mm on the lower part is reduced to approximately 4,000 to 6,000 percent by wet etching.
After etching, P polycrystalline silicon is buried and heat treated using a low pressure vapor phase growth method, and the width is 4000 mm as shown in Fig. 5.
Form an inactive base area (33) of ~6000 people.

However, although the bipolar NPN transistor made in this way has significantly improved operating speed characteristics compared to the PS8-Run sister, the width of the inactive base region is determined by wet etching, making it difficult to adjust the process. Moreover, the process proceeds with the part where the emitter will be formed in the NPN I-lan sister exposed, so the silicon surface in the active area of the transistor is damaged during the process, especially during the dry etching process, which may cause electrical damage to the device. Characteristics may deteriorate.

[Problems to be Solved by the Invention] An object of the present invention is to solve the above-mentioned conventional drawbacks and to provide a method for manufacturing a semiconductor device with a small device area, high operating speed, and good electrical characteristics. do.

[Means for Solving the Problems] In order to achieve such an object, the method for manufacturing a semiconductor device of the present invention includes implanting arsenic ions into the surface of a wafer,
An N+ buried layer is formed by diffusion at 1200°C, and an N type epitaxial layer doped with phosphorus is formed on top of the N+ buried layer to a thickness of 1.6 cm.
55 μm on the surface of the oxide film formation site as a mask.
In a method of manufacturing a semiconductor device, the method involves etching a 00-layer film, then ion-implanting a P'-type impurity, and forming an oxide film (1) with a Jγ size of IOK using a wet oxidation method at 925° C. to separate each device. , boron ions Y are mainly introduced to form the base region (2) of the transistor, a polycrystalline silicon layer with a thickness of 3000 nm is formed on the entire surface of the wafer by low pressure vapor phase epitaxy, and impurities ( The process of converting arsenic (arsenic) into N-type ions and forming a 2000-layer primary oxide film layer (4) on the N-type using a low pressure vapor phase growth method.
Steps of forming a primary nitride film layer (6) and photolithography are used to determine the parts of the polycrystalline silicon that will become the emitter (15) and collector (16), and the excess parts are removed by dry etching. Then, the N9 polycrystalline silicon layer (3) is excessively etched under the oxide film to increase the emitter width (5) by 2.
A secondary oxide film with a thickness of 2,500 μm is grown in a vacuum vapor phase, and the oxide film (8' ), and forming a secondary nitride film (9) with a thickness of 2,000 to 3,000 people on it,
A step of removing the upper secondary nitride film layer (9') by plasma etching, a step of etching the silicon surface around the polycrystalline silicon layer by about 1500 Å by dry etching, and a step of etching the etched polycrystalline silicon layer by 500 people. An oxide film with a thickness of 700 mm is grown on top of it.
The process of depositing the next nitride film layer (11) by low pressure vapor phase epitaxy and the upper nitride layer 1 of the tertiary nitride film layer by plasma etching.
1i (11'), growing an oxide film (12) with a thickness of 2500 nm, and removing the primary, secondary, and tertiary nitride films (6, 9, and 11) by wet etching. A process of depositing 3,000 polycrystalline silicon in the open area by low pressure vapor phase growth, doping with boron by thermal diffusion to form a P1 type, and photolithography and dry etching to form a P''% crystalline silicon layer (13).
and thermally diffusing to form a P3 non-active base region (14).

[Function] The bipolar NPN I-run sister fabricated according to the present invention can be fabricated with the width of the P'' non-active base region precisely within the range of 2000-3000 mm as required, so that other transistors Compared to this, the area of the lever can be made as narrow as possible.

In the NPN transistor manufactured according to the present invention, the emitter made of polycrystalline silicon is formed at the beginning of the process, and the active area of the transistor is protected by the polycrystalline silicon layer throughout the process so that the surface is not damaged, so that each element is in good condition. Not only can individual devices with good electrical characteristics be obtained, but also the yield of whole wafers is good.

[Example] An example of the present invention will be described in detail with reference to FIGS. 1(8) to F).

FIG. 1(^) is a cross-sectional view showing an embodiment up to element isolation by an oxide film (1). To explain this in μ, inside the body, arsenic was ion-implanted into the surface of a P-type silicon wafer with a thickness of 0 using a human oxide film as a mask, and then heated to 1200°C.
After the oxide film was completely removed, a 16 μm thick N-type epitaxial layer doped with phosphorus and having a resistivity of 0.2 Ωcm was grown.

The next step is to form an oxide film that separates the device, including an oxide film with a thickness of 500 and a nitride film (Si3N) with a thickness of 2000.
Using 4) as a mask material, the surface of the silicon where the isolation oxide film (1) is to be formed is etched to about 5500 Å, and ions are implanted to form a P'''' isolation layer.
Oxidized M(1) with a thickness of 10M by wet oxidation method at 25℃
grew. Next, boron ions are implanted into the base (2
), a polycrystalline silicon film with a thickness of 3,000 wafers was deposited on the entire surface of the wafer by low pressure vapor phase epitaxy, and arsenic ions were implanted to form an N-type film. 1 of 2000 people thick on it
Secondary oxide layer (4) and primary nitride layer (6) with a thickness of 2000 mm
is achieved using the low pressure vapor phase growth method. Here, the emitter and collector are formed using photoetching. Polycrystalline silicon part (3)
Determine the area and remove unnecessary parts using dry etching. In this process, the final polycrystalline silicon layer is wet-etched by leaving about 500 layers during dry etching to protect the silicon surface, and the oxidized I The lower part of the film was corroded excessively, and the emitter width (5) formed was much narrower than the predetermined width of 2 μm.

Figure 1 (B) shows N3 which constitutes the emitter and external conductor.
This is a process of forming electrically insulating oxide films on both side walls of polycrystalline silicon. When a secondary oxide film is grown in a vacuum vapor phase to a thickness of 2,500 mm and this film is subjected to reactive ion etching, which is a type of dry etching, the oxide film (8') on the top surface of polycrystalline silicon is completely corroded, and the side surfaces of the polycrystalline silicon are completely corroded. oxide film (8
) remains as is, and oxide films are formed on both sides.

This method is a typical example of applying the characteristics of dry etching, and takes advantage of the fact that when dry etching an oxide film or nitride film, vertical surfaces are not corroded, but only horizontal surfaces are corroded. Here, the primary oxide film (4) is protected by the primary nitride film (6), so it is not damaged.

FIG. 1C shows a step of forming a secondary nitride film (9) to form a P'inactive base region (14).

First, a secondary nitride film is formed over the entire wafer by low pressure vapor phase epitaxy. The thickness of this secondary nitride film is an important factor that determines the width of the non-active base region, and by appropriately adjusting this thickness, it is possible to achieve the very narrow width of the P layer, which is the object of the present invention.
``A non-active base region can be easily formed. In the present invention, the thickness of the secondary nitride film is adjusted to 2000 to 300 nm as necessary.
The film is then removed by plasma etching, which is a type of dry etching, to form a nitride film (9) on both walls, similar to the secondary oxide film.

FIG. 1(D) shows the bird's beak generated during the growth of the isolation oxide film (12) shown in FIG. 1(El).
This is a step of forming tertiary nitride nu (11) to prevent the l-type oxide film from growing to the part where the P inactive base is to be formed.

First, as a preliminary step for forming the isolation oxide film (12), the surface of the silicon around the polycrystalline silicon layer is etched by about 1500 Å by dry etching. Then grow a 500-layer buffer oxide film and on top of this film about 7
A 3000 tertiary nitride film (,11) is deposited by low pressure chemical vapor deposition. This is etched using a plasma method, and as shown in Figure 1 (DJ) of the previous process, approximately 1500 Å is etched.
By leaving the nitride film (11) only on the sidewalls of the etched silicon, it was possible to prevent the formation of a beak shape when an isolation oxide film is grown in the next step.

FIG. 1(E) shows the step of growing an isolation oxide film, 9
A 2,500 oxide film (12) was grown on the silicon layer, which was etched to about 1,500 Å by wet oxidation at 29°C.

Here, the portion where the P"inactive base region is formed is 2
The next nitride film protects the oxide film from being formed.

FIG. 1F shows a step in which a P''' inactive base region (14) is formed by a P' polycrystalline silicon layer (13). First, wet etching was used to remove the primary, secondary, and tertiary nitride films so that the portion where the P non-active paste region was to be formed was opened.

The present invention provides a very narrow P° non-active region with a thickness of 20 mm.
It is formed under the secondary nitride film of 0.00 to 3000, and its width is almost the same as the thickness of the secondary film.

The next step was to grow polycrystalline silicon by low pressure vapor phase growth.
After depositing 00000 people, doping with boron by thermal diffusion to form a P+ type, defining a P'' polycrystalline silicon layer (13) by photolithography and dry etching, and then thermally diffusing it again to form a P+ type. “A non-active base region is formed. The subsequent metal layer deposition process is the same as a general transistor manufacturing process.

The metal layer was vacuum deposited with approximately 8000 aluminum. Bipolar NI'N I manufactured through the above process
- The run sister is shown in FIG.

Due to the characteristics of the process, the manufacturing method according to the present invention is shown in FIG. 1 (C).
, (D), (E) If the process is continued without steps, it will be formed in the same way as the existing PS^ transistor. Accordingly, this method can selectively manufacture a general PSA transistor that is a process-dependent transistor and a high-speed transistor in which the area of the P3 non-active base region is reduced as much as possible.

[Effects of the Invention] As explained above, the bipolar N['N I-run sister manufactured according to the present invention has a width of the P3 inactive region within the range of 2,000 to 3,000 as necessary. Because it is precisely manufactured, the area of the lever can be minimized compared to other transistors.

The NPN l-ran sister produced according to the present invention is N
Since the emitter of 0 polycrystalline silicon is formed at the beginning of the process and the active area of the transistor is protected by the polycrystalline silicon layer throughout the process and the surface is not damaged, each device obtains an individual device with good electrical properties. Moreover, there is an advantage that the yield of the whole wafer is good.

Further, according to the present invention, it is possible to selectively manufacture a general PSA transistor with a simple process and a high-speed transistor with a P''' inactive base region reduced in area as much as possible.

[Brief explanation of drawings]

FIG. 1(A) to F) shows a bipolar N according to the present invention.
A cross-sectional view illustrating the manufacturing process of PN l-run sister. Figure 2 is a bipolar NPN manufactured by the method of the present invention.
Figure 3 is a cross-sectional view of a bipolar NPN transistor using a conventional P-N junction, Figure 4 is a cross-sectional view of a conventional bipolar NPN transistor using self-aligned polycrystalline silicon, and Figure 5 is a cross-sectional view of an l-run sister. 1 is a cross-sectional view of a conventional super-self-aligned bipolar NPN I-run sister; FIG. l... Oxide film, 2... Base, 3... Polycrystalline silicon layer, 4... Primary oxide film, 5... Emitter width, 6... Primary nitride film, 8...・Side surface oxide film, 8'...Top oxide film, 9...Secondary side surface nitride film, 9'...Secondary top surface nitride film, 11...Tertiary nitride film, 12...Isolation oxidation film, 13...P" polycrystalline silicon layer, 14...P3 inactive base region;

Claims (1)

[Claims] Arsenic ions are implanted into the surface of the wafer and diffused at 1200°C to form an N^+ buried layer, and a 1.6 μm thick N-type epitaxial layer doped with phosphorus is formed thereon. 5500 Å on the surface of the oxide film formation site was etched as a mask, and then P^+ type impurities were ion-implanted, and 92
Oxide film (1) with a thickness of 10KÅ by wet oxidation method at 5℃
In a semiconductor device manufacturing method that separates each element by forming a
2) is formed on the entire surface of the wafer by low pressure vapor phase epitaxy.
A process of forming a polycrystalline silicon layer with a thickness of 3000 Å, ion-implanting impurity (arsenic) into the polycrystalline silicon layer to make it N^+ type, and depositing on the N^+ type layer by low pressure vapor phase epitaxy. Thickness 2000Å
A process of forming a primary oxide film layer (4) and a primary nitride film layer (6) with a thickness of 2000 Å, and photolithography to form an emitter (15) and a collector (16).
), the excess portion is removed by dry etching, and the N^+ polycrystalline silicon layer (3) is excessively etched under the oxide film to form the emitter width (5). A secondary oxide film with a thickness of 2500 Å is grown in a vacuum vapor phase, and the oxide film (8) on the top surface of the polycrystalline silicon is removed by reactive ion etching, leaving only the oxide film (8) on the side surfaces. ') and then a secondary nitride film (9) with a thickness of 2000 to 3000 Å on top of it.
is formed, and the upper secondary nitride film layer (
9'); etching the silicon surface around the polycrystalline silicon layer by about 1500 Å by dry etching; growing an oxide film of 500 Å on the etched polycrystalline silicon layer; a step of depositing a tertiary nitride film layer (11) with a thickness of 700 Å on the tertiary nitride film layer (11) by low pressure vapor phase epitaxy; a step of removing the upper nitride film (11') of the tertiary nitride film layer by plasma etching; A process of growing an oxide film (12) with a thickness of 2500 Å, and polycrystalline silicon was grown by low pressure vapor phase growth in the open areas where the primary, secondary, and tertiary nitride films (6, 9, and 11) were removed by wet etching. A process of doping boron to form a P^+ type by thermal diffusion and forming a P^+ polycrystalline silicon layer (13) by photolithography and dry etching, followed by thermal diffusion to form a P^+ polycrystalline silicon layer (13). + a step of forming an inactive base region (14).