JP3131986B2 - Bipolar transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a bipolar transistor having excellent high-speed operation.

[Prior Art] Conventionally, a bipolar transistor has a fine self-aligned process technology (SST).
(Proc. of 12th)
conf. on solid-state device, 1980, p. 67).

FIG. 5 is a cross-sectional view showing a conventional npn-type bipolar transistor manufactured by a self-alignment technique.

An n ⁺ type buried layer 22 is selectively formed on the surface of the p ⁻ type silicon substrate 21. On the n ⁺ type buried layer 22, LOCOS (Local
n which is isolated by Oxidation of Silicon) layer 24 ^-
A silicon epitaxial layer 23 and an n ⁺ -type phosphorus diffusion layer 25 are formed.

On the surface of n ⁻ -type silicon epitaxial layer 23, p ⁺ -type intrinsic base region 28 is selectively formed. On the surface of the intrinsic base region 28, an n ⁺ -type emitter region 30 is selectively formed. An external base region 29 is selectively formed on the surface of the epitaxial layer 23 adjacent to the intrinsic base region 28. Then, a silicon oxide film 26 is formed on the region excluding the n ⁺ -type phosphorus diffusion layer 25, the intrinsic base region 28, the external base region 29, and the emitter region 30.

On n ⁺ type phosphorus diffusion layer 25, a collector electrode 33 made of a polycrystalline silicon film is patterned. A base electrode 32 made of a polycrystalline silicon film is formed on the external base region 29 and the silicon oxide film 26 by patterning. Also,
An emitter electrode 31 made of a polycrystalline silicon film is patterned on the emitter region 30. This emitter electrode
A silicon nitride film 27 is interposed between 31 and the base electrode 32. The silicon nitride film 27 is also formed on the base electrode 32 and the silicon oxide film. Further, a silicon oxide film 34 is formed on the silicon nitride film 27.

The Al electrode 35 is pattern-formed on the emitter electrode 31, the base electrode 32, and the collector electrode 33, respectively.

In the bipolar transistor thus configured, the intrinsic base region 28 is formed by ion-implanting a p-type impurity into the surface of the n ⁻ -type silicon epitaxial layer 23, and the external base region 29 is formed by the base electrode 32
Is formed in a self-aligned manner by diffusing a p-type impurity doped at a high concentration into the surface of the intrinsic base region 28.
Further, the emitter region 30 is formed in a self-aligned manner by diffusing an n-type impurity added to the emitter electrode 31 at a high concentration into the surface of the intrinsic base region 28. The element miniaturized by such a self-alignment process is connected to the Al electrode 35 via the emitter electrode 31, the base electrode 32, and the collector electrode 33.

Also, as other conventional bipolar transistors,
Manufactured using low-temperature epitaxial technology (Sy
mp.on VLSI Technology, 1989, pp. 91-92). In this bipolar transistor, after a polycrystalline silicon film for a base electrode is patterned on a collector region made of single crystal silicon, a single crystal is formed on the collector region where the polycrystalline silicon film for a base electrode is not formed by epitaxial growth. The base layer is selectively grown.

Thereafter, an emitter region is selectively formed on the surface of the single crystal base layer. In this case, the single crystal base layer can be thinned by an epitaxial technique.

[Problem to be Solved by the Invention] However, the above-described conventional bipolar transistor has the following problems.

First, in a bipolar transistor manufactured using a self-alignment process, a base region is formed by an ion implantation method.
It is difficult to make the base region thinner. Further, if the base region is to be made thinner by reducing the implantation energy of the impurity and increasing the dose, even if the heat treatment is performed at a predetermined temperature or less and within a predetermined time at which the impurity profile of the base region does not spread. In addition, implantation damage cannot be recovered, and impurities cannot be activated.

Further, in a bipolar transistor having such a structure, it is difficult to form an element on a (100) plane orientation of a silicon substrate having good crystallinity in a manufacturing process.
That is, the base electrode 32 is formed by the following steps. First, after a polycrystalline silicon film for a base electrode is patterned on a silicon oxide film formed on a silicon substrate, the upper surface and side surfaces of the opening of the polycrystalline silicon film are covered, and the silicon The oxide film is removed. At this time, a silicon oxide film 26 is formed by side-etching the silicon oxide film below the polycrystalline silicon film. Next, after depositing an undoped polycrystalline silicon film on the entire surface by a low pressure chemical vapor deposition (LPCVD) method or the like, the undoped polycrystalline silicon film is heat-treated to form the undoped polycrystalline silicon film from an overhang portion of the polycrystalline silicon film. Diffuses impurities. Thus, a base electrode 32 made of a polycrystalline silicon film to which a predetermined impurity has been added is formed. Further, it is necessary to remove the undoped polycrystalline silicon film in a region excluding the region below the overhang portion. In this case, the undoped polycrystalline silicon film can be selectively removed by performing wet etching with hydrazine having etching selectivity between the undoped polycrystalline silicon and the impurity-doped polycrystalline silicon. However, in etching with hydrazine, the etching rate of a single crystal silicon substrate exposing the (100) plane orientation is substantially equal to the etching rate of undoped polycrystalline silicon.
When a silicon substrate having such a crystal orientation is used, the intrinsic base region on the surface is also etched. Therefore, in the structure of the conventional bipolar transistor, it is difficult to form an element in the (100) plane orientation of the silicon substrate.

On the other hand, in a bipolar transistor manufactured using a low-temperature epitaxial technique, the emitter and the base cannot be formed in a self-alignment manner due to the structure. For this reason, it is necessary to newly form a mask for forming the emitter region on the single crystal base layer, and there is a limit to miniaturization of the element. For this reason, it is difficult to reduce the parasitic capacitance and the parasitic resistance of the bipolar transistor.

As described above, with the structure of the conventional bipolar transistor, it is difficult to further improve the operation speed of the bipolar transistor.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a bipolar transistor whose operation speed can be improved as compared with the related art.

[Means for Solving the Problems] A bipolar transistor according to the present invention includes a first insulating film formed on a silicon substrate and having a first opening on a collector region, and a pattern formed on the first insulating film. A base electrode formed and having a second opening having a smaller diameter than the first opening on the first opening; and a second electrode formed on the base electrode and on a side surface of the second opening. An intrinsic base layer formed on the silicon substrate on which the collector region is formed in the first opening and having a thickness smaller than that of the first insulating film; an intrinsic base layer; An external base layer formed so as to fill a gap with a portion where the base electrode protrudes, and an emitter layer formed by epitaxial growth on the intrinsic base layer.

[Operation] In the present invention, the intrinsic base layer is formed in the first opening provided in the first insulating film. Also,
The outer base layer is formed between the base electrode and the intrinsic base layer. Further, the emitter layer is formed on the base layer. Therefore, unlike the case where the intrinsic base layer, the external base layer, and the emitter layer are formed by injecting impurities into the surface of the silicon substrate, the thickness can be easily reduced.

In addition, the intrinsic base layer and the external base layer are formed on a second electrode provided on a base electrode and on a side surface of the second opening.
The first insulating film can be selectively deposited in the first opening using the insulating film as a mask. In this case, the intrinsic base layer growing from the surface of the collector region and the external base layer growing from the surface of the base electrode protruding above the first opening are in close contact with each other, so that the external base layer is And an intrinsic base layer. Therefore, unlike the case where the intrinsic base layer and the base electrode are connected by using the conventional selective etching with hydrazine, the element is formed in the (100) plane orientation of the silicon substrate having good crystallinity. be able to.

Further, the emitter layer can be formed in a self-aligned manner on the intrinsic base layer through the second opening. Therefore, the element can be miniaturized, so that the parasitic capacitance and the parasitic resistance of the transistor can be reduced.

Therefore, according to the present invention, the operation speed of the bipolar transistor can be improved as compared with the related art.

Preferably, the intrinsic base layer is made of a single crystal silicon-germanium mixed crystal, and the external base layer is made of a polycrystalline silicon-germanium mixed crystal. In this case, the band gap of the intrinsic base layer and the external base layer is smaller than the band gap of the emitter layer made of, for example, single crystal silicon. Thus, the base current can be suppressed to an appropriate value, and the cutoff frequency of the transistor can be improved. Also, even if the intrinsic base layer is thinned or highly concentrated in order to maintain the junction breakdown voltage between the collector and the emitter at or above a desired value,
A predetermined current gain can be maintained.

The base electrode preferably has a laminated structure including a polycrystalline silicon layer and a refractory metal silicide layer. In this case, the sheet resistance of the base electrode can be significantly reduced.

Further, in the present invention, an emitter electrode made of a polycrystalline silicon film can be formed on the emitter layer.
The emitter electrode can be selectively deposited on the emitter layer using the second insulating film as a mask, and can be selectively disposed in the second opening. Therefore, the formation region of the emitter electrode can be reduced.

Example Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a sectional view showing an npn-type bipolar transistor according to a first embodiment of the present invention.

The p ^- type silicon substrate 1 has a specific resistance of, for example, about 10Ω · cm.
The surface of which is diffused with arsenic or the like to obtain n ⁺
The mold burying layer 2 is selectively formed. On this n ⁺ -type buried layer 2, an n ⁻ -type silicon epitaxial layer 3 having a thickness of, for example, about 1.0 μm and an impurity concentration of, for example, about 5 × 10 ¹⁵ cm ⁻³ and an n ⁺ -type for extracting a collector are provided. A phosphorus diffusion layer 5 is formed, and the epitaxial layer 3 and the n ⁺ -type phosphorus diffusion layer 5 are separated from each other by a LOCOS layer 4. And LOCOS
A silicon nitride film 6 having a first opening on the epitaxial layer 3 and an opening for forming a collector electrode on the n ⁺ -type phosphorus diffusion layer 5 is formed on the layer 4. A base electrode 12 made of n-type polycrystalline silicon is formed on the silicon nitride film 6 by patterning.
Numeral 12 protrudes above the first opening, and a second opening smaller than the first opening is provided.

On the n ⁻ -type silicon epitaxial layer 3 in the first opening, an intrinsic base layer 8 made of p-type single crystal silicon is provided.
Are formed at a height approximately half that of the silicon nitride film 6. An external base layer 9 made of p-type polycrystalline silicon is formed between the portion of the base electrode 12 protruding above the first opening and the intrinsic base layer 8. Further, an n-type emitter layer 10 made of n-type single crystal silicon is formed on the intrinsic base layer 8 in the first opening.

On n ⁺ type phosphorus diffusion layer 5, a collector electrode 13 made of a polycrystalline silicon film is patterned. On the n-type emitter layer 10, an emitter electrode 11 made of n-type polycrystalline silicon is patterned. This emitter electrode 11
A silicon nitride film 7 and a silicon oxide film 14 are interposed between the silicon nitride film 7 and the silicon oxide film 14, and the silicon nitride film 7 is also formed on the base electrode 12 and the silicon oxide film 6.
Incidentally, the silicon oxide film 14 is formed on the side wall of the silicon nitride film 7.

The Al electrode 15 is patterned on the emitter electrode 11, the base electrode 12, and the collector electrode 13.

Next, a method of manufacturing the bipolar transistor configured as described above will be described.

2 (a) to 2 (e) are partial enlarged cross-sectional views showing a method of manufacturing the bipolar transistor according to the first embodiment in the order of steps. 2 (a) to 2 (e) show the extracted features of the present application, and the manufacturing method of the other parts is omitted.

First, as shown in FIG. 2A, a silicon nitride film 6 having a thickness of, for example, about 2000 ° is formed on the epitaxial layer 3, and then a polycrystalline silicon film for a base electrode and A silicon oxide film is sequentially deposited. Next, using a predetermined photoresist film as a mask, the silicon oxide film and the polycrystalline silicon film in the region where the emitter is to be formed (second opening) are selectively removed by dry etching. Thus, the base electrode 12 made of the polycrystalline silicon film is patterned. Then, decompression CV
After a silicon oxide film is deposited on the entire surface by the method D, the silicon oxide film is etched back by dry etching, so that the silicon oxide film 7 is patterned on the base electrode 12 and on the side surface of the second opening. Form.
Next, using the silicon oxide film 7 as a mask, the silicon nitride film 6 between the epitaxial layer 3 and the base electrode 12 is etched with phosphoric acid to provide a first opening. At this time, the silicon nitride film 6 below the base electrode 12 is side-etched, so that the base electrode
The base electrode 12 and the epitaxial layer 3 are exposed in the first opening so that the base 12 protrudes by about 2000 °.

Next, as shown in FIG. 2 (b), molecular beam epitaxy (MBE) with the crystal growth conditions set appropriately.
By the method, an intrinsic base layer 8 made of single-crystal silicon and an external base layer 9 made of polycrystalline silicon are simultaneously grown on the exposed surface of single-crystal silicon of the epitaxial layer 3 and the exposed surface of polycrystalline silicon of the base electrode 12, respectively. .

Then, as shown in FIG. 2 (c), the intrinsic base layer 8 and the external base layer 9 are mutually connected by the crystal growth by the MBE method. In this case, for example, a substrate temperature of about 60
When the temperature is 0 ° C., the source gas is Si ₂ H ₆ , the degree of vacuum during crystal growth is about 4 × 10 ⁻⁶ Torr, and the growth time is about 55 minutes, the thickness of the intrinsic base layer 8 is about 1100 °. , External base layer 9
Is about 900 mm thick. In the present embodiment,
Although the intrinsic base layer 8 and the external base layer 9 are formed by the MBE method, they may be formed by other growth methods. For example, as such a growth method, an LPCVD method for growing a crystal under a pressure of several Torr, or about 10 ^{-1 to} 10 ^-5 T
There is a CVD method in which crystal growth is performed under orr pressure.

Next, as shown in FIG. 2 (d), an n-type emitter made of single-crystal silicon and having a thickness of several hundreds of millimeters is formed on the intrinsic base layer 8 in the first opening by the above-mentioned MBE method. Tier 10
Grow.

Next, after a silicon oxide film is deposited on the entire surface, the silicon oxide film is etched back by dry etching, so that the silicon oxide film 14 remains on the side of the silicon oxide film 7 in the second opening. This silicon oxide film 14 is provided to reliably prevent a leakage current between the base and the emitter. That is, when the n-type emitter layer 10 is formed on the intrinsic base layer 8 by the MBE method, a facet is easily generated at the interface between the external base layer 9 and the n-type emitter layer 10. Therefore, by providing the silicon oxide film 14, an interface between an emitter electrode, which will be described later, and the n-type emitter layer 10 is appropriately separated from an interface between the external base layer 9 and the n-type emitter layer 10. As a result, it is possible to prevent the occurrence of a leak current due to the influence of the facet.

Next, as shown in FIG. 2 (e), an emitter electrode 11 made of n-type polycrystalline silicon is formed on the n-type emitter layer 10 in the first opening. The emitter electrode 11 made of n-type polycrystalline silicon contributes to the reduction of the base current of the npn-type bipolar transistor, so that the current amplification factor can be improved. Also, an n-type emitter layer
By providing the emitter electrode 11 between the metal wiring 10 and the metal wiring, it is possible to prevent the formation of alloy pits between the metal and the element due to the heat treatment after the formation of the metal wiring, thereby preventing the junction breakdown. Further, the emitter electrode 11 can be formed by selectively growing n-type polycrystalline silicon on the n-type emitter layer 10 using the silicon oxide films 7 and 14 as a mask.
Therefore, the emitter electrode 11 can be selectively arranged in the second opening, and the element can be further miniaturized.

In the subsequent steps, as shown in FIG. 1, after selectively removing the silicon oxide film 7 in the electrode formation region, aluminum or the like is deposited on the entire surface, and the emitter electrode 11 and the base electrode 12 are formed by photolithography. And a pattern is formed on the collector electrode 13.

In this embodiment, the intrinsic base layer 8, the external base layer 9, and the n-type emitter layer 10 are formed by MBE. Therefore, these elements can be easily made thin by reducing the thickness of the silicon nitride film 6. In addition, since the intrinsic base layer 8, the external base layer 9, and the n-type emitter layer 10 are formed by depositing single crystal silicon or polycrystal silicon doped with impurities, ion implantation is not required. The accompanying high-temperature heat treatment is unnecessary. In addition, unlike the case of manufacturing by the conventional self-alignment technique, since the intrinsic base layer 8 and the base electrode 12 are connected by the external base layer 9 formed simultaneously with the intrinsic base layer 8, hydrazine or the like is used. There is no selective etching step used. Therefore, an element can be formed in the (100) plane orientation of the silicon substrate having good crystallinity. Further, unlike the conventional low-temperature epitaxial technology, the n-type emitter layer 10 can be formed on the intrinsic base layer 8 in a self-aligned manner. Therefore, the parasitic capacitance and the parasitic resistance of the bipolar transistor can be reduced.

Therefore, the bipolar transistor according to the present embodiment
High speed operation is superior to the conventional one.

In this embodiment, when forming the intrinsic base layer 8 and the external base layer 9 by the MBE method, the raw material gas (Si
GeH ₄ can be added to ₂ H ₆ ). In this case, on the epitaxial layer 3 made of single crystal silicon, for example, about
A single crystal silicon-germanium mixed crystal containing 15 mol% is grown, and an intrinsic base layer 8 made of the single crystal silicon-germanium mixed crystal is formed. On the other hand, a polycrystalline silicon germanium mixed crystal grows below the overhang portion of the base electrode 12 made of polycrystalline silicon, and an external base made of the polycrystalline silicon germanium mixed crystal is formed between the base electrode 12 and the intrinsic base layer 8. Layer 9 is formed.

The forbidden band width of the silicon germanium base layer is smaller than the forbidden band width of the silicon emitter layer. Note that the amount of reduction of the forbidden band width depends on the mol% of germanium and the amount of distortion of the silicon germanium base layer. Such a difference in the bandgap acts as a barrier for a small number of carriers injected from the base layer into the emitter layer, so that the base current can be appropriately suppressed. Thereby, the cutoff frequency of the bipolar transistor can be improved. Also, the junction breakdown voltage between collector and emitter
Even when the base layer is thinned or highly concentrated in order to keep the BV _CEO at or above a desired value, a predetermined current amplification factor can be maintained.

FIG. 3 is a sectional view showing a bipolar transistor according to a second embodiment of the present invention. In this embodiment, the structure of the base electrode is different from that of the first embodiment.
In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description of those portions will be omitted.

In this embodiment, the base electrode 12 is a polycrystalline silicon layer.
16b and a titanium silicide (TiSi ₂ ) layer 16a formed on the polycrystalline silicon layer 16b.
For example, when the thickness of the TiSi ₂ layer 16a is about 1000 ° and the thickness of the polycrystalline silicon layer 16b is about 1500 °, the base electrode 1
2 of the sheet resistance ρ _s is 2 or 3Ω / □. On the other hand, when it is made of only polycrystalline silicon and its thickness is about 2500 °, the sheet resistance ρ _s of the base electrode 12 is 8 to 9Ω /
□. Thus, in this embodiment, the base electrode
The sheet resistance ρ _s can be remarkably reduced by using the above-described two-layer structure of 12.

Note that this laminated structure can be formed by depositing titanium on the polycrystalline silicon layer 16b by sputtering or the like and then performing silicidation by heat treatment.

FIG. 4 is a partially enlarged sectional view showing a method for manufacturing a bipolar transistor according to a third embodiment of the present invention. Since FIG. 4 shows the next step after the steps shown in FIGS. 2 (a) to (c), the same components are denoted by the same reference numerals and detailed description of those portions will be omitted.

As shown in FIG. 4, the intrinsic base layer 8a deposited on the epitaxial layer 3 is further deposited from the state shown in FIG. 2 (c), and formed so as to reach the lower portion of the base electrode 12. ing. Then, after a silicon oxide film is deposited on the entire surface, the silicon oxide film is etched back by dry etching, so that the silicon oxide film 14 remains on the side of the silicon oxide film 7 in the second opening. Next, an n-type emitter layer 10a made of single-crystal silicon is deposited on the intrinsic base layer 8a by MBE, and an emitter electrode 11a made of n-type polycrystalline silicon is deposited on the n-type emitter layer 10a.

In this embodiment, the n-type emitter layer 10a is formed in the second opening. For this reason, the n-type emitter layer 10a can be miniaturized as compared with the first embodiment, and the parasitic capacitance can be further reduced. Further, unlike the first embodiment, the n-type emitter layer 10a and the external base layer 9 do not directly contact each other and are sufficiently separated by the silicon oxide film 14, so that the generation of facets is suppressed. be able to. As a result, it is possible to reliably prevent the occurrence of a leak current between the emitter and the base.

In this embodiment, when the thickness of the intrinsic base layer 8a is made to be substantially the same as the thickness of the intrinsic base layer 8 in the first embodiment, the silicon nitride film 6 may be formed slightly thinner.

[Effects of the Invention] As described above, according to the present invention, since the base / emitter region is formed on the collector region, the thickness can be easily reduced. In addition, when the base layer and the base electrode are connected, selective etching is not performed on the element region, so that the element can be formed in the (100) plane orientation of the silicon substrate having good crystallinity. Further, since the emitter layer can be formed in a self-aligned manner, the element can be miniaturized, and the parasitic capacitance and the parasitic resistance of the transistor can be significantly reduced.

Therefore, according to the present invention, a bipolar transistor having excellent high-speed operation can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an npn-type bipolar transistor according to a first embodiment of the present invention, FIGS. 2 (a) to 2 (e) are partially enlarged sectional views showing a method of manufacturing the same in the order of steps, and FIG. FIG. 4 is a sectional view showing a bipolar transistor according to a second embodiment of the present invention; FIG. 4 is a partially enlarged sectional view showing a method of manufacturing the bipolar transistor according to the third embodiment of the present invention;
FIG. 5 is a cross-sectional view showing a conventional npn-type bipolar transistor. 1,21; p ^- type silicon substrate, 2,22; n ⁺ type buried layer, 3,23; n ^- type silicon epitaxial layer, 4,24; LOCOS layer, 5,25; n ⁺ type phosphorus diffusion layer, 6,27; silicon nitride film, 7,14,26,34; silicon oxide film, 8,8a; intrinsic base layer, 9; external base layer, 10,10
a; n-type emitter layer, 11, 11a, 31; emitter electrode, 12, 32; base electrode, 13, 33; collector electrode, 15, 35; Al electrode, 16a; titanium silicide layer, 16b; polycrystalline silicon layer, 28; intrinsic base region, 29; external base region, 30; emitter region

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-2-30144 (JP, A) JP-A-2-150033 (JP, A) JP-A-50-68478 (JP, A) JP-A-4- 25028 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/33-21/331 H01L 29/165 H01L 29/68-29/737

Claims (5)

(57) [Claims] A first insulating film formed on a silicon substrate and having a first opening over a collector region; and a first insulating film patterned over the first insulating film and over the first opening. A base electrode having a second opening smaller in diameter than the first opening, a second insulating film formed on the base electrode and on a side surface of the second opening, and inside the first opening. An intrinsic base layer formed on the silicon substrate on which the collector region is formed and having a thickness smaller than that of the first insulating film; and filling a gap between the intrinsic base layer and a portion where the base electrode protrudes. An external base layer formed on
A bipolar transistor having an emitter layer formed by epitaxial growth on the intrinsic base layer. 2. The bipolar transistor according to claim 1, wherein the thickness of the intrinsic base layer is half the thickness of the first insulating film. 3. The bipolar transistor according to claim 1, further comprising a third insulating film formed on a side surface of said second insulating film and in contact with said emitter layer. 4. The method according to claim 1, wherein said intrinsic base layer is made of a single crystal silicon-germanium mixed crystal, and said external base layer is made of a polycrystalline silicon-germanium mixed crystal. The bipolar transistor according to claim 1. 5. The bipolar transistor according to claim 3, further comprising an emitter electrode selectively deposited on the emitter layer and disposed in the second opening.