JPH0451981B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention provides, for example, Integrated Injection
The present invention relates to a method for manufacturing a reverse operation npn transistor used in a Logic (hereinafter referred to as I ² L) integrated circuit (hereinafter referred to as IC).

I ² L shown in FIG. 1 has a composite structure of a lateral pnp transistor (referred to as Tr) that functions as a current source and a load, and a reverse operation npn transistor that performs switching. The manufacturing method is based on the already well-known bipolar IC process.
The impurity distribution of npn Tr is shown in Figure 2. In the graft-based I ² L with such a structure, a lightly doped epitaxial (n ^- epi) layer remains in the emitter layer, where holes are accumulated, and as shown in Fig. 3, the I ² L gate speed increases. , has saturation characteristics in the high current region, and the emitter-base-collector impurity distribution is such that no accelerating electric field is applied for reverse direction operation, making it difficult to increase the frequency.

In order to improve these drawbacks, the embedded base I ² L process shown in FIG. 4 has been proposed. For example, see J. Agraz-Guerena et al. “High Performance
“Upward” Bipolar Technology for VLSI”;
1978 IDEM9-2 (Washington, 1978) Techincal
There is Digest of IEDM (1978) P.209. In this process, first, antimony Sb is selectively diffused into a p ^- type silicon plate 1 to form an n ⁺ layer 2.
Boron (B ⁺ ) is ion-implanted, an n ^- epitaxial layer 4 is grown on it, and at the same time, a p layer 3 that becomes a buried base layer is formed by lifting up from the B ⁺ implanted layer (Fig. 4A). ). Next, the elements are separated by an isolation oxide film 6 formed by selectively oxidizing the nitride layer 5 (FIG. 4B). At this time, a high-pressure oxidation method at a low temperature (700°C) is used to prevent the buried base layer 3 from floating up. After that, the base electrode extraction layer 7 and the emitter layer 8 of the pnp transistor, which will become the injector ^{, are} After forming the collector electrode extraction layers 9 and 10 as an n ⁺ layer, a contact window is opened in the surface oxide film, and a low resistance metal (for example A1) wiring 1
Perform steps 1, 12, 13, and 14 (Figure 4C).
The impurity distribution of the I ² L npn Tr obtained in this manner is shown in FIG. Since the emitter junction of this I ² L npn Tr is formed between it and the heavily doped buried n ⁺ layer 2, there is almost no hole accumulation, and the base impurity distribution is similar to the distribution where an accelerating electric field is applied to the reverse operation transistor. This makes it possible to increase the frequency. As shown in FIG. 3, although the speed is higher than that of the graft-based type I ² L, saturation characteristics are significantly apparent in the high current region. This is because, as shown in FIG. 5, the n ^- epilayer 4 remains in the collector layer, and the accumulation effect here becomes significant.

However, the purpose of lowering the temperature of the separation process in FIG. 4B, suppressing the floating of the buried base layer 3, and leaving the epi layer 4 in the collector layer is to keep the reverse current gain βu of the npn Tr constant. It's for a reason. For example, arsenic (As) is used to form the buried emitter layer 2.
When the buried base layer 3 is raised by high-temperature annealing after epitaxial growth (in the case of the solid line in Fig. 6), the base width is the same as that between the buried emitter n ⁺ layer and the wafer surface. It is determined by the distance from the collector layer due to n ⁺ diffusion, and this means that if the thickness of the epitaxial layer 4 varies, the base width will vary accordingly.
On the other hand, if the epitaxial layer remains in the collector layer, the base width will not be affected by variations in the thickness of the epitaxial layer.
This is because the controllability of βu can be improved.
As shown in Figure 8, this is βu at the As emitter.
This can be seen from the fact that the standard deviation for Sb emitters is ±11.5%, while it is ±16.7%. However, with the As emitter, the
Since the n ^- epi layer does not remain and there is no accumulation effect, the saturation characteristics are small as shown in FIG ^. 3, and high speed is achieved.

This invention was made in view of these points, and it is a buried ace type reverse direction that does not have an n ^- epi layer remaining in the collector layer, enables higher speeds, and improves the control characteristics of βu. A method of constructing an operational npn transistor is provided.

One embodiment of the method of the present invention is to form a high concentration n-type diffusion layer with As as an impurity on a low concentration p-type silicon substrate according to the manufacturing process shown in FIG. 9 in order to obtain the impurity distribution according to the present invention shown in FIG. 2a is selectively formed, and boron (B ⁺ ) is ion-implanted into a partial region to form a low concentration p-type diffusion layer 3a containing B as an impurity. The low concentration n-type layer 4a is formed by an epitaxial growth method using the H ₂ reduction reaction of silane [FIG. 9A]. Then,
Annealing is performed by heat treatment in the element isolation process so that the low concentration p-type diffusion layer is re-diffused to the surface of the low concentration n-type layer [FIG. 9B], npn
The process consists of forming the active base layer 3b of the transistor [FIG. 9C].

In the manufacturing method according to this example, B ⁺ ions are ejected from the surface of the B ⁺ ion-implanted layer by pre-annealing in a high-temperature H ₂ atmosphere during low-pressure epitaxial growth, and are generated by decomposition of dichlorosilane.
The silicon surface including the B ⁺ ion-implanted layer is etched by the CI ions, the surface concentration of the B ⁺ ion-implanted layer decreases, and the floating base concentration decreases (as indicated by the dashed line in Figure 6). (low impurity concentration). Moreover, heat treatment is performed at high temperatures and for long periods of time (1050℃,
7 hours), the buried base layer is lifted up and reaches the wafer surface as shown by the broken line in Figure 7 (the cross section of the device is shown in Figure 9B), and the base layer has an optimal impurity distribution. have a cumulative effect
The n ^-epi layer does not remain in the collector layer either. moreover,
In addition to improving the controllability of the epitaxial film through low-pressure epitaxial growth, the concentration of the base layer is lowered, making it possible to widen the base width, and the effect of variations in the base width due to variations in the epitaxial film on βu is also reduced. The variation in βu is small, and as shown in Figure 8, the standard deviation is 8.9%, indicating very good controllability.

In this example, epitaxial growth was performed in a reducing atmosphere under reduced pressure, so the surface concentration of the buried base layer was reduced during epitaxial growth, and the film thickness controllability of the epitaxial film was improved. Together, these can suppress variations in characteristics due to variations in base width. Furthermore, after the epitaxial growth described above, heat treatment is performed to re-diffuse the impurities in the buried base layer to the wafer surface, so that the active base layer spreads to the wafer surface and creates a hole accumulation effect on the active base layer. No epitaxial layer remains, and higher speeds can be achieved. In this manner, the method of this embodiment can both improve the controllability of characteristics and increase the speed of operation.

In the above explanation, an example of isolation between elements using an oxide film was described, but of course, if there is no isolation of I ² L,
Furthermore, it can also be applied to p ⁺ -n junction separation when fabricated on the same chip using a normal bipolar IC process.

As described above, according to the present invention, the step of forming the active base layer of the reverse operation npn transistor constituting the IIL circuit is performed by selectively replacing the n-type diffusion layer with a highly concentrated buried layer doped with arsenic. a step of selectively forming a low concentration p-type epitaxial layer by implanting boron into a part of the region, and an epitaxial step of growing a low concentration n-type epitaxial layer over the entire surface in a reducing product atmosphere under reduced pressure. The structure consists of a growth step and a heat treatment step in which the impurities in the low concentration p-type diffusion layer are re-diffused to the surface of the low concentration n-type layer by heat treatment, so it is possible to achieve high-speed operation of the IIL circuit, and also to increase the speed of the IIL circuit. This has the effect of improving controllability of characteristics.

[Brief explanation of the drawing]

Figures 1A and B are the basic structure diagram and equivalent circuit diagram of I ² L, Figure 2 is an impurity distribution diagram of an I ² L npn transistor produced by a general bipolar IC process, and Figure 3
The figure shows the speed/power characteristic diagram of the I ² L gate, Figure 4 is a cross-sectional view showing the manufacturing process of the buried base type I ² L, and Figure 5 shows the impurity of the conventional buried base type I ² L npn transistor. Figure 6 is an impurity distribution diagram for each process for buried base type I ² L, Figure 7 is an impurity distribution diagram for heat treatment after epitaxial growth for buried base type I ² L, and Figure 8 is for conventional Embedded base according to the method and the present invention
A diagram showing the manufacturing conditions and characteristics of I ² L, and FIG. 9 are cross-sectional views showing the manufacturing process of the embedded base type I ² L according to the present invention. In the figure, 1 is a P ^- type silicon substrate, 2, 2
a is an n ⁺ type diffusion layer, 3, 3a, 3b are p type diffusion layers,
4 and 4a are n ^- type epitaxial layers, 6 is an isolation oxide film, 7 and 8 are P ⁺ type diffusion layers, 9 and 10 are n ⁺ type diffusion layers, and 11 to 14 are wirings.

Claims (1)

[Claims] 1. In a method for manufacturing a reverse-operating npn transistor constituting an IIL circuit, the step of forming the base layer of the transistor is selectively performed using a highly concentrated buried n-type diffusion layer doped with arsenic. A step in which a low concentration p-type epitaxial layer is grown on the entire surface in a reducing atmosphere under reduced pressure. A method for manufacturing a reverse-operation npn transistor, comprising: an epitaxial growth step; and a heat treatment step for redifusing impurities in the low concentration p-type diffusion layer to the surface of the low concentration n-type layer. . 2. The method for manufacturing a reverse-operation npn transistor according to claim 1, wherein the heat treatment is performed using heat treatment in an element isolation step.