JP2532384B2 - Bipolar transistor and its manufacturing method - Google Patents

Description

FIELD OF THE INVENTION This invention relates to the field of integrated circuit manufacturing. Specifically, the present invention relates to bipolar transistor structures and fabrication methods.

PRIOR ART AND PROBLEMS One property that prevents high frequency and high speed digital operation of bipolar transistors is capacitive coupling between the base and emitter and between the base and collector of the bipolar transistor. Capacitive coupling occurs via the depletion region of each junction. This phenomenon is well known,
Sze, "Physics of Semiconductor Devices," pages 79-81 (1981). Since the base-emitter junction controls the current flow of the transistor, most transistors are made to minimize the area of the base-emitter interface. The area of this interface is the area of the base and emitter in contact with each other. Using a simple parallel-plate Capacitor model, the junction capacitance equation is:

C = ke ₀ / A / d where C is the junction capacitance, k is the relative permittivity of the material between the “polar plates” of the capacitor, e ₀ is the vacuum permittivity, and A is the “ The area of the "polar plate", d is the width of the depletion region of the junction.

Thus, the capacitance of the junction is directly proportional to the area of the junction and inversely proportional to the width of the depletion region of the junction. Therefore, there are three methods to reduce the capacitance of the junction. Reducing the relative permittivity of the bonding material or a portion of the bond, reducing the area of the bond, and increasing the thickness of the bond. Since the active junction region must be composed of the semiconductor material forming the bipolar transistor, it is usually impractical to change the overall junction (active and parasitic) dielectric constant of the bipolar transistor. Therefore, in order to reduce the junction capacitance, either reduce the effective junction area, increase the effective junction thickness, or decrease the relative permittivity of the parasitic junction region. Or the combination of them must be adopted.

FIG. 1 is a side view of a conventional vertical bipolar transistor. A buried collector 3 is formed in the substrate 1.
An N-type epitaxial layer is formed on the substrate 1 and an isolation oxide region 2 is formed in the epitaxial layer. A base region 5 is formed on the epitaxial region 4, and an emitter region 6 is formed in the base region 5. The contact diffusion portion 9 enables the ohmic contact of the base contact 8. The emitter contact 7 is in direct contact with the emitter area 6.
In this structure, and in most vertical bipolar transistors, the area of the base-emitter interface is much smaller than the area of the base-collector interface. Therefore, the overall parasitic capacitance of the vertical bipolar transistor can be minimized by reducing the base-collector capacitance. Therefore, it is an object of the present invention to minimize the base-collector capacitance of a vertical bipolar transistor.

Means and Actions for Solving Problems The bipolar transistor of the present invention is a bipolar transistor having a structure having a base on an insulator.
A first conductivity type single crystal semiconductor material collector region, a second conductivity type homogeneous single crystal semiconductor material base region formed adjacent to the collector region, and the base region. An insulator region disposed between the collector region and the extrinsic base that substantially separates the entire extrinsic base from the collector region and does not eliminate an interface area between the base region and the collector region; An emitter region of the first conductivity type formed by diffusion from silicon and formed in the base region, the emitter region not in contact with the collector region; and the extrinsic base and the insulator. At the interface with the region, the extrinsic base does not substantially extend beyond the insulator region.

The bipolar transistor manufacturing method of the present invention is a method for manufacturing a vertical bipolar transistor having a structure having a base on an insulator, and a first conductivity type substrate acting as a collector of the transistor is prepared. Implanting atoms into the substrate to a selected depth to react with the substrate to form an insulator region, and sidewalls above the region of the substrate where the extrinsic base of the transistor is formed. Forming a dielectric and, after forming the insulator region, implanting dopant ions of a second conductivity type into the substrate, the implanted dopant ions being offset by the sidewall dielectric. By forming the base with a region of the extrinsic base that is Base and a step to avoid substantially protrude beyond said insulator region, and forming an emitter region by implanting ions of the first conductivity type in the substrate.

In one embodiment of a vertical bipolar transistor constructed in accordance with the present invention, oxygen is implanted into the vertical bipolar transistor to form a silicon dioxide layer between the parasitic extrinsic base region and the collector of the vertical bipolar transistor. To provide. This silicon dioxide layer reduces the actual interface area of the base-collector junction, thus
The capacitance of the collector-collector junction is reduced. Further, the thickness and relative permittivity of the silicon dioxide layer are as follows. That is, the capacitance sandwiching the silicon dioxide layer, and hence the capacitance between the base and the collector, becomes extremely smaller than the capacitance between the base and collector formed by the base-collector junction itself. This is because the relative permittivity of silicon dioxide is about 3.9, which is smaller than that of crystalline silicon, which is about 11.7.

Example FIG. 2A to FIG. 2H show a vertical bipolar transistor having a reduced base-collector capacitance according to one embodiment of the present invention.
FIG. 3 is a schematic side view showing the process steps required to make a transistor. The diffusion region 3 in FIG. 2A is an N + type diffusion portion formed in the P type substrate 1 using a well-known method. The epitaxial layer 10 of silicon in FIG. 2B is formed on the surface of the substrate 1 using known methods to a thickness of about 1 micron. The epitaxial layer 10 is formed using a well-known method.
Silicon oxide layer 11 and silicon nitride layer on the surface of
12 are formed and define the pattern. Thereafter, the epitaxial layer 10 is subjected to anisotropic etching to form the structure shown in FIG. 2C. The silicon dioxide layer 2 in FIG.
Thermally grow for about 8 hours in a steam atmosphere at a temperature of 975 ° C. After that, the silicon nitride layer 12 and the silicon dioxide layer 11 are removed by using a known method. Next, the silicon dioxide layer 14 is exposed to about 90 minutes in an oxygen atmosphere at a temperature of 950 ° C.
Thermally grow to a thickness of 300Å. Next, the polycrystalline silicon layer 14a is formed to a thickness of about 2,000Å by chemical reaction vapor deposition. Next, using chemical reaction vapor deposition, the silicon nitride layer 13 is formed to a thickness of about 2,000Å. Next, the silicon dioxide layer 13a is deposited to a thickness of 6,000 to 8,000Å by chemical reaction vapor deposition or plasma deposition. Next, using a known method, a silicon dioxide layer is formed.
14, the patterns of the silicon dioxide layer 13a, the polycrystalline silicon layer 14a and the silicon nitride layer 13 are defined and subjected to anisotropic etching. The epitaxial layer 10 is then subjected to an implantation of oxygen ions (O ₂ ) with an energy of about 300 kiloelectron volts and a density of 6E17 (6 × 10 ¹⁷ ) ions / cm ² . After the implantation of oxygen, the silicon dioxide layer 14 is densified without forming a noticeable undercut (densif eye).
The silicon dioxide layer 13a is removed by wet etching with diluted 10% hydrofluoric acid to selectively etch the silicon dioxide layer 13a which has not been formed. The implantation of oxygen has no effect on the separation region 2. About 2 at about 1,150 ℃
When the oxygen ion implanted portion is annealed, this implanted oxygen forms the silicon dioxide region 15 in FIG. 2F.
This is about 4,000Å below the surface of the epitaxial layer 10. Next, a protective silicon dioxide layer 15a is thermally grown on the exposed surface of the epitaxial layer 10 to a thickness of about 1,500Å.

Next, the structure shown in FIG. 2F is implanted with boron ions having an energy of about 50 kiloelectron volts and a density of about 1E15 ions / cm ² . Then, using a phosphoric acid solution, the silicon nitride layer 13
Is removed. After that, by selective wet etching,
Alternatively, the polycrystalline silicon layer 14a is removed by, for example, selective plasma etching in a carbon tetrafluoride-oxygen plasma. Next, a second boron implant is performed at an energy of about 50 to 70 kiloelectron volts and a density of about 1E13 to 1E14 ions / cm ² . After that, a drive-in process of the boron ion implantation portion is performed to form the P + type region 16 and the P type base region 17 of FIG. 2G, and the base region is also formed on the silicon dioxide region 15. Make a structure that has a base on top of the insulator. By wet etching in a 10% hydrofluoric acid solution, the silicon dioxide layer 14 is removed while leaving a substantial portion of the silicon dioxide layer 15a. Next, an N + type region 18 is formed on the surface of the epitaxial layer 10 by implanting a suitable dopant such as phosphorous or arsenic ions to form the structure of FIG. 2H. Next, the collector diffusion 3 and the extrinsic base region 16 are formed using a known method.
Attach a contact (not shown) to. This structure limits the parasitic capacitance between the base and collector by reducing the dielectric constant at the extrinsic base-collector junction.

Figures 3A through 3D are simplified side views showing the process steps necessary to form another embodiment of the present invention. This embodiment uses a similar self-aligning method, but produces a polycrystalline silicon emitter structure. A polycrystalline silicon layer 20 is formed to a thickness of about 2,000Å by low pressure chemical reaction vapor deposition. Next, the silicon dioxide region 21 is thermally grown to a thickness of about 300Å. The silicon nitride layer 22 is formed by low pressure chemical reaction vapor deposition.
Form to a thickness of 2,000 to 3,000Å. A silicon dioxide layer 23 is formed to a thickness of about 6,000 to 8,000Å by plasma deposition or chemical reaction vapor deposition. The layers are then patterned using known methods and subjected to anisotropic etching to produce the structure shown in Figure 3A. next,
A layer of silicon dioxide (not shown) having a thickness of about 3,000Å is deposited on the surface of the epitaxial layer 10 by low pressure chemical vapor deposition. The silicon dioxide layer (not shown) is then anisotropically etched to form sidewall oxide layer 24. Next, change the structure shown in Fig. 3A to approximately 300
It is subjected to implantation of oxygen ions (O ₂ ) having an energy of kiloelectron volts and a density of about 6E17 atoms / cm ² . This ion-implanted portion is annealed to form the silicon dioxide region 15 shown in FIG. 3B. Next, sidewall oxide layer 24 and plasma oxide layer 22 are selectively etched using 10% diluted hydrofluoric acid. Next, a silicon dioxide layer 25 is formed by thermal oxidation to a thickness of about 1,500Å. The important thing is the silicon dioxide layer 21
However, it is 300 Å thinner than the thickness of the silicon dioxide layer 25.
Is to have a thickness of. Next the structure of FIG. 3B is subjected to implantation of energy and about 1E15 ions / cm ² in density of boron ions 70 keV. The silicon nitride layer 22 (FIG. 3B) is removed using an etching method that selectively removes silicon nitride without etching silicon dioxide, such as wet etching in phosphoric acid. Next, the silicon dioxide layer 21 is removed by wet etching in a 10% diluted hydrofluoric acid solution. Oxide layer during etching
Sufficient to remove 21 but is chosen to leave a substantial portion of silicon dioxide layer 25. Therefore, the polycrystalline silicon region 20 is exposed.

The structure of Figure 3C is subjected to implantation of N-type dopant ions such as boron ions having a density of energy and about 1E15 to 1E16 ions / cm ² to about 50 keV. This ion-implanted part is annealed to obtain the very shallow N + in Fig. 3D.
The mold emitter region 26 is formed and the P + type region 16 is driven in. Further, this ion implantation strongly doped the polycrystalline silicon region 20,
The specific resistance of is lowered to a negligible value. Next, boron ions are implanted at an energy of about 140 kiloelectron volts and a density of about 1E13 to 1E14 ions / cm ² , and the base regions 17 are annealed. An opening for the base contact 27 is etched into the silicon dioxide region 25 using known methods. A contact (not shown) to the collector diffusion 3 is provided by a known method.

Thus, the transistor 50 having the silicon dioxide region 15 is formed by using the self-alignment method. Silicon dioxide region 15 reduces the base-collector junction capacitance. The reason is as described above.

The present invention has the technical advantage of reducing the base-collector capacitance of a vertical bipolar transistor. This reduction in capacitance allows vertical bipolar transistors made in accordance with the present invention to operate at higher frequencies and at higher speeds when used in digital electronic circuits.

 The following section is further disclosed in connection with the above description.

(1) In a bipolar transistor having a structure having a base on an insulator, a collector region of a first conductivity type and a base region of a second conductivity type formed adjacent to the collector region. An insulator region disposed between the base region and the collector region that reduces, but does not eliminate, the interfacial area between the base region and the collector region,
A bipolar transistor having an emitter region of the first conductivity type formed in the base region, the emitter region not in contact with the collector region.

(2) The bipolar transistor according to the item (1), wherein the insulator region is a silicon dioxide region.

(3) The bipolar transistor according to the item (2), wherein the silicon dioxide region is formed by implanting oxygen into crystalline silicon.

(4) The bipolar transistor according to the item (1), wherein the first conductivity type is N-type and the second conductivity type is P-type.

(5) In a bipolar transistor having a structure having a base on an insulator, a first conductivity type substrate, a second conductivity type subcollector region formed in the substrate, and the substrate. The second conductivity type epitaxial layer formed on the surface of the substrate in contact with the sub-collector, and the first conductivity type base region formed in the epitaxial layer adjacent to the collector region. An insulator region that is disposed between the base region and the collector region and that reduces an area of an interface between the base region and the collector region but does not reduce the area; and the insulator region formed in the base region. A bipolar transistor having a second conductivity type emitter region, wherein the emitter region is not in contact with the collector region.

(6) The bipolar transistor according to the item (5), wherein the first conductivity type is P-type and the second conductivity type is N-type.

(7) The bipolar transistor according to the item (5), wherein the insulator region is a silicon dioxide region.

(8) The bipolar transistor according to the item (7), wherein the silicon dioxide region is formed by implanting oxygen into crystalline silicon.

(9) In a method of manufacturing a vertical bipolar transistor having a structure having a base on an insulator, a substrate having a first conductivity type which acts as a collector of the transistor is prepared and reacted with the substrate. Atoms forming an insulator region into the substrate to a selected depth, and dopant ions having a second conductivity type are implanted into the substrate to form a base region, A method comprising implanting ions into the substrate to form an emitter region.

(10) The method according to the item (9), wherein the first conductivity type is N type and the second conductivity type is P type.

(11) The method according to the item (9), wherein the atom is an oxygen atom.

(12) The method according to the item (9), wherein the substrate is crystalline silicon.

[Brief description of drawings]

FIG. 1 is a simplified side view showing the structure of a conventional vertical bipolar transistor, and FIGS. 2A to 2H are simplified side views showing the processing steps necessary for constructing one embodiment of the present invention.
Figures 3 through 3D are simplified side views showing the processing steps required to make another embodiment of the present invention. Explanation of main symbols 3: Collector diffusion region 15: 2 Silicon oxide region (insulator region) 16,17: P + and P type region (base region) 18,26: N + type region (emitter region)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-56-126961 (JP, A) JP-A-53-39889 (JP, A) JP-A-59-87865 (JP, A) JP-A-60- 97670 (JP, A) JP 61-234563 (JP, A)

Claims (2)

(57) [Claims] 1. A bipolar transistor having a structure having a base on an insulator, wherein a collector region of a single crystal semiconductor material of a first conductivity type and a second conductivity type formed adjacent to the collector region. A homogenous single crystal semiconductor material base region, disposed between the base region and the collector region,
An insulator region that substantially separates the entire extrinsic base from the collector and does not eliminate the interfacial area between the base region and the collector region; and the base region formed by diffusion from polycrystalline silicon. An emitter region of the first conductivity type formed therein, the emitter region not in contact with the collector region, and at an interface between the extrinsic base and the insulator region,
A bipolar transistor in which the extrinsic base substantially does not extend beyond the insulator region. 2. A method of manufacturing a vertical bipolar transistor having a structure having a base on an insulator, comprising: providing a substrate of a first conductivity type that acts as a collector of the transistor; and reacting with the substrate. Implanting atoms to form a dielectric region into the substrate to a selected depth, and forming a sidewall dielectric above the region of the substrate where the extrinsic base of the transistor is formed. , After forming the insulator region, implanting dopant ions of a second conductivity type into the substrate such that the implanted dopant ions are offset by the sidewall dielectric. By forming the base having a region, the extrinsic base actually extends beyond the insulator region at the interface between the extrinsic base and the insulator region. Qualitatively preventing it from squeezing out, and implanting ions of the first conductivity type into the substrate to form an emitter region.