JPS6097670A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the unnecessary junction part capacity by a method wherein, in the junction part region between semiconductor regions (impurity regions), insulating films are formed at the junction part regions other than the junction part region equivalent to the intrinsic region, which fulfills the original functions of the junction part region. CONSTITUTION:An N<+> type buried layer 11 is connected to an N<+> type impurity layer for leading-out a collector, which has been provided outside the diagram. This N<+> type impurity layer is provided in an epitaxial layer adjacent to an oxide film 13 at the right end of the diagram. In the junction part region, which is a boundary of a base region 14 and the epitaxial layer 12, insulating films 19 are formed at the junction part regions other than the junction part region just under an emitter region 15. The insulating films 19 are a silicon oxide film or a silicon nitriding film formed by performing an implantation of oxygen or nitrogen and a proper thermal treatment after the base region 14 was formed. As the insulating films 19 are formed at the junction part regions other than the junction part region just under the emitter region 15, which is an intrinsic region of the base region 14, the junction part capacity at the external regions other than the intrinsic region is decided by the insulating films 19. As a result, the junction part capacity is reduced to a very small one.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and, for example, to a technique that is particularly effective when used to reduce capacitance in a semiconductor device.

[Background Art] When semiconductor devices are integrated on the same semiconductor substrate, the junction capacitance of each element poses a problem in terms of speeding up. Particularly in integrated circuits, it is desirable to eliminate junction capacitance in areas other than the original active region of the device as much as possible. - As an example, a conventional typical structure of a vertical bipolar transistor (for example, Japanese Patent Application Laid-Open No. 54-67388
This unnecessary junction capacitance will be explained with reference to FIG.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate, such as a P-type impurity silicon semiconductor substrate.

On this substrate 1, an N+ type buried layer 2 and an N type epitaxial layer 3 are formed. This substrate 1 has an isolation region (
That is, the active region is divided into a region covered with a relatively thick insulating film 4) and an active region other than the region covered with the relatively thick insulating film 4. In the active area,
A P+ type impurity region 5, which is the base of the bipolar transistor, and an N+ type impurity region 6, which is the emitter. Also, an N+ type impurity region 7 for drawing out the collector is formed. Reference numeral 8 denotes an insulating protective film such as a silicon oxide film or phosphosilicate glass, and aluminum wiring for electrodes for the emitter, base, and collector is provided through this film 8.

In this kind of conventional bipolar transistor, the original function as a transistor is the N+ type impurity region (
This is achieved by the P1 type impurity region (base region) 5 and the N type epitaxial layer 3 directly under the emitter region) 6. Therefore, the base region 5 directly below the emitter region 6,
It is preferable that the external base region other than the so-called intrinsic base region be as small as possible. However, this external base region is necessary because of the need to provide contact holes in one base region 5. Therefore, in the external base area,
Junction capacitance between base region 5 and epitaxial layer 3;
The addition of the junction capacitance in the intrinsic base region is the transistor's CTC' (collector-base junction capacitance).
This caused a problem in speeding up the process.

[Object of the Invention] Therefore, an object of the present invention is to provide a technique for reducing unnecessary junction capacitance in a semiconductor device.

The novel features of the present invention for the above and other purposes are:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, an insulating film is formed in a junction region between semiconductor regions (impurity regions) constituting a semiconductor device, other than the junction region corresponding to the intrinsic region that controls the original function of the semiconductor device. As a result, the junction capacitance in areas other than the intrinsic region is determined by the capacitance of the insulating film, thereby achieving a reduction in the junction capacitance.

[Embodiment 1] Hereinafter, an embodiment in which the semiconductor device of the present invention is applied to a bipolar transistor will be described with reference to FIG.

In FIG. 2, reference numeral 10 denotes a semiconductor substrate, for example, a P-type silicon semiconductor substrate.

An N+ type buried layer 11 is formed on this substrate 10, and an N type epitaxial layer 12 which is a first semiconductor region of a first conductivity type (hereinafter referred to as an impurity region) is formed on the substrate 10.
is formed to form a semiconductor substrate. The epitaxial layer 12 is surrounded by a relatively thick silicon oxide film 13 to define the active region of the device. The oxide film 13 separates the entire surface of the semiconductor substrate into a plurality of regions. Reference numerals 14 and 15 denote P+ second impurity regions of the first conductivity type and the opposite conductivity type formed in one of the plurality of separated regions on the whole surface of the epitaxial layer 12, and a part of this region. The N4'' third impurity region is of the first conductivity type and corresponds to the base region and emitter region of the transistor, respectively.The N+ type buried layer 11 is connected to the N+ type impurity layer for extracting the collector (not shown). This N+ type impurity layer is provided in the epitaxial layer adjacent to the oxide film 13 at the right end of the figure.The reference numeral 16 is a protective insulating film such as a silicon oxide film or a phosphosilicate glass film, and the reference numerals 17 and 18 are , are contact holes for the base and emitter, respectively.Although not shown, aluminum wiring is connected to each region through the contact holes, and a final protective film is provided on this.

An insulating film 19 is formed in the junction region, which is the boundary between the base region 14 and the epitaxial layer 12, other than directly under the emitter region 15. This insulating film 19
is a silicon oxide film or a silicon nitride film formed by implanting oxygen or nitrogen and performing appropriate heat treatment after forming the base region 14. The insulating film 19 is attached to the base region 1
Since the junction capacitance of the external region other than the intrinsic region is determined by the insulating film 19, it is extremely small. Therefore, the parasitic capacitance C0o is reduced, the speed of the transistor can be increased, and power consumption can be reduced.

[Embodiment 2] FIG. 3 shows another embodiment in which the present invention is similarly applied to a bipolar transistor. In the figure, reference numeral 20 denotes a semiconductor substrate, such as a P-type silicon substrate. An N1 type buried layer 21 is formed on this substrate 2o, and an N type epitaxial layer 22, which is a first impurity region of a first conductivity type, is formed on top of the N1 type buried layer 21 to form a semiconductor base. The epitaxial layer 22 is surrounded by a relatively thick silicon oxide film 23, as in the first embodiment, and defines the active region of the device. On this epitaxial layer 22, a P+ second impurity region 24 of the first conductivity type and the opposite conductivity type and an N+ third impurity region 25 of the first conductivity type are formed, and are respectively a base region and an emitter region of the transistor. It corresponds to Reference numeral 26 is a protective insulating film such as a silicon oxide film or a phosphosilicate glass film, and 27 and 28 are contact holes for the base and emitter, respectively.

Of the junction region that is the boundary between the base region 24 and the epitaxial layer 22, the junction region other than directly under the emitter region 25 has an insulating film 29 made of, for example, a silicon oxide film.
is formed. This insulating film 29 is formed by forming the epitaxial layer 22 and further forming the silicon oxide film 23, and then thermally oxidizing the surface of the semiconductor substrate other than where the silicon oxide film 23 is provided. Thereafter, the epitaxial layer 30 is again selectively grown on the insulating film 29, the silicon oxide film 23, and the epitaxial layer 22. The epitaxial layer N30 can be formed using the epitaxial layer 22 exposed through the opening 31 provided in the insulating film 29 as a seed crystal. Note that after a polycrystalline silicon layer is deposited on the surface of the substrate by CVD, it may be formed as a single crystal according to the epitaxial layer 22 by laser annealing or the like. This selectively formed epitaxial layer 3
After introducing boron as an impurity into 0, the surface is thermally oxidized to form an oxide film 26. After this.

Emitter region 25 is formed by selectively introducing arsenic. Since the insulating film 29 is thus formed in the junction region of the external region of the base, cTo is reduced, making it possible to increase the speed of the transistor and further reduce power consumption.

In both Examples 1 and 2, the insulating films 19 and 29 are formed to reduce clo, but the manufacturing process is different. That is, in Example 1,
Although the epitaxial growth process is performed once, the insulating film 19 is formed by ion implantation. Further, in Example 2, epitaxial growth is performed again on the epitaxial layer 22, the insulating film 29, and the silicon oxide film 23, but ion implantation for forming the insulating film 29 is not necessary. Embodiment 1 is more advantageous in terms of process in that it requires fewer epitaxial growth steps.

[Effect] As explained above, in the semiconductor device of the present invention, the junction capacitance is reduced by forming an insulating film in the junction region of the external region other than the intrinsic region in the junction region. This has the effect of contributing to faster speeds and lower power consumption.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to bipolar transistors, which is the field of application which is the background of the invention, but the invention is not limited to this, for example.

It can be widely used in semiconductor integrated circuits such as diodes and resistors.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional structural diagram of a conventional bipolar transistor, FIG. 2 is a cross-sectional structural diagram showing one embodiment of a bipolar transistor in which the semiconductor device of the present invention is applied, and FIG. FIG. 12.22...First impurity region (epitaxial layer)
, 13.23... silicon oxide film, 14.24...
2nd impurity region (base region), 15.25...3rd
Impurity region/(emitter region), 19.29...Insulating film. Agent Patent Attorney Akio Takahashi Figure 1 Figure 2 Figure 3 H

Claims (1)

[Claims] 1. A first impurity region of a first conductivity type formed in an active region surrounded by an element isolation insulating film, and a first impurity region of a conductivity type opposite to the first conductivity type formed on the first impurity region. of the second impurity region, the third impurity region of the first conductivity type formed in the second impurity region, and the junction region that is the boundary between the first impurity region and the second impurity region. 1. A semiconductor device comprising an insulating film formed in a junction region other than directly under an impurity region. 2. The semiconductor device is a bipolar transistor,
Claim 1, wherein the second impurity region is a base region, the third impurity region is an emitter region, and the insulating film is located deeper than the junction between the emitter and the base. Semiconductor equipment. 3. The semiconductor device according to claim 1, wherein the insulating film formed in the junction region is thinner than the previous i-element isolation insulating film.゛