JPS60257572A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having small junction capacitance by utilizing a polycrystalline layer formed onto an insulating film as an inert region in a semiconductor element and using a single crystal layer in an opening as an active region. CONSTITUTION:Boron ions, etc. are implanted to a P type silicon substrate 1, a channel cut region 7 is shaped, and an oxide film 8 is formed onto the region 7 in thickness of 1.5mum. A desired region is bored through anisotropic etching, the ions of Sb, As, etc. are implanted, and an N<+> type buried layer 3 is shaped through treatment in a non-oxidizing atmosphere at a high temperature of approximately 1,200 deg.C. Silicon is grown selectively in an epitaxial manner. When an epitaxial growth layer 4 is superposed in thickness thicker than the thickness of the oxide film 8 at that time, a polycrystalline layer 4b grows toward the lateral direction from a single crystal growth layer 4a even on the oxide film 8, and an extent increases with the thickening of thickness. Since the polycrystalline layer shaped onto the insulating film 8 is utilized as an inert region in a semiconductor element and the single crystal layer in and on the opening is used effectively as an active region, a semiconductor device having small junction capacitance and high performance is obtained.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a method for manufacturing a half-collar device, particularly an ultra-high-speed logic L8
The present invention relates to a method of manufacturing an industrial bipolar transistor.

[Prior art]

Traditionally, bipolar transistors for ultra-high-speed logic LSIs have a structure in which elements are separated by an oxide film, such as Bell Laboratories' 0XIII structure, Fairchild Semiconductor's isoplanar ■ structure, and Siemens' OXS. Transistors with this structure are known, and if transistors with these structures are used, the device area can be reduced to about 60% compared to the conventionally widely used PN isolated transistor, and the collector-base junction area can be reduced to 40 cm. Since it can be reduced to a certain degree, the ultrahigh speed theory immediately
Applying to LSI, its degree of integration, delay direction - 9?
I[i impulse can be made very small.

Hereinafter, the above-mentioned oxide film isolated transistor f for high-speed LSI will be explained in detail according to the manufacturing process shown in FIGS. 1(a) to 1(t).

First, as shown in Figure 1(a), the concentration is relatively low (~
An oxide film (2) is grown on a P-type silicon substrate (1) of I'I cm -3), and then a part of the oxide film (2) is photographed as shown in Figure 1(b). '(, a hole is removed by plate making and etching, and then N from this opening
The sb or A8 which is to become the shaped buried layer (3) is ion-implanted, and then oxidation and drive diffusion of the implanted ions are performed as shown in FIG. 1(c).
As shown in Figure (d), the oxide film (2) is removed and an N-type epitaxial layer (4) with a relatively low concentration (~10"cm-3) is removed.
) to grow. At this time, vertical auto-doping occurs, and the effective thickness of the N- type layer located in the negative part of the N+ type buried layer (3) becomes slightly thinner than that in other regions. Next, as shown in FIG. 1(e), an underlying oxide film (5) and an oxidation-resistant insulating film (6) are formed, and elements such as transistors, etc.
wiring! The semi-dedicated head layer that should become the R-shaped layer in Figure 1: The underlying oxide film (5) of the part other than the second part of the buried layer (3).
and the oxidation-resistant insulating film (6) is removed. Thereafter, as shown in FIG. 1(f), an N-type epitaxial layer R (
4) 'c etching and further boron ion implantation to form a P-type channel cut)@*(7). Then,
As shown in FIG. 1(g), selective oxidation is performed to form an insulating oxide film (8), and the oxidation-resistant insulating film (6) and underlying oxide film (5) are removed. Next, as shown in FIG. 1() 1), areas other than the base region are covered with a resist (9), and boron ions are implanted to form a P+ type active base region aO. Similarly, as shown in Figure 1(i), P+ type inactive base @
Region (11) is formed with a higher concentration than P+ type active base region 4.

Thereafter, as shown in FIG. 1(j), the semiconductor (9) is removed, the semiconductor surface is covered with an oxide film by CVD method, and these ? Shape active base area Q! and drive diffusion of the one-legged inactive base region αJ). Then,
As shown in FIG. 1(k), a base and an emitter.

Remove the oxide film on the collector contact area, cover only the @ region that will become the base contact with resist (9),
A8 is ion-implanted from other oxide film removed regions to form N+i emitter regions 0 to N+f collector regions. Next, the above-mentioned resist is removed, and after ion implantation, As is annealed, and then the base and emitter are removed as shown in FIG.

A base electrode 0→, an emitter power supply 0υ, and a collector electrode θQ are respectively formed in the opening of the collector) (an Ibora transistor is formed).

A polar transistor with a conventional insulating film isolation structure (as shown in the figure above) has a type 1 buried layer (3), a P type channel cut region (7), and an insulating film isolation structure (8), making it possible to maintain transistors with the same size or other characteristics. The force that separates the elements of 1 et al., P−N
11i [f], the base-collector junction capacitance (
CTo) and collector substrate junction capacitance (CT8) 75
:Each~]/2. ~5/6 power can be reduced to deer;
Possible ○ However, as far as improving the Ibora structure for ultra-high speeds is concerned, it is important to further improve the frequency characteristics.

For this purpose, (ffi reduction of base resistance (rbb'), emitter-base junction capacitance (C, ) and CTCI C
Structures that result in reduced T8, narrow base width, and low collector resistance must be realized with good reproducibility.

The number of knots due to the miniaturization of transistors is as described above (D C
, , , CT, , It is expected that the transistor performance will be improved by reducing CT11 and rhb'. For example, in a transistor with a fine emitter structure of 3 x 3 μm2, cT8 = o, 05 pF,
C,, C= o, 04-TJFr CT8= 0.1
The capacitance of each part is reduced to 6pF, and the appearance;
r) It can be set to about f-2GH2, and if used in this transistor LSI, the propagation delay speed can be reduced to 0.50.
However, in the conventional transistor structure, the N+ type buried layer (3
) does not extend to the transistor's active page, that is, not only to the area directly below the emitter, but also to the base and collector lead-out contact area, otherwise isolation between elements cannot be achieved. Therefore, even in the above example, collector substrate junction capacitance (CT8) As can be seen, it occupied 64% of the capacity of one concubine, and could not be made sufficiently small. Therefore, no<i, Iira1. In aiming for high-speed HIS of sI, the conventional structure cannot be used;
Since the collector culm and plate joint volume N'r (CT) cannot be made sufficiently small, there is a limit to how high the speed can be achieved.

Furthermore, with the current photolithography technology, 3 μm is the finest and most stable level of accuracy, so if a conventional structure is made using this design standard, the shape of the base and emitter will be determined by the 3 μm rule, and the CTE + 07° will also be determined by some new technology. Unless it had a radial structure, only the above level could be achieved.

[Summary of the invention]

This invention has been made in view of the above points, and includes forming an opening 17 in an insulating film formed on a semiconductor substrate, epitaxially growing a semiconductor in this opening to a thickness equal to or greater than the thickness of the insulating film, and forming an opening 17 in an insulating film formed on a semiconductor substrate. By using the polycrystalline layer that is sometimes formed spread over an insulating film as the non-active region of the semiconductor element, and effectively using the single crystal layer inside the opening as the active region, the junction capacitance can be reduced. The present invention provides a method for obtaining a semiconductor device.

1: [Embodiment J of the Invention Figures 2(a) to (f) are cross-sectional views showing the main stages of a method according to an embodiment of the present invention. First, Figure 2(a)
As shown in the figure, a channel cut region (7) is formed by implanting ions such as boron into a P-type silicon substrate (1), and an oxide film (8) is formed thereon to a thickness of 1.5 μm.

After that, the desired area is opened by anisotropic etching,
Sb, As, etc. are ion-implanted and treated in a non-oxidizing atmosphere at a high temperature of about 1200"C to form an IJ+ type buried layer (3
) to form. Since the Ir-type buried layer (3) spreads isotropically to the edge of the opening, there is no risk of "misalignment" occurring due to mask alignment operations as in conventional methods. Next, as shown in FIG. 2(b), selective epitaxial growth of silicon is performed. The epitaxial growth layer (4) is of N type as in the conventional case. At this time, an epitaxial layer grows on the silicon, and no cracks grow on the insulating film, but when the epitaxial growth layer (4) is rolled to a thickness smaller than that of the oxide film (8), the oxide film is formed. Also on (8), a polycrystalline layer (4b) grows laterally from the single crystal growth layer (4a). The length of this lateral growth is such that when silicon moves to a stable point on the oxide film (8) and meets single crystal silicon, it stops there and grows.
The thicker the Jl of the epitaxial growth layer (4), the more the spread increases. Next, as shown in FIG. 2(c), the entire upper surface is covered with an oxide film by heating it to a high temperature in an oxidizing atmosphere. This oxide film may be deposited by CVD, sputtering, etc. Alternatively, the oxide film may be replaced by another insulating film such as a silicon nitride film. Next, the second
As shown in Figure (d), polycrystalline P (4b
) part remains with a thickness of about 30008 J
Flatten x 1fii. Polishing is 0.5μ, n8.
A sufficiently flat surface can be obtained even if the grain size is + or 7 degrees. After that, boron is implanted from the upper surface of the layers (4a) and (4b), and this is driven to form a P+ type base feeding region n, and the entire upper surface is covered with an oxide film to form the 21'J(e). Get structure. Next, as shown in FIG. 2(f), the oxide film at the part where the base and emitter are to be contacted is removed, and ions such as As are implanted only from the latter removed part to form a 14+ type emitter region 04. do. Although not shown in the drawings, electrodes are formed in the same manner as in the prior art. In this structure, the PN junction area can be made extremely small by pushing the inactive base region θ1) onto the insulating film. Since the active base area and the buried collector area of the transistor can be reduced, C1°ICT8 can be reduced to 2/3 to 1/2 of the conventional structure, and the base resistance can be lowered because the current (temporary) can be extracted from the entire circumference of the opening. High-performance transistors can be realized.

Although crystal defects were not mentioned in the above description, when selective epitaxial growth is performed, defects occur within silicon at a distance of about 1 to 1.5 μm from the edge of the oxide film. Therefore, it is desirable to adopt a method of removing defects by high-temperature annealing or the like after the step shown in FIG. 2(b) and then polishing. By performing this treatment, junction leakage can be prevented.

〔Effect of the invention〕

As explained above, in the method of the present invention, (1): an opening is formed in an insulating film formed on a semiconductor substrate, a semiconductor is epitaxially grown in this opening to a thickness equal to or greater than the thickness of the insulating film; At the time, the polycrystalline layer that is formed over the insulating crotch is used as the non-active region of the semiconductor element, and the single crystal layer inside the opening and above it is effectively used as the active region. A small, high-performance semiconductor device of 6.0 is obtained, and since there is no need for a mask alignment operation for partitioning active regions and non-active regions, there is no need to worry about mask misalignment.

[Brief explanation of the drawing]

Figures 1(a) to 2(1) are cross-sectional views showing the main stages of the manufacturing method for a semiconductor device with a conventional structure; Figure 2(1)
-(f) are sectional views showing the main stages of a method according to an embodiment of the present invention. In the figure, (1) is a semiconductor substrate, (4) is an epitaxial growth layer, (4a) is a single crystal layer, (4b) is an LD polycrystalline layer, (8) is an insulating film, σQ is an active base region, (11)
is the inactive pace @ area. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agents: Oiwa, Masuo, Figure 1, Figure 1. 1 Figure 1 Figure 2 Figure 3 Figure 2

Claims (1)

[Claims] (1) A first step of forming an insulating film on the whole surface of the semiconductor substrate, a second step of forming an opening in a desired part of the insulating film and exposing the semiconductor substrate on the bottom surface of the opening, and a second step of forming an insulating film on the entire surface of the insulating film. a third step of epitaxially growing a semiconductor to a thickness greater than or equal to the thickness of the insulating film to obtain a single crystal layer in the opening and on the half, and a polycrystalline layer on the insulating film in the vicinity thereof; and a fourth step of performing necessary processing, wherein the single crystal layer is effectively used as an active region, and the polycrystalline layer is used as an inactive region. (As the process of 21g4, heat treatment to remove defects in the single crystal layer, polishing treatment to flatten the top surface of the epitaxial growth layer and leave a thin polycrystalline layer, and treatment to introduce necessary impurities from the top surface into the single crystal layer) 2. The method of manufacturing a semiconductor device according to claim 1, wherein the active base region is formed in the polycrystalline layer and the inactive base region is formed in the polycrystalline layer.