JPH05335329A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a high performance bipolar transistor structure by farming a trench groove on a surface Si layer extending as far as the oxide film layer below it, forming an emitter area on the side wall of that trench groove, and also forming a base area which surrounds it in its side direction. CONSTITUTION:In an SOI structure, a trench groove 9 which extends as far as a lower oxide film 2 is provided an a silicon layer 3, and the side wall of that trench groove 9 is provided with an emitter area 4. As a result, the emitter area 4 is completely surrounded by a base area 5, so, the joining area other than the effective bipolar operation area is significantly reduced. In other wards, this structure, being a horizontal bipolar transistor, is equivalent to a vertical bipolar transistor formed with respect to the trench side wall, and so there is little, if any, joining area other than the effective bipolar operation region. As a result, unnecessary increase in joining capacity between the emitter and the base can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention is applied to SOI (Silicon on Silicon).
The present invention relates to a semiconductor device having a bipolar Tr structure in an insulator structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, a semiconductor device using a MOS transistor having an SOI structure has been actively developed. When the SOI structure is used, the integration degree is improved by forming a three-dimensional element,
Further, it becomes possible to manufacture a highly functionalized chip. In addition, in order to operate each MOS transistor as well, the substrate is depleted and this operation is performed, and it has been confirmed that the short channel effect can be suppressed. However, if higher speed and higher driving capability are required here, there is a limit in the MOS type transistor, and it is considered necessary to form a bipolar type transistor.

Generally, in a semiconductor device using bulk Si, a bipolar transistor having a vertical structure is used (see FIG. 4 (b)). In this bipolar transistor, the base width WB can be formed thin with good controllability, and the junction area between the emitter (E) 22 and the base (B) 21 can be limited to the size of the active region. Therefore, high performance such as high speed and high hFE (current amplification factor) can be achieved.

On the other hand, in the horizontal type, as shown in FIG. 4 (a), even if the base width WB can be formed with good controllability, an effective active area (see FIG. 4 (a) )
The solid junction arrow → indicates the current path), but the extra junction area that does not contribute to the operation between the emitter (E) 19 and the base (B) 17 is increased compared to the vertical structure. Therefore, the junction capacitance Cjn becomes large, which is a great disadvantage for high-speed driving. Further, the obliquely distributed current component as shown by the dotted arrow in FIG. 4 (a) also greatly contributes to the operation thereof, and the performance thereof is considerably reduced as compared with the vertical type.

In FIG. 4 (a), reference numeral 18 denotes the collector (C) region of the lateral bipolar transistor, and FIG.
In (b), 20 is an n-type bulk silicon substrate, and 23
Is the collector (C) region of the vertical bipolar transistor.

[0006]

Here, considering that the bipolar transistor is formed on the SOI substrate as described above, in the SOI structure, the Si layer on the oxide film is 0.1 or less.
Since it is generally as thin as μm to 0.5 μm, it is difficult to form a vertical bipolar transistor as in the case of using bulk Si.

Further, when a horizontal structure is adopted, as shown in FIG.
As shown in (b), even if the increase in the junction capacitance Cjn in the deep portion of the substrate is suppressed by making all the Si layers into a junction, the increase in the capacitance Cjnp in the periphery of the junction and the oblique current in the periphery There are defects similar to those of bulk Si, such as the generation of components (indicated by broken line arrows), and it is difficult to obtain a high performance bipolar transistor.

In FIGS. 5 (a) and 5 (b), 1 is S
A substrate of an insulator forming an OI substrate, 2 is an oxide film formed on the substrate 1, 4, 5 and 6 are emitter regions, base regions and collectors of lateral bipolar transistors formed on the Si layer on the oxide film 2. Area.

The present invention has been made to solve the above problems, and provides a semiconductor device having a high performance bipolar transistor structure in an SOI structure, and further, a semiconductor device suitable for realizing this structure. It aims at providing the manufacturing method of.

[0010]

In a semiconductor device according to the present invention, in an SOI structure, a trench groove reaching an oxide film layer therebelow is formed in a surface Si layer, and an emitter region is formed on a sidewall of the trench groove. Is provided with a base region so as to surround it from the side surface.

Also, in the method of manufacturing a semiconductor device according to the present invention, in the SOI structure, a step of providing a trench groove in the Si layer down to the oxide film layer therebelow, and a method of forming a trench groove on the sidewall of the trench groove and adhering thereto. It includes a step of depositing a silicon film and a step of diffusing impurity ions from the polysilicon layer to the Si layer to form an emitter and a base region.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-mentioned manufacturing method, conductive type impurity ions forming a base region are first formed in the Si layer from the polysilicon film adhered to the trench groove side wall of the Si layer. Then, the polysilicon film is divided into a plurality of regions, and then impurity ions of a conductivity type for forming an emitter are implanted into the polysilicon film in contact with the region to be the emitter, and then the polysilicon film is again removed from the polysilicon film. The impurity ions are diffused into the Si layer to form an emitter region.

[0013]

According to the semiconductor device of the present invention, in the SOI structure, a trench groove reaching the oxide film layer thereunder is formed in the surface Si layer, and the side wall of the trench groove surrounds the emitter region. Since the base region is provided as described above, it is possible to suppress an unnecessary increase in the junction capacitance between the emitter and the base, and further it is possible to suppress the generation of a current component in a region other than the effective active region.

Further, in the manufacturing method of the present invention, in the SOI structure, a step of forming a trench groove in the Si layer reaching the oxide film layer thereunder, and a step of depositing a polysilicon film adhered to the side wall of the trench groove. And the step of diffusing impurity ions from the polysilicon layer to the Si layer to form the emitter and base regions, a junction having a uniform base width can be obtained.

Further, in another manufacturing method of the present invention, S
From the polysilicon film adhered to the sidewall of the trench of the i layer,
First, the conductivity type impurity ions forming the base region are Si
A base region is formed by diffusing into a layer, then the polysilicon film is divided into a plurality of regions, and a conductivity type impurity ion for forming an emitter is implanted into the polysilicon film in contact with a region to be an emitter, and the polysilicon film is again implanted. Since the emitter region is formed by diffusing the impurity ions from the polysilicon film to the Si layer, it is possible to fix the base potential by providing the base electrode along the trench groove in the vicinity of the base region, which is more stable. The operation can be guaranteed.

[0016]

EXAMPLES Example 1. FIG. 1 shows a semiconductor device according to an embodiment of the present invention. 1A is a plan view of this embodiment, and FIG. 1B is a sectional view taken along the solid line I-I 'of FIG. 1A. In these figures, 1 is a substrate of an insulator that constitutes an SOI substrate, 2 is an oxide film formed on the substrate 1,
3 is a silicon layer on the oxide film 2, 4 is an emitter region provided inside the trench groove formed in the silicon layer 3,
Reference numeral 5 is a base region formed on the outside thereof, 6 is a collector region provided in a trench groove formed in the silicon layer 3, 7 is a silicon layer 3, emitter region 4, and base region 5
And an oxide film formed on the collector region 6, 8, 8 '
Is a polysilicon film, and the polysilicon film 8 is an oxide film 2
The polysilicon film 8 ′ is formed so as to cover the upper portion, the side wall of the emitter region 4, the side wall of the oxide film 7 and a part of the oxide film 7, and the polysilicon film 8 ′ is on the oxide film 2, the side wall of the collector region 6 and the side wall of the oxide film 7. The oxide film 7 is formed so as to cover a part thereof, and the polysilicon films 8 and 8'are formed so as not to contact each other on the oxide film 7.

Next, the invention of claim 1 of the present invention will be described with reference to FIGS. 1 (a) and 1 (b). According to the first aspect of the present invention, the lower oxide film 2 is formed on the silicon layer 3 in the SOI structure.
Is provided, and the emitter region 4 is provided on the side wall of the trench groove 9. By doing so, the emitter region 4 can be completely surrounded by the base region 5, and the junction area other than the effective bipolar operation region can be significantly reduced. That is, in the case of such a structure, although it is a lateral bipolar transistor, it is equivalent to forming a vertical bipolar transistor on the sidewall of the trench, and there is almost no junction area other than the effective bipolar operation region. Becomes

By the way, as shown in the sectional view of FIG. 1B, an oxide film 7 is formed on the Si layer 3 in a relatively thick film thickness. This is because the polysilicon 8 serving as the emitter electrode overlaps the emitter / base regions 4 and 5 on the upper surface of the Si layer 3 and the MOS operation is performed by the three members of the Si layer, the oxide film and the polysilicon. This is to prevent it from happening.

As is clear from FIGS. 1 (a) and 1 (b) above, in order to obtain a high-performance structure of the invention according to claim 1 of the present invention, the junction of the emitter regions is almost It is necessary to form a base region having a uniform width with a uniform width.

Example 2. The invention of claim 2 of the present invention is for satisfying this requirement, and is shown in FIG.
The invention of claim 2 will be described with reference to (f). First, an SOI substrate including the substrate 1, the oxide film 2 and the Si layer 3 is prepared (FIG. 2 (a)), the oxide film 7 is provided on the surface of the Si layer 3, and the trenches 9 are formed using the resist 24 as a mask. Dig (Fig. 2 (b)). Here, the oxide film 7 may be a thermal oxide film formed by thermally oxidizing the Si layer 3, or may be formed by deposition. However, this oxide film 7 is
As described above, it is necessary to prepare a material having a thickness that hinders the MOS operation in the base region 5.

Next, the polysilicon film 8 (8 ') is patterned in close contact with the side wall (consisting of 7 and 3) of the trench groove 9 (FIG. 2 (c)).

Next, in the polysilicon film 8 (8 '), conductive type impurity ions A for forming an emitter (collector) are formed.
Inject s + (Fig. 2 (d)).

Subsequently, using the resist 24 as a mask, only the polysilicon film 8 to be the emitter electrode is doped with conductive type impurity ions for forming a base region, in this case B + (FIG. 2 (e)).

Thereafter, lamp annealing is performed to remove the polysilicon film 8 from the trench sidewalls (7, 3).
Impurity ions As @ + and B @ + are diffused into and are activated to form a base region 5 and an emitter region 4.

Further, by performing this lamp anneal, etc., the polysilicon film 8'is removed from the trench sidewalls (7, 3).
Impurity ions As @ + are diffused into and are activated to form collector region 6.

In the above embodiment shown in FIG. 2, since an example of an npn type transistor is shown, an n type region (emitter, emitter,
Arsenic is implanted in the collector and boron is implanted in the p-type region (base). Thus, if impurity ions are selected, S
Since the diffusion coefficient at i is larger in boron than in arsenic, the n-layer 4 in the emitter region is as shown in FIG. 2 (f).
It can be completely covered by the p-layer 5 of the base. Further, since these impurities are uniformly diffused from the side wall, the base width WB becomes uniform. In view of the purpose of improving this uniformity,
It is desirable that the side wall of the trench groove 9 be formed as perpendicular to the lower oxide film layer 2 as possible.

After that, a region covering the polysilicon film 8 and the emitter region 4 is framed with an oxide film, and a contact is opened from a portion on the base region 5 to provide a base electrode in contact with the base region 5. Thus, a lateral bipolar transistor can be obtained. However, some caution is required when providing this base electrode. This point will be described below with reference to FIGS. 3 (a) and 3 (b) showing the region surrounded by the solid line II in FIG.

According to the second aspect of the present invention, the spread of the junction between boron and arsenic diffused from the polysilicon film 8 is formed only by the difference in the diffusion coefficient to Si. Therefore, it is considered to be difficult in terms of size to provide a base electrode in this base junction portion (width of the portion in contact with the trench side wall of the base region 5 in FIG. 3 (a)), as shown in FIG. 3 (a). As described above, it is considered necessary to expand (5 ') the p + region of the base by injecting p-type ions into the trench sidewall of the Si layer 3 using the polysilicon film 8 as a mask and diffusing the ions. In Figure 3 (a),
5 is a base region by diffusion from the polysilicon film 8,
Reference numeral 5'denotes a base junction expanded by implanting p-type ions into the side wall of the Si layer 3).

However, the p + implantation compensates the n + region 4 of the emitter (n-type ions are reduced by p-type ions), and the n-type region 4 is formed near the edge of the polysilicon film 8 serving as the emitter electrode. Invert part of p. Here, as shown in FIG. 3B, if the n + region 4 recedes to a region where the emitter electrode 8 is in contact with the trench side wall, the emitter electrode 8 may short-circuit with the base region 5. Become.

The invention according to claim 3 of the present invention has been made to solve such a problem, and a base electrode is provided near the base region along the side wall of the trench to stabilize the base potential with a low resistance. It was designed to be able to be taken.

Example 3. The manufacturing method according to claim 3 of the present invention will be described below with reference to FIGS. 6 (a) to 6 (g).

First, in the same manner as described in the second aspect of the present invention, a trench groove is formed in the side wall of the silicon layer 3 and the oxide film 7 (the sectional view of FIG. 6 (a), FIG. (b) Plan view).

Then, polysilicon electrodes 30 and 30 'are formed in close contact with the sidewalls of the trenches in the regions to be the emitter and collector (FIG. 6C).

Next, boron, which is a p-type ion, is implanted into these polysilicon electrodes 30, and arsenic, which is an n-type ion, is implanted into the polysilicon electrode 30 ', and impurity ions are implanted from these polysilicon electrodes 30, 30' by lamp annealing or the like. B
+ And As + are diffused in the silicon layer 3 and activated to form the base portion 5 and the collector portion 6 (FIG. 6 (d)).

Next, the polysilicon electrode on the emitter side is
Patterning is performed on the base electrode 30 and the emitter electrode 30 ″ (FIG. 6 (e)).

Next, in this divided polysilicon electrode group, arsenic serving as an emitter and boron serving as a base are implanted only in a region serving as an emitter electrode 30 ", if necessary to secure a base width. A region 31 of 6 (f) shows a resist opening at the time of this implantation.

After that, lamp annealing is performed again to diffuse and activate n-type arsenic and p-type boron from the emitter electrode 30 ″ to form the emitter region 4 and the base region 5, thereby forming the bipolar region. A transistor can be obtained (Fig. 6 (g)).

According to the method of this embodiment as described above, the base electrode 30 can be formed without performing ion implantation in a later step, and a short circuit between the emitter 30 ″ electrode and the base can be suppressed. Further, since the base electrode 30 can be provided near the emitter junction 4 and the base junction 5 along the side wall of the trench, it is possible to stably take the base potential with low resistance.

[0039]

As described above, according to the semiconductor device of the present invention, in the SOI structure, the trench groove reaching the lower oxide film layer is formed in the Si layer on the surface, and the sidewall of the trench groove is formed. Since the structure is provided with the emitter region, it is possible to obtain a lateral bipolar transistor that can suppress an unnecessary increase in the junction capacitance between the emitter and the base and further suppress the generation of a current component outside the effective active region. Be done.

Further, according to the manufacturing method of the present invention, in the SOI structure, a step of forming a trench groove reaching the lower oxide film layer in the Si substrate, and a polysilicon film adhered to the sidewall of the trench groove are deposited. And a step of diffusing impurity ions from the polysilicon layer to the Si layer to form the emitter and base regions,
Since the impurity ions forming the emitter / base are diffused into the Si layer from the polysilicon film adhered to the side wall of the trench groove, a lateral bipolar transistor having a uniform base width can be obtained.

Furthermore, according to the manufacturing method of the present invention, a polysilicon film is formed in a region to be an emitter / base, impurity ions of the same conductivity type as the base are diffused from the polysilicon film, and the polysilicon film is used as an emitter.・ Since it is divided into base electrodes, impurity ions necessary for emitter formation are injected into the emitter electrode, and these impurity ions are diffused again into the silicon layer, so that short circuit with the base of the emitter electrode is prevented and low resistance is achieved. A base electrode can be provided on the.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a method of manufacturing a semiconductor device according to an embodiment of the invention of claim 2;

FIG. 3 is a diagram showing a defect in forming a base electrode in the semiconductor device according to the first embodiment of the invention.

FIG. 4 is a simple structural diagram of a conventional bipolar transistor.

FIG. 5 is a structural diagram of a lateral bipolar transistor having an SOI structure.

FIG. 6 is a diagram showing a method of manufacturing a semiconductor device according to an embodiment of the invention of claim 3;

[Explanation of symbols]

 1 substrate 2 oxide film 3 Si layer 4 emitter region 5 base region 6 collector region 7 oxide film 8 emitter electrode 17 base region 18 collector region 19 emitter region 21 base region 22 emitter region 23 collector region

Claims (3)

[Claims] 1. In a bipolar transistor semiconductor device formed on an SOI (Silicon on Insulator) substrate, a trench groove reaching the lower oxide film layer is formed in a Si layer on the surface, and an emitter region is formed on a sidewall of the trench groove. However, the semiconductor device is characterized in that a region is provided so as to surround the side face. 2. The method for manufacturing a bipolar transistor according to claim 1, wherein a step of forming a trench groove in the surface Si layer reaching the lower oxide film layer, and forming a trench groove in the sidewall of the trench groove of the Si layer. Manufacturing a semiconductor device, comprising: forming a contacting conductive film layer; and diffusing impurity ions from the conductive film layer to trench sidewalls of the Si layer to form a base region and an emitter region. Method. 3. The method of manufacturing a bipolar transistor according to claim 1, wherein a step of forming a trench groove in the surface Si layer reaching the lower oxide film layer, and a step of forming a trench groove in the sidewall of the trench groove of the Si layer. Forming a contacting conductive film layer, diffusing first conductive type impurity ions forming a base region from the conductive film layer into a trench sidewall of the Si layer, and forming the conductive film layer into a plurality of regions. And a step of diffusing second-conductivity-type impurity ions that form an emitter region in the side wall of the trench groove of the Si layer from the conductive film layer serving as an emitter electrode in the divided conductive film layer. A method of manufacturing a semiconductor device, comprising: