JP2646856B2 - Manufacturing method of bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a bipolar transistor.

[0002]

2. Description of the Related Art Generally, a bipolar transistor is
The switching speed is determined by the cutoff frequency f _{T, the} collector-base junction capacitance, and the like. Expressing this cutoff frequency f _T as the carrier transit time, it is expressed by equation (1).

[0003]

In equation (1), τ _e is dominant in a low current region, and τ _b is dominant in a high current region.

FIG. 7 is a sectional view showing a first example of a conventional bipolar transistor, and FIG. 8 is a view showing an impurity concentration distribution from point E to point F in FIG.

As shown in FIG. 7, high-concentration N-type (N ⁺ type)
The collector region 51 is formed on a semiconductor substrate (not shown), and the low-concentration N-type (N ⁻ ) collector region 52 is formed on the high-concentration N-type collector region 51. Next, P
The base region 53 is selectively formed on the surface of the low concentration N-type collector region 52, and the N-type emitter region 54 is formed selectively on the surface of the P-type base region 53. An insulating film 55 is formed on the surface including the N-type emitter region 54, and the insulating film 55 on the P-type base region 53 and the N-type emitter region 54 is selectively opened. Furthermore, the P-type base region 53 and the N-type
A base electrode 57 and an emitter electrode 56 are selectively formed in the opening on the mold emitter region 54 and the edge thereof, respectively. The impurity concentration from point E to point F of the conventional bipolar transistor thus configured is distributed as shown in FIG.

As described above, the high concentration N-type collector region 51
The impurity concentration of the low-concentration N-type collector region 52 between the P-type base region 53 and the P-type base region 53 is as low as 5 × 10 ¹⁵ (1 × 10 ^{15 to} 5 × 10 ¹⁵ cm ⁻³ ) per cubic cm. Therefore, in the high current region, a large amount of electrons are injected into the depletion layer of the base-collector junction and neutralize the charge.
Holes are injected from the base electrode 57. Then, the width of the depletion layer at the base-collector junction is reduced, and the electric field in the depletion layer converges. Then, the holes are introduced to the low-concentration N-type collector region 52, and the base width of the P-type base region 53 becomes as if it were enlarged. Further, the minority carriers accumulated in the base region become slower in proportion to the square of the base width, so that the time constant τ _{b of the} minority carriers accumulated in the base region increases. For this reason, there is a drawback that the cutoff frequency f _T is lowered, and the switching speed of the bipolar transistor is greatly reduced. Generally, this phenomenon is called a Kirk effect.

In order to prevent the influence of the Kirk effect,
A bipolar transistor as shown in FIG. 9 has been proposed. As shown in FIG. 9, first, a high-concentration N-type collector region 51 is formed on a semiconductor substrate. Next, the low-concentration N is deposited on the high-concentration N-type collector region 51 by epitaxial growth.
The mold collector region 52 is grown. Immediately below the region where the emitter is to be formed, a high-energy pentavalent N-type impurity, for example, phosphorus is ion-implanted from the surface of the substrate to locally increase the impurity concentration on the surface of the low-concentration N-type collector region 52. A concentration N-type impurity region 58 is formed. Next, a P-type base region 53 is selectively formed on the surface of the low-concentration N-type collector region 52 including the upper half of the medium-concentration N-type impurity region 58. Further, an N-type emitter region 54 is selectively formed on the surface of the P-type base region 53 immediately above the medium-concentration N-type impurity region 58.

When this bipolar transistor is operated in a high current region, the P-type base region 53 generated by injection of holes from the base electrode 57 expands due to the presence of the medium concentration N-type impurity region 58. Is suppressed.
As described above, the bipolar transistor having the medium-concentration N-type impurity region 58 is manufactured by ion-implanting N-type impurities with high energy from the substrate surface.

[0010]

However, in the above-described conventional method for manufacturing a bipolar transistor, a high energy (200 to 400 ke) is applied from the surface of the semiconductor substrate.
Since a pentavalent impurity such as phosphorus is ion-implanted in V), a large crystal disorder is generated in the active region, and the disorder is not recovered by heat treatment. For this reason, there is a problem that the bipolar transistor is left with damage or crystal defects are generated, the base-collector junction breakdown voltage and the collector-emitter breakdown voltage are deteriorated, and the reliability of the bipolar transistor is reduced.

It is an object of the present invention to provide a method of manufacturing a bipolar transistor in which the switching speed is improved by suppressing the spread of the base region without causing crystal disorder in the active region.

[0012]

According to the method of manufacturing a bipolar transistor of the present invention, a step of forming a high-concentration impurity collector region of one conductivity type on a semiconductor substrate, and a step of forming one conductivity type on the high-concentration impurity collector region by epitaxial growth. Forming a low-concentration impurity collector region of a negative conductivity type ; and forming a high-concentration impurity of a reverse conductivity type on the low-concentration impurity collector region.
Forming a polycrystalline silicon layer and forming said polycrystalline silicon layer and the selectively and sequentially etched away top of the low concentration impurity collector region opening, after which the opening wherein by diffusing opposite conductivity type impurities into the low concentration impurity collector region from said polycrystalline silicon layer by heat treatment while introducing opposite conductivity type impurity in the low concentration impurity collector region, said opening subordinates
The active base region, the surrounding polycrystalline silicon layer
The higher concentration impurity collector than the lower peripheral base region.
Forming a base region having a configuration close to the region, forming a side wall only on the side surface of the opening, and introducing one conductivity type impurity into the surface of the active base region using the side wall as a mask. Yes and forming an emitter region
I do .

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 to 3 are sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, a high concentration N-type collector region 1 containing antimony or arsenic as an impurity is formed on a semiconductor substrate (not shown). Next, a low concentration N-type collector region 2 is formed to a thickness of 1 μm on the high concentration N-type collector region 1 by an epitaxial growth method.

Next, as shown in FIG. 1B, a polycrystalline silicon layer 3 is deposited on the low-concentration N-type collector region 2 by a CVD method, and a P-type impurity such as boron is highly concentrated. It is introduced into the crystalline silicon layer 3. In this case, a P-type impurity may be introduced during the growth of the polycrystalline silicon layer 3, or may be introduced by ion implantation or diffusion after the polycrystalline silicon layer 3 is deposited. Next, the first insulating film 4 is formed to a thickness of 0.2 to 0.3 μm by a thermal oxidation method or a CVD method.

Next, as shown in FIG. 1C, the upper portions of the insulating film 4, the P-type polycrystalline silicon layer 3, and the low-concentration N-type collector region 2 are selectively etched and sequentially removed to form an opening. The part 5 is formed. At this time, the reactive ion
First, the insulating film 4 is etched using a photoresist film as a mask by an etch (hereinafter referred to as RIE) method, and then the gas type is changed to SF ₆ -based gas to form the P-type polycrystalline silicon layer 3 The upper portion of the N-type collector region 2 is sequentially etched, and 0.
An opening 5 having a depth of 3 to 0.5 μm is formed.

Next, as shown in FIG. 1D, a P-type impurity such as boron is introduced into the low-concentration N-type collector region 2 of the opening 5 by diffusion or ion implantation using the insulating film 4 as a mask. I do. Here, a silicon oxide film having a thickness of 50 nm is formed on the surface of the low-concentration N-type collector region 2 in the opening 5 and on the surface of the exposed high-concentration P-type polycrystalline silicon layer 3, and then ion-implanted. P-type impurities may be introduced by a method. Next, a P-type impurity is diffused from the high-concentration P-type polycrystalline silicon layer 3 to the low-concentration N-type collector region 2 by performing a heat treatment to form a P-type base region 6.
Is diffused to a desired depth to form a P-type active base region 6a.

Next, as shown in FIG.
The second insulating film 7 is deposited on the surface including the by the CVD method.

Next, as shown in FIG. 2B, the entire surface is etched back by the RIE method to form a side wall 7a while leaving the insulating film 7 only on the side surface of the opening 5. Here, the structure of the insulating film 4 is a three-layer structure of a silicon oxide film, a polycrystalline silicon layer, and a silicon nitride film from below, and the silicon nitride film is used as a stopper when etching the low concentration N-type collector region 2 in the previous process. The second polycrystalline silicon layer can be used as a stopper when the entire surface of the insulating film 7 is etched.

Next, as shown in FIG.
A polycrystalline silicon layer 8 is deposited on the surface containing the GaN by CVD, and N-type impurities such as arsenic and antimony are introduced into the polycrystalline silicon layer 8 by ion implantation. Next, a heat treatment is performed to convert the polycrystalline silicon layer 8 into a P-type active base region 6a.
Is diffused into the surface of the substrate to form an N-type emitter region 9.

Next, as shown in FIG. 3, an aluminum layer is deposited on the polysilicon layer 8, and the aluminum layer and the polysilicon layer 8 are selectively etched to form an emitter electrode 10.

In this embodiment, a part of the low-concentration N-type collector region 2 in the emitter formation region is etched from the upper surface, and a P-type active layer base region 6a and an N-type emitter region 9 are formed in that portion. High concentration N-type collector region 1
The impurity which has risen into the low-concentration N-type collector region 2 from the high-concentration N-type collector region 1 is arranged in the transition region having a concentration gradient. By arranging the transition region having the concentration gradient immediately below the N-type emitter region 9, the switching speed of the bipolar transistor can be improved. In this case, the transition region having a concentration gradient, since it is formed only immediately below the N-type emitter region 9, it is possible to improve the cutoff frequency f _T without hardly increasing the collector-base junction capacitance.

FIG. 4 is a diagram showing the impurity concentration distribution from point A to point B in FIG. 3, and FIG. 5 is a diagram showing the impurity concentration distribution from point C to point D in FIG.

As shown in FIG. 5, in the region immediately below the peripheral base region, the low-concentration N-type collector region 2 between the P-type base region 6 and the high-concentration N-type collector region 1 is The impurity concentration is sufficiently reduced by the concentration gradient from, and the region reaches a uniform impurity concentration.

On the other hand, as shown in FIG.
In the region immediately below, a part of the low-concentration N-type collector region 2 is etched away from the surface, so that the low-concentration N-type collector region 2 between the P-type base region 6a and the high-concentration N-type collector region 1 In the inclined region where the impurity concentration decreases due to the concentration gradient from the high concentration N-type collector region 1. Usually, the concentration of the low-concentration N-type collector region 2 bonded to the P-type active base region 6a is set to 10 16 per cubic cm in consideration of the speed-up due to the Kirk effect and the speed-down due to the increase in the collector-base junction capacitance. 10 to 17
Exponentiation is desirable.

[0027] FIG. 6 is a characteristic diagram showing the relationship between the collector current I _c and the cut-off frequency f _T of the bipolar transistor of a conventional bipolar transistor and the present invention.

As shown in FIG. 6, the characteristic curve B according to the embodiment of the present invention has a cutoff frequency f _{T of the} bipolar transistor higher on the high current side than the characteristic curve A of the conventional example, and the switching speed is lower. You can see that it is improving.

[0029]

As described above, according to the present invention, the active base region and the emitter region are formed in a self-aligned manner by removing the low-concentration collector region of the emitter forming region by etching, thereby suppressing the crystal disorder of the active region. Since the active base region can be arranged in the transition region having the concentration gradient from the high-concentration collector region without occurrence, a bipolar transistor having an improved switching speed by suppressing the spread of the base region in the high-current region is manufactured. It has the effect of being able to.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor chip shown in a process order for describing one embodiment of the present invention.

FIG. 4 is a diagram showing an impurity concentration distribution from point A to point B in FIG. 3;

FIG. 5 is a diagram showing an impurity concentration distribution from point C to point D in FIG. 3;

FIG. 6 is a characteristic diagram showing a relationship between a collector current and a cutoff frequency of a conventional bipolar transistor and a bipolar transistor of the present invention.

FIG. 7 is a cross-sectional view of a semiconductor chip showing a first example of a conventional bipolar transistor.

8 is a diagram showing an impurity concentration distribution from point E to point F in FIG. 7;

FIG. 9 is a cross-sectional view of a semiconductor chip showing a second example of a conventional bipolar transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 High concentration N type collector region 2 Low concentration N type collector region 3 Polycrystalline silicon layer 4 Insulating film 5 Opening 6 P type base region 6a P type active base region 7 Insulating film 7a Side wall 8 Polycrystalline silicon layer 9 N type Emitter region 10 Emitter electrode

Claims (1)

(57) [Claims] A step of forming a one-conductivity-type high-concentration impurity collector region on a semiconductor substrate; a step of forming a one-conductivity-type low-concentration impurity collector region on the high-concentration impurity collector region by epitaxial growth; Forming a polycrystalline silicon layer containing a high-concentration impurity of the opposite conductivity type on the low-concentration impurity collector region, and selectively removing the polycrystalline silicon layer and the upper portion of the low-concentration impurity collector region by sequentially etching them; forming an opening, deer
After that, a reverse conductivity type impurity is introduced into the low concentration impurity collector region of the opening, and a reverse conductivity type impurity is diffused from the polycrystalline silicon layer to the low concentration impurity collector region by heat treatment. Active
Source region is located under the polycrystalline silicon layer.
Closer to the high concentration impurity collector region than the base region
Forming a base region having a structure based on the above structure, forming a side wall only on the side surface of the opening, and introducing an impurity of one conductivity type into the surface of the active base region using the side wall as a mask. Forming a bipolar transistor.