JP2646872B2 - Manufacturing method of bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a bipolar transistor.

[0002]

BACKGROUND ART Generally, bipolar transistor, the cutoff frequency f _T and the collection-database junction capacitance C _JC like, its switching speed is determined. If the cutoff frequency f _T is expressed as a carrier traveling time, it is expressed by the following equation (1).

1 / (2πf _T ) = τ _e + τ _b + τ _x + τ _c (1) where τ _e is a charge / discharge time constant of the emitter-base junction, τ
_b is the time constant of the minority carrier accumulated in the base region, τ
_x is time of carriers traveling collector depletion layer, the tau _c is the charge and discharge time constant of the base-collector depletion layer. In addition,
In the equation (1), τ _e is dominant in the low current region, and τ _b is dominant in the high current region.

FIG. 4A is a cross-sectional view of an example of a conventional bipolar transistor, and FIG. 4B is a diagram showing an impurity concentration distribution along a line passing through points E and F in FIG. 4A. .

As shown in FIG. 4A, an N ⁺ -type collector region 51 having a high concentration of N-type impurities is formed on a semiconductor substrate, and has a low concentration of N-type impurities thereon by an epitaxial method. An N ⁻ type collector region 52 is formed. P-type base region 53 is selectively formed on the surface of N ⁻ -type collector region 52, and N-type emitter region 54 is selectively formed on the surface of P-type base region 53. An insulating film 55 and a base electrode 57 and an emitter electrode 56 are formed on the surface of the semiconductor substrate so as to fill an opening selectively formed in the insulating film 55.

In the conventional bipolar transistor configured as described above, the P-type or N-type impurity concentration of each active region is distributed as shown in FIG. That is, the impurity of the N ⁻ type collector region 52 between the N ⁺ type collector region 51 and the P type base region 53 is 1 × 10 ¹⁵ to
Since the concentration is as low as 5 × 10 ¹⁵ cm ⁻³ , in the high current region, a large amount of electrons are injected into the depletion layer of the base-collector junction, and holes are removed from the base electrode 57 so as to neutralize the charge. Is injected. Then, the width of the depletion layer at the base-collector junction becomes narrow, and the electric field in the depletion layer converges. Then, the holes are introduced to the N ⁻ -type collector region 52, and the base width of the P-type base region 53 becomes as if it were enlarged. Further, the minority carriers accumulated in the base region become slower in proportion to the square of the base width, so that the time constant τ _{b of the} minority carriers accumulated in the base region increases. For this reason, there is a disadvantage that f _T is reduced and the switching speed of the bipolar transistor is greatly reduced. Generally, this phenomenon is called a Kirk effect.

In order to prevent the influence of the Kirk effect, a bipolar transistor as shown in FIG. 5 has been proposed. That is, as shown in FIG. 5, after an N ⁺ -type collector region 51 and an N ⁻ -type collector region 52 are formed on a semiconductor substrate, pentavalent with a high energy of 200 to 400 KeV and a valence of 200 to 400 KeV immediately below the region where an emitter is to be formed. Then, an N-type impurity, for example, phosphorus is ion-implanted to locally increase the impurity concentration on the surface of the N ⁻ -type collector region 52 to form an N-type impurity region 58 having a medium concentration. Then, a P-type base region 53 is selectively formed on the surface of N ⁻ -type collector region 52 including the upper half of N-type impurity region 58, and an N-type emitter region 54 is selectively formed on the surface of P-type base region 53. Things.

With this configuration, the P-type or N-type impurity concentration of each active region is distributed as shown in FIG. For this reason, when this bipolar transistor is operated in a high current region, this medium concentration N
The presence of the type impurity region 58 suppresses the spread of the P-type base region 53 generated by injection of holes from the base electrode 57.

[0009]

However, in the above-mentioned conventional method for manufacturing a bipolar transistor, a high energy phosphorous or the like is removed from the surface of the semiconductor substrate.
Due to ion implantation of a valence impurity, large crystal disorder occurs in the active region. The disorder of the crystal is not recovered by the heat treatment. For this reason, there is a problem that the bipolar transistor is damaged and crystal defects occur, the base-collector junction breakdown voltage and the collector-emitter breakdown voltage are degraded, and the manufacturing yield of the bipolar transistor is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is possible to improve the switching speed by suppressing the spread of the base region, and to improve the crystallinity and the production yield of the bipolar transistor. It is intended to provide a manufacturing method.

[0011]

A method of manufacturing a bipolar transistor according to the present invention comprises the steps of forming a first conductivity type high concentration impurity collector region on a semiconductor substrate, and forming the first conductivity type high concentration impurity collector region on the high concentration impurity collector region by epitaxial growth. Forming a first-conductivity-type low-concentration impurity collector region; and sequentially forming a second-conductivity-type high-concentration impurity polycrystalline silicon layer and a first insulating film on the low-concentration impurity collector region. A step of patterning the first insulating film and the polycrystalline silicon layer to form an opening, and then introducing a second conductivity type impurity into the low concentration impurity collector region in the opening; A second conductivity type impurity in the layer is diffused into the low concentration impurity collector region to form a base region, and then a second insulating film is formed on a side wall of the opening. Forming a side wall, said from the base region to the bottom of the groove by introducing second conductivity type impurities after the sidewall as a mask to form a part is removed groove of the low-concentration collector region High
Forming an active base region close to the concentration impurity collector region ; and introducing an impurity of a first conductivity type into the active base region from the trench to form an emitter region.

[0012]

According to the present invention, after forming a polycrystalline silicon film and an insulating film on the low concentration impurity collector region, the insulating film and the polycrystalline silicon film are removed from the upper surface of a desired portion.
Further, a part of the low-concentration impurity collector region is removed, and an active base region and an emitter region are formed immediately below by self-alignment. Therefore, the active base region rises from the high-concentration impurity collector region to the low-concentration impurity region, and is arranged in the transition region having the concentration gradient from the high-concentration impurity collector region side. By suppressing the expansion of the region, the switching speed of the bipolar transistor can be further increased. Further, since a high energy ion implantation step is not required, damage to the bipolar transistor and crystal defects can be prevented.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, an N ⁺ -type collector region 1 containing, for example, antimony or arsenic as an impurity is formed on a semiconductor substrate such as silicon. Next, an N ⁻ type collector region 2 is formed on the N ⁺ type collector region 1 by epitaxial growth. Next, a polycrystalline silicon film is deposited on the N ⁻ -type collector region 2 by the CVD method, and then a P-type impurity such as boron is introduced at a high concentration to form a P ⁺ -type polycrystalline silicon film 3. In this case, a P-type impurity may be introduced during the growth of the polycrystalline silicon film, or the impurity may be introduced by ion implantation or diffusion after depositing the polycrystalline silicon film.

Next, a first insulating film 4 made of a silicon oxide film is formed on the entire surface by a thermal oxidation method or a CVD method. In this case, an insulating film is laminated and used in a later step in order to use a part of the N ⁻ type collector region by etching and to use as an etching stopper when forming a sidewall made of an insulating film on the side wall thereof. You may. For example, a film such as a silicon oxide film, a silicon nitride film, and a polycrystalline silicon is laminated and used. The thickness of this insulating film is about 20
0 to 300 nm.

Next, an opening 5 is formed by removing the first insulating film 4 and the P ⁺ -type polycrystalline silicon 3 at desired locations by photolithography. In this case, the first insulating film 4 is first etched using a photoresist film as a mask by reactive ion etching (RIE), and then the gas type is changed to SF ₆ -based gas to form a P ⁺ -type polycrystal. The silicon film 3 is etched to expose the N ⁻ type collector region 2. In this case, the etching is performed so that a part of the P ⁺ -type polycrystalline silicon film 3 slightly remains, and thereafter, the remaining P ⁺ -type polycrystalline silicon film is etched by an HF wet etching method having a selectivity depending on the impurity concentration. Should be removed.

Next, as shown in FIG. 1B, an N ^- type collector region in the opening 5 is formed by diffusion or ion implantation using a P-type impurity such as boron as a mask with the first insulating film 4 as a mask. 2 to the exposed part. In this case, the exposed surface of the N ⁻ -type collector region 2 and the surface and side surfaces of the P-type polycrystalline silicon film 3 are preferably oxidized thinly (about 50 nm), and then P-type impurities are introduced by ion implantation. Next, P-type impurities are diffused from P ⁺ -type polycrystalline silicon film 3 to N ⁻ -type collector region 2 by performing a heat treatment. Next, a second insulating film 7 made of a silicon oxide film or the like is deposited on the entire surface by the CVD method.

Next, as shown in FIG. 1C, the second insulating film 7 is etched by the RIE method to form a sidewall 7A made of the second insulating film 7 on the side wall in the opening 5.
In this case, the first insulating film 4 serves as a stopper for this etching. Next, the P-type base region 6 exposed from the opening narrowed by the sidewall 7A is removed by etching using an RIE method using an SF ₆ -based gas to form a groove 5A. For example, N grown by epitaxial growth
Assuming that the film thickness of the ⁻ type collector region 2 is 1 μm,
Etching is preferably performed at 0.3 to 0.5 μm.

Next, as shown in FIG.
P-type impurities such as boron are first implanted by ion implantation.
Using the insulating film 4 and the sidewall 7A as a mask, the groove 5 is formed.
A to form a P-type active base region 6A. In this case, the exposed silicon surface may be oxidized thinly (about 50 nm), and then a P-type impurity may be introduced by ion implantation. Next, a polycrystalline silicon film is deposited by a CVD method, and an N-type impurity such as arsenic or antimony is introduced by an ion implantation method to form an N ⁺ -type polycrystalline silicon film 8. Next, heat treatment is performed to form an N-type emitter region 9.

As shown in FIG. 2A, a metal such as aluminum is deposited on the emitter region, and an emitter electrode 10 is formed by a photolithography process.

In this embodiment, a portion of the N ⁻ type collector region 2 immediately below the emitter forming region is etched from the upper surface to form a groove 5A, and a P type active base region 6A and an N type emitter region In order to form 9, the impurities rising from the N ⁺ type collector region 1 to the N ⁻ type collector region 2 are arranged in the transition region having a concentration gradient from the N ⁺ type collector region 1.

By arranging the transition region having a concentration gradient immediately below the N-type emitter region 9, the switching speed of the bipolar transistor can be improved. In this case, the transition region having a concentration gradient, since it is formed only immediately below the N-type emitter region 9, it is possible to improve the cutoff frequency f _T without hardly increasing the collector-base junction capacitance.

FIGS. 2B and 2C are views showing the impurity concentration distribution of a cross section taken along a line passing through points A and B in FIG. 2A and an impurity concentration distribution taken along a line passing through points C and D in FIG. It is a figure which shows a density distribution.

As shown in FIG. 2C, in the region immediately below the peripheral base, the N ⁻ type collector region 2 between the P type base region 6 and the N ⁺ type collector region 1 is N ⁺ type collector region 1. The impurity concentration is sufficiently reduced by the concentration gradient from
It is a region up to a uniform impurity concentration. On the other hand, in the region immediately below the emitter electrode 10, a part of the N ⁻ type collector region 2 is etched away from the surface, so that the N ⁻ type between the P type active base region 6A and the N ⁺ type collector region 1 is removed. The collector region 2 is an N ⁺ type collector region 1
This is in the slope region of the graph where the impurity concentration is decreasing due to the concentration gradient from. Normally, the impurity concentration at the junction between the P-type active base region 6A and the N ⁻ -type collector region 2 is 10 ¹⁶ to 10 ^{17 in} consideration of the speed-up due to the Kirk effect and the speed-down due to the increase in the collector-base junction capacitance.
cm ^-3 is desirable.

FIG. 3 is a diagram showing the relationship between the collector current I _C of the bipolar transistor and the cutoff frequency f _T.
The horizontal axis shows the collector current I _C , and the vertical axis shows the cutoff frequency f
Indicates _T. In FIG. 3, a line segment P is a conventional bipolar transistor shown in FIG. 4A, and a line segment Q is a line segment Q in FIG.
2 shows the relationship between the collector current I _C and the cutoff frequency f _{T of} the self-aligned bipolar transistor shown in FIG.

As is clear from FIG. 3, in this embodiment, the cutoff frequency f _T of the bipolar transistor is higher on the high current side than that of the conventional bipolar transistor, and the switching speed is improved. I understand.

[0027]

As described above, according to the present invention, the active base region can be arranged in the transition region having a concentration gradient from the high concentration collector region by etching away the low concentration collector region immediately below the emitter region. Therefore, since the spread of the base region in the high current region is suppressed,
A self-aligned bipolar transistor having a much higher switching speed can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a bipolar transistor manufactured according to an example and a diagram showing a distribution of impurity concentration in a depth direction.

FIG. 3 is a diagram illustrating a relationship between a cutoff frequency and a collector current in a conventional example and an example.

FIG. 4 is a cross-sectional view of a conventional bipolar transistor and a diagram showing a distribution of impurity concentration in a depth direction.

FIG. 5 is a cross-sectional view of a conventional bipolar transistor and a diagram showing a distribution of impurity concentration in a depth direction.

[Explanation of symbols]

Reference Signs List 1 N ⁺ type collector region 2 N ⁻ type collector region 3 P ⁺ type polycrystalline silicon film 4 First insulating film 5 Opening 5A groove 6 P type base region 6A P type active base region 7 Second insulating film 7A Sidewall 8 N ⁺ type polycrystalline silicon film 9 N type emitter region 10 Emitter electrode

Claims (1)

(57) [Claims] 1. A step of forming a first conductive type high concentration impurity collector region on a semiconductor substrate, and a step of forming a first conductive type low concentration impurity collector region on the high concentration impurity collector region by an epitaxial growth method. Forming a polycrystalline silicon layer into which a second conductive type high-concentration impurity is introduced and a first insulating film on the low-concentration impurity collector region; and forming the first insulating film and the polycrystalline silicon layer. Patterning an opening to form a second conductive type impurity in the low concentration impurity collector region in the opening, and heat treating the second conductive type impurity in the polycrystalline silicon layer.
Forming a base region by diffusing a conductive impurity into the low-concentration impurity collector region, and then forming a sidewall made of a second insulating film on a side wall of the opening; After removing a portion of the trench to form a groove, a second conductivity type impurity is introduced to introduce a high concentration impurity
Forming an active base region close to the rectifier region, and introducing an impurity of a first conductivity type into the active base region from the trench to form an emitter region. .