JPH02205033A - Bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To extend the limit of the longitudinal miniaturization of a bipolar transistor and to operate at a high speed by providing an N-type impurity concentration of a protrusion of a predetermined N-type single crystalline Si, and forming part of an emitter of a hetero material except an N-type polycrystalline Si film or a crystalline Si on the N-type single crystalline Si. CONSTITUTION:After an epitaxial Si layer 3 formed with a base layer is exposed, a polycrystalline Si film is deposited, and BF2+ is implanted by ion implanting. Thereafter, an SiO2 film formed by completely oxidizing the polycrystalline Si is removed, and a base layer 4 of peak concentration 1X10<19>cm<-3> is formed. Then, an N-type epitaxial layer 8 selectively formed on an opening. Subsequently, after the P concentration is deposited on an N-type polycrystalline Si film of X10<20>cm<-3>, it is patterned by etching as a normal photolithography to form an emitter 9. An N-type fine crystalline Si film laminated by a normal plasma CVD method or a hetero material of other wire band gap may be employed instead of the N-type Polycrystalline Si film of the part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure and manufacturing method of a bipolar transistor suitable for high-speed operation.

[Conventional technology]

The known example closest to the present invention regarding bipolar transistors that do not use heteromaterials in the emitter is discussed in IEDM 87, pages 170 to 173.

Limitations due to characteristic problems when vertical miniaturization of bipolar transistors is advanced are discussed. According to this, the limit of vertical miniaturization of bipolar is (1)
(2) Increase in leakage current due to high concentration of emitter-base junction; (2) occurrence of punch-through due to reduction in base width;
(3) It is said that it is determined by the saturation of the operating speed due to the accumulation of minority carriers in the emitter.

Regarding the known example closest to the present invention regarding a bipolar transistor using a hetero material for the emitter, see IEICE Technical Research Report VoQ, 86Nα32pp29-34.
It is discussed in

In case of emitter and base or heterojunction, heterojunction and p
The position of the n-junction is shifted by an appropriate distance, that is, Si
It has been argued based on computer simulation results that forming an n-type layer as part of an emitter on a single crystal substrate can improve junction characteristics without impairing the effect of a heterojunction.

[Problem to be solved by the invention]

In the above-mentioned prior art, regardless of whether a heterogeneous material is used for the emitter or not, there are limits to vertical miniaturization due to the three problems mentioned above.

By the way, the three problems (1) to (3) mentioned above are closely related to each other. In order to prevent the punch-through described in (2) above in miniaturizing elements, it is necessary to increase the base impurity concentration. That is, if the base width is reduced without increasing the base impurity concentration, punch-through occurs between the emitter and the collector. By the way, the problem with (1) above is that the emitter impurity concentration is
(2) When the base concentration exceeds a certain level at about -8, a leakage current occurs due to tunneling between the emitter and the base. The limit concentration of this base impurity concentration is 5
It is about X 10 "an-8".

The upper limit of impurity concentration determined from (1) is 5×1018■-
8, the lower limit of the base width at which punch-through does not occur is approximately 400 people.

Furthermore, when the base concentration is increased, the impurity concentration profile of the prior art includes high concentration n-type impurities in addition to high concentration n-type impurities in the emitter of the Si single crystal portion. In that case, the band gap of the emitter portion is narrowed not only by the n-type impurity but also by the n-type impurity. In other words, when the n-type impurity concentration is below 10"an-8, gap narrowing does not occur, but when it is above it, gap narrowing occurs, and 10"an-8
9'', the bandgap becomes narrower by about 30 m e V.

In the prior art, as the base concentration increases, the bandgap becomes narrower. This causes an increase in the number of holes injected into the emitter, and even if miniaturization is advanced, the operating speed will reach saturation as described in (3).

An object of the present invention is to eliminate or improve the problems in the prior art described above, to expand the limits of vertical miniaturization of bipolar transistors, and to produce bipolar transistors that can operate at higher speeds than conventional ones.

[Means to solve the problem]

The above objective is achieved by adopting the following technical means.

First, as a first method, an emitter layer made of single crystal Si sandwiched between an n-type emitter made of polycrystalline Si or a hetero material and a p-type base is formed so that the n-type impurity is replaced with the p-type impurity as in the conventional method. Instead of being compensated by , only n-type impurities are included.

Next, as a second means, the n-type impurity concentration of the emitter layer made of the above-mentioned N-type single crystal Si is set to a value close to the solid solubility limit of about I x 10 "cxa-" as in the case of the conventional technology. Instead, it is set to about 1X10''-8 to 5X10 9am-8. Also, as the p-type impurity concentration of the base increases, this concentration is lowered.

For example, if the base concentration is 9 am-8, the base concentration is 3
10”, 6×1018cn-3 for Ca1-8
It is best to do the following.

Next, as a third means, the thickness of the emitter layer made of n-type single crystal Si is made larger than the width of the depletion layer extending toward the emitter side of the base-emitter junction and smaller than 500 nm.

The above-mentioned technical means can solve or improve the above-mentioned problems. Although each of the first to third means described above is effective when used alone, it is preferable to use the second and third means in combination. is more preferable.

[Effect]

In the emitter of the single crystal Si part in the case of the conventional technology, n
The type impurity is compensated by the p-type impurity forming the base, so the bandgap is narrower than in the case of only n-type impurities.

If the first means described above is adopted and the p-type impurity concentration of the emitter of the single crystal Si portion is set to 10"am-' or more, the extra narrowing can be achieved regardless of the p-type impurity concentration of the base. Bandgap formation can be prevented.

This suppresses hole injection into the emitter,
Accumulation of minority carriers is reduced, making it possible to prevent saturation of operating speed and reduction of current amplification factor when the device is further miniaturized in the vertical direction.

By adopting the second means and reducing the n-type impurity concentration of the emitter of the single crystal Si portion to 5 x 10"txa-a or less, the impurity concentration of the base can be reduced to 5 x 10"txa-
Even at a high concentration of 3 or more, the width of the junction depletion layer is about 120 or more, so leakage current due to carrier tunneling is suppressed. This removes the upper limit on the impurity concentration of the base, making it possible to reduce the base width without causing punch-through.

Furthermore, when the above first means is adopted, even if the emitter impurity concentration is lowered, I
If it is more than X 10"m-3, the base current increases,
That is, the current amplification factor does not decrease by +11°.First, the base current Jp is expressed by equation (1).

where Po is the equilibrium hole density in the emitter, DP is the hole diffusion constant in the emitter, and P is the x-L density gradient in the emitter.

FIG. 9 shows the relationship between Po and n-type impurity concentration at 300K. The dashed line shows the case without considering the narrow band gap phenomenon, and the solid line shows the actual case.

According to this, in the high impurity concentration region of lXl0"an-3 or higher, Po is almost dx due to the narrow bandgap. Here, Sp is the effective regeneration of minority carriers at the interface between polycrystalline Si or hetero material and single crystal Si. Binding rate, u+
q is the normalized hole concentration at the interface, and τ is the lifetime of holes in the single crystal Si emitter.

When the impurity concentration of the emitter in the single-crystal Si portion decreases, us and τ increase, and the first term on the right side of equation (2) increases and the second term decreases. When using a hetero material such as polycrystalline Si or microcrystalline Si, Sp = 100 to 30 QC!
Q/See is small and the amount of decrease in the second term is less than the amount of increase in the first term, but it does not become large. For the above reasons, even if the impurity concentration of the emitter of the single crystal Si portion is lowered, the base current Jp will not increase if it is 1.times.10.sup.18.sup.-3 or more.

Holes injected into the emitter accumulate as minority carriers in the single crystal Si portion and the polycrystalline Si or hetero material portion. Since the diffusion length of holes in heterogeneous materials such as polycrystalline Si or microcrystalline Si is less than 500 Å, hole accumulation occurs within 500 nm from the interface with single crystal Si (see FIG. 10). Therefore, in order to reduce the amount of minority carriers accumulated in the emitter and improve device characteristics, it is effective to adopt the third method described above and reduce the thickness of the emitter layer in the single crystal Si portion to 500 Å or less. (See Figure 10). As this thickness is made smaller, the amount of accumulated minority carriers decreases, and the device characteristics are improved. The presence of interface states increases emitter-base leakage current. Therefore, the thickness of the emitter layer in the single-crystal Si portion must be greater than the thickness of the portion of the base-emitter junction depletion layer extending toward the emitter side.

Also, the above 1. If the second method is adopted,
For the reasons described below, by reducing the thickness of the emitter layer in the single crystal Si portion, an increase in the base current, that is, a large decrease in the current amplification factor does not occur. Assuming that recombination in the bulk can be ignored when the emitter concentration of the single crystal Si portion is low, equation (2) becomes dx. For example, the emitter concentration of the single crystal Si part is 5×1
Considering the case where SP is 30,000 an/see in 0188 country-8, Dp is about 5 csl/see, so dx becomes dx, and the change in hole concentration in an emitter with a thickness of about 2,000 is more than 10% at most. From equations (1) and (3), Jp= −qPoSpus ・=(5
), even if the thickness of the emitter in the single crystal Si portion is reduced, the change in us, that is, Jp, will be about 10% at most, and the current amplification factor will not decrease significantly.

For the reasons stated above, by adopting the first to third means described above, it is possible to expand the limits of vertical miniaturization of bipolar transistors using conventional technology and to fabricate bipolar transistors capable of higher-speed operation. It becomes possible.

〔Example〕

A first embodiment of the present invention will be described with reference to FIGS. 1 and 2.

First, in Fig. 1, 1 is a p-type Si substrate, 2 is an n-type buried layer, 3 is an n-type epitaxial layer, 4 is a p-type single crystal Si layer, 5 and 7 are 5iOz films, and 6 is a p-type polycrystalline layer. Si film, 8 is n
The protrusions of the type epitaxial layer, 9 are n0 type polycrystalline Si films or microcrystalline Si films, and 10 are metal electrodes. 9 may be another n-type hetero material. 2 and 3 serve as collectors, 4 as a base, 6 as base extraction electrodes, and 8 and 9 as emitters, respectively.

The impurity concentration and thickness of each layer in the section taken along line AA' in FIG. 1 will be explained with reference to FIG. 2. The emitter of the part made of polycrystalline Si or a hetero material contains n-type impurities.
10 "an-", thickness 700mm, emitter of single crystal Si part has n-type impurity of 5 x 1101aa""8 (p-type impurity is less than I x 1018dl-"), thickness 30mm
0 people, the base layer has a p-type impurity peak concentration of 1 x 10 min9
(1m-”, thickness is 300 people.

According to this embodiment, the element size can be increased without causing problems such as leakage current between emitter base, punch-through between emitter and collector, relative increase in accumulation of minority carriers, and decrease in current amplification factor, which are problems in conventional technology. It becomes possible to miniaturize the device in the vertical direction, and it is possible to exceed the limit of the element operating efficiency in the conventional technology.

A second embodiment of the present invention will be described with reference to FIGS. 3 and 4. The names and functions of each part in FIG. 3 are the same as those with the same reference numerals in FIG. However, 11 is n-type S
It acts as an emitter in the i layer.

Next, the impurity concentration and thickness of each layer in the section taken along line BB' in FIG. 3 of this embodiment will be explained with reference to FIG. Polycrystalline S
The emitter 9 of the part made of i or hetero material has an n-type impurity of I x 10 "cm-" and a thickness of 700 cm, and the emitter 11 of the single-crystal Si part has a peak concentration of n-type impurity of 3 x 10 cm - 8, The peak concentration of p-type impurity is 2 x 10 '' (!! l-'', the peak of carrier concentration is I The peak concentration is 1 x 10" (m-8), and the thickness is 300 people.

According to this embodiment, the same effect as the first embodiment of the present invention is obtained, but the amount of accumulated minority carriers is reduced due to the presence of p-type impurities in the emitter of the single crystal Si portion and the degree of narrowing of the gap is large. However, the degree of improvement in the operating speed of the element is smaller than in the first embodiment. However, unlike the first embodiment, since the impurity concentration is high at the surface, each layer can be formed only by a diffusion process, which has the advantage of simplifying the manufacturing method.

A third embodiment of the present invention will be explained with reference to FIG. 11(f) and FIG. 12. The names and functions of each part in FIG. 11(f) are the same as those with the same reference numerals in FIG. However, 16 is a p-type single-crystal Si layer that serves as a graft base, and 19 is a p-type Si single-crystal layer to which 10% Ge is added and serves as a base.

Next, the impurity concentration and thickness of each layer in the section cut along c-c' in FIG. 11(f) of this embodiment will be explained with reference to FIG. The n-type and p-type impurity concentrations and thickness of each layer are
This is the same as the first embodiment of the invention shown in the figure. However, the base P-type layer 19 contains Ge at 5×1018 ICm-,'
(10%) added.

According to this embodiment, there are effects similar to those of the first embodiment of the present invention. However, since the base layer is doped with 10% Ge, the bandgap of the base layer is narrowed by about 50 meV, and therefore the injection of minority carriers into the emitter becomes about 1/7. Therefore, there is an effect that the operating speed and current amplification factor of the element are further improved compared to the first embodiment.

For reference, the impurity concentration distribution of a bipolar transistor according to the prior art is shown in FIG.

Next, the first manufacturing method of the first embodiment of the present invention will be explained based on FIGS. 6(a) to 6(d).

After forming an n÷-type buried layer 2 and an n-type epitaxial layer 3 on a p-type Si substrate 1, an element isolation region 5 is formed of a SiOx film. Thereafter, a base extraction electrode 6 is formed from a p-type polycrystalline Si film, and by oxidizing it, a 5iOz film 7 for separating the base and emitter is formed. The manufacturing method of the above steps is publicly known.

Next, a base layer is formed (after exposing the taxi-killed Si layer 3, 200 polycrystalline Si films are deposited, and ion implantation is performed to reduce BFz÷ to 3×10 at an acceleration energy of 20 keV.
After that, the polycrystalline Si is completely oxidized in an 02 atmosphere at 900°C, and the formed SiOx film is removed to a thickness of 300mm and a peak concentration of I x 10"c.
Forming the base layer 4 of yn-8 (a). Next, an n-type epitaxial layer 8 with a thickness of 300 nm is selectively formed on the opening at a substrate temperature of 800° C. by thermal decomposition of 5 iHz CQ 2 gas to which HCQ and PHs are added. P of this layer
The concentration is 5 x 10"am-' (b), and then the n-type polycrystalline Si with a P concentration of I After the film is deposited, patterning is performed by etching as usual photolithography to form emitters 9. The n-type polycrystalline Si film contains A instead of P.
s may be added. Also, the n-type polycrystalline Si in this part
Instead of a film, n deposited by normal plasma CVD method
A type microcrystalline Si film or other wide bandgap heteromaterial may be used (FIG. 6(C)). Next, normal C
After depositing the SiOx film 7 by the VD method, a contact hole with the electrode is formed by ordinary photolithography and etching, and finally, after depositing a metal film, the electrode 10 is formed by ordinary photolithography and etching.

This completes the explanation of the first manufacturing method of the first embodiment of the present invention. According to this method, since an emitter can be formed in a self-aligned manner with respect to a graft base having a fine width that is formed in a self-aligned manner, an element having a small parasitic capacitance due to a junction can be formed.

Next, a second manufacturing method of the first embodiment of the present invention will be explained based on FIGS. 7(a) to 7(d).

An n-type buried layer 2 on a p-type Si substrate 1. After forming the n-type epitaxial layer 3, the element isolation region 5 is formed of a 5iOz film. Next, after exposing the epitaxial layer on which the base layer is to be formed, a thickness of 300 mm and a peak concentration of I
A base layer 4 of X 10"θ--8 is formed. After that, a single crystal S
An n-type single crystal Si layer of 8.5 iOz is deposited on the n-type polycrystalline Si film. The P concentration in this layer is 5X101
' Qll-8, the thickness is 350 people (a).

Next, after forming a 100-thick 5iOz film 12 at 850°C in an 02 atmosphere, a 500-thick 5ixN4 film 13 and a 4000-thick (7) SjO2 film 14 were formed by normal CV.
An island pattern made of these films is formed on the emitter layer 8 by the D method and by ordinary photolithography and etching.

After that, the thickness of 600 people was heated at 850℃ in a wet atmosphere.
i○2 film 15 film shape 5, then ion implantation method with acceleration energy 25 keV B+ 1 × 1015! -2
It is implanted and activated in a Nz atmosphere at 850° C. to form a graft base 16 (b).

Next, after depositing a 5isNt film 17 (thickness: 2000 nm), the 51gN4 film 17 other than the side wall portions of the 5iOz film 14 was removed by anisotropic dry etching, and the SiOx
Film 15 is also removed. Next, a p-type polycrystalline Si film 6 (thickness: 3000 nm) was deposited by the usual CVD method, and 4 polycrystalline Si films were deposited on the Si○2 film 14 by filling the recesses with resist and planarizing by etching back. The film is selectively removed (FIG. 7(C)). Next, after removing the 5iOz film 14, a SiO2 film 7 is formed by thermal oxidation in a wet 02 atmosphere at 850°C. Further, after removing the 5isNa film 13 and the 5iOz film 12, a p-doped polycrystalline Si film 9 is deposited by the usual CVD method, and an emitter pattern is formed by the usual photolithography and etching (d). Needless to say, As may be added to the polycrystalline Si film instead of P. Also, polycrystalline S
Instead of the i film, an n-type microcrystalline Si film deposited by a normal plasma CVD method or another wide band gap hetero material may be used. Next, electrodes are formed by the method described in the explanation of FIG. 6(d).

This concludes the explanation of the second manufacturing method of the first embodiment of the present invention. According to this method, since the periphery of the emitter-base junction is formed by thermal oxidation, there is an effect that the leakage current between the base and emitter is smaller than that in the first method using the selective epitaxial method.

Next, the manufacturing method of the second embodiment of the present invention will be explained based on FIGS. 8(,) to (d). First, in the first embodiment, the 8th
The structure shown in Figure (a) is formed. However, the thickness of the base layer 4 is 600 mm, the ion implantation of BF2+ is 8×1018×-2 so that the peak concentration is 2×10×2−8, and the diffusion temperature of the polycrystalline Si film is 930° C.

Next, a polycrystalline Si film 17 (thickness: 20 mm) is formed using the normal CVD method.
After forming □, A by the ion implantation method.
Accelerate s+ with energy 10keVi' 1 x 10
"cm-QT chikomi (b).

Next, polycrystalline Si film 17 was formed in a wet atmosphere at 900°C.
By completely thermally oxidizing 19, an n-type single crystal Si layer 11 having a peak concentration of As of 3×10 19 an-8 and a thickness of 300 nm is formed (c).

Next, after removing the 5ins film 18, a polycrystalline Si film 9 doped with P or As is deposited by a normal CVD method. Instead of the polycrystalline Si film, an n-type microcrystalline Si film deposited by a normal plasma CVD method or another wide band gap hetero material may be used. Furthermore, an emitter pattern is formed by conventional photolithography and etching (d). Finally, electrodes are formed by the method described in the explanation of FIG. 6(d). According to the above, the second aspect of the present invention
This concludes the explanation of the manufacturing method of the embodiment.

The manufacturing method of the third embodiment of the present invention will be explained based on FIGS. 11(a) to 11(f). First, after forming an n medium-sized buried layer 2, an n-type epitaxial layer 3, and a 5ift film 5 for element isolation on a p-type substrate l by the same method as the conventional method,
P-type polycrystalline Si film 6, S i C) a film 7 by VD method
After depositing , 6 and 7 are removed by conventional photolithography and etching to form an opening over the element region. Furthermore, polycrystalline Si was formed by heat treatment at 950°C in an N2 atmosphere.
Diffuse B from the membrane to form the graft base 16 (a
). Next, normal MBE (Molecular BeaIIEpitax)
By the method of y), Ge is 10% and Ga is i x 101
gcm-” included p-type Si layer 19 (300 layers thick),
Then, an n-type S'i layer 8 (300 layers thick) containing 5×10 18 As is formed. However, a polycrystalline Si film is formed on the 5iOz7. Further, the polycrystalline Si film on the 5iOz7 except the area around the opening is removed by ordinary photolithography and etching (b).

Next, S i Ox film 12 (thickness: 200), 5isN film 13 (thickness: 500), 5iOz film 14 (thickness: 350)
After depositing the film (0) by a conventional CVD method, an island pattern made of these films is formed on the opening by conventional photolithography and etching (C).

Next, after completely oxidizing the n-type Si layer 8 in a wetoz atmosphere at 800°C, a polycrystalline Si film 20 is formed using a normal CVD method.
Then, the polycrystalline Si film on the 5-inch IL film 14 is selectively removed by filling the recess with a resist and nipping (d).

Next, after removing the Sing film 14, the wet
* Oxidize the polycrystalline Si film 20 in an atmosphere to form a 5ins film 21
(film thickness 2000 people).

Then, the 5iaNa film 13.5ift film 12 is further removed by normal etching (e).

Finally, an emitter and an electrode made of an n-type polycrystalline Si film or a hetero material are formed by the same method as explained in FIGS. 6(Q) and (d). This concludes the explanation of the manufacturing method.

〔Effect of the invention〕

In the conventional technology, the limit for vertical miniaturization of bipolar transistors is a base width of 400, and the limit for operating speed is fT□8 of 55 GHz.

According to the present invention, problems such as leakage current between the emitter base, punch-through between the emitter and collector, relative increase in hole accumulation in the emitter, and decrease in current amplification factor, which are problems caused by miniaturization in the conventional technology, can be avoided. Therefore, the base width can be miniaturized to 200 Å or less.

Regarding the operating speed, f Tmax is 75 GHz in the first embodiment of the present invention when the base width is 200 people.
65 GHz in the second embodiment, 85 GHz in the third embodiment
GHz, which makes it possible to increase the speed compared to the conventional technology.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal cross-sectional view of a bipolar transistor according to a first embodiment of the present invention, FIG. 2 is an impurity concentration distribution diagram along line A-A' in FIG. Longitudinal sectional view, 4th
The figure is an impurity concentration distribution diagram of the BB' line part in Figure 3, and
The figure is an impurity concentration distribution diagram of a bipolar transistor according to the prior art, Figures 6 and 7 are cross-sectional views showing the manufacturing process of the first embodiment, and Figure 8 shows the manufacturing process of the second embodiment. 9 is a diagram showing the relationship between the n-type impurity concentration and the equilibrium hole concentration Po, FIG. 10 is a diagram showing the accumulated hole concentration distribution at the emitter of the bipolar transistor of the conventional method and the present invention, and FIG. 11 is a diagram showing the relationship between the n-type impurity concentration and equilibrium hole concentration Po. FIG. 12 is a sectional view showing the manufacturing process of the third embodiment of the present invention, and is an impurity concentration distribution diagram of the portion taken along line CC' in FIG. 11(f) of the third embodiment of the present invention. 1...p-type Si substrate, 2...n medium-sized buried layer, 3...
・N-type epitaxial layer, 4...p-type layer (base),
5...5iOz film, 6...P-type polycrystalline Si film, 7.
...SiOx film, 8...n-type single crystal Si layer, 9...
n-type polycrystalline Si layer, 10...metal electrode, 11...n
Type single crystal Si layer, 12...5i02 film, 13...5
ixNth film, 14...SiO2 film, 15...SiO
2 film, 16... p-type Si layer, 17 polycrystalline Si film, 1
8...SiO2 film, 19...p-type single crystal 5iGe,
20... Polycrystalline Si film, 21... Si ○2

Claims (1)

[Claims] 1. The peak concentration of impurities is 5 x 10^1^8 cm^-^
In a bipolar transistor in which an emitter consisting of a protrusion of n-type single crystal Si with a p-type impurity concentration of less than 1 x 10^1^8 cm^-^3 is formed on a base composed of three or more p-type single crystal Si layers, A bipolar transistor characterized by a structure in which a part of the emitter is formed on the n-type single crystal Si by an n-type polycrystalline Si film or a hetero material other than crystalline Si. 2. The n-type impurity concentration of the n-type single crystal Si protrusion is 1×
10^1^8cm^-^3 or more 5x10^1^9cm^
The bipolar transistor according to claim 1, characterized in that the bipolar transistor has a structure of -^3 or less. 3. The structure is characterized in that the height of the protrusion of the n-type single crystal Si is larger than the thickness of the depletion layer extending to the emitter side in a state where no bias is applied at the junction with the base, and is 500 Å or less. The bipolar transistor according to claim 1. 4. The peak concentration of p-type impurity in the base is 5×10^1^
In a Si bipolar transistor in which the p-type impurity concentration of the n-type single crystal emitter is 8 cm^-^3 or more and the p-type impurity concentration of the n-type single crystal emitter is 5 x 10^1^8 cm^-^3 or more, the carrier of the n-type single crystal Si emitter Density is 1 x 10^1^8 cm^-^3 or more 5 x 10^1^9 cm^
A bipolar transistor characterized by a structure in which a part of the emitter is formed on the n-type single-crystal Si with n-type polycrystalline Si or a hetero material other than crystalline Si. 5. Features a structure in which the thickness of the emitter part of n-type single crystal Si is larger than the thickness of the depletion layer extending to the emitter side when no bias is applied at the junction with the base, and is less than 500 Å. 5. The bipolar transistor according to claim 4. 6. In the method for manufacturing a bipolar transistor according to claims 1 to 3, after forming an opening on the base layer, an epitaxial layer having a desired impurity concentration and thickness is selectively formed on the opening. 1. A method for manufacturing a bipolar transistor, comprising a step of growing a polycrystalline Si film containing an n-type impurity or a step of depositing a hetero material other than crystalline Si. 7. In the method for manufacturing a bipolar transistor described in Claims 1 to 3, after forming a base layer, a Si layer with a desired impurity concentration and thickness is formed on a single crystal substrate as an epitaxial layer and an insulating layer. A step of depositing a polycrystalline layer on the Si layer, a step of forming an island pattern of an anti-oxidation film in the region of the epitaxial layer of the Si layer, and a step of oxidizing the Si layer other than the portion where the anti-oxidation film is formed. A method for manufacturing a bipolar transistor, comprising the steps of: removing the oxidation prevention film, and then depositing a polycrystalline Si film containing an n-type impurity or a hetero material other than crystalline Si. 8. A bipolar transistor according to any one of claims 1 to 3, characterized in that Ge is contained in single crystal Si of the base layer.