JP3053831B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for a self-aligned bipolar transistor and a BiCMOS transistor in which the density of an electrode extraction portion is increased, and manufacturing thereof. About the method.

To increase the speed of the (prior art) bipolar transistors, the improvement of the cutoff frequency f _T, collector-base junction capacitance, reduced such element isolation capacity, and reduce the parasitic elements of the base resistance and the like are important .

To reduce parasitic elements, fine pattern processing technology and high-precision alignment technology are required for lithography, but with pattern processing technology, pattern dimensions have evolved to the submicron order. In addition, the mask alignment accuracy of photolithography has been an obstacle in miniaturizing and increasing the speed of the semiconductor element region.

FIG. 4 is a cross-sectional view of a conventional semiconductor device having a bipolar transistor. In the figure, a P-type semiconductor region 43 and an N-type semiconductor region 44 are formed on a main surface of an N-type semiconductor substrate 41, and the semiconductor substrate 41, the P-type region 43 and the N-type region 44 are respectively composed of a collector region and a base region. ,
And function as an emitter region.

On the surface of the semiconductor substrate 41, an insulating film 45 is formed outside the position on the outer edge of the base region 43, and on the insulating film 45,
Polycrystalline semiconductor layer extended in connection with the base region 43
46 is formed, a polycrystalline semiconductor layer 46, a region where the polycrystalline semiconductor layer 46 does not exist on the base region 43, and a region where the polycrystalline semiconductor layer 46 does not exist on the insulating film 45 have outer edges of the emitter region 44. An insulating layer 47 is formed outside the position on the part.

In addition, a window 48 is formed in the insulating layer 47 on the surface of the polycrystalline semiconductor layer 46 formed so as to extend on the insulating film 45, and an external device is connected to the polycrystalline semiconductor layer 46 through the window 48. Base electrode
40 are formed.

According to such a structure, the base electrode 40 is
Since the base region 43 is connected to the base region 43 via the polycrystalline semiconductor layer 46 outside the region 43, the area of the base region 43 can be reduced as compared with a case where a base electrode is directly connected to the base region 43.

However, in such a structure, the polycrystalline semiconductor layer 46
Since the polycrystalline semiconductor layer is formed by etching after forming the polycrystalline semiconductor layer on the surface of the substrate 41, the area of the polycrystalline semiconductor layer 46 occupying the base region 43 must be relatively large. Is an obstacle to improving In addition, there is a problem that it is difficult to improve the operation speed because the junction capacitance is required to be relatively large.

In addition, for the same reason, the area of the insulating layer 47 occupying the base region 43 also becomes large, which also poses a problem in reducing the area.

Regarding the technology for solving these problems, for example, Japanese Patent Publication No. 55-26630 and Japanese Patent Publication No. 55-27469, or IEICE Technical Report (Vol.89.No.141) It is discussed on pages 33-37.

Hereinafter, with reference to FIG.
The prior art discussed in Japanese Patent Publication No. 630 and Japanese Patent Publication No. 55-27469 will be described.

First, an SiO ₂ oxide film 4b is formed on the surface of a silicon substrate 100 on which an N ⁺ layer 2 and an N layer 3 are formed on a P-type substrate 1, and a field for element isolation is performed by selective oxidation by a normal LOCOS method. An insulating film 4a is formed. In the following description, the field insulating film 4a and the SiO ₂ oxide film 4b may be simply referred to as the oxide film 4 in some cases.

Next, a Si ₃ N ₄ film 20 is formed on the surface of the oxide film 4, and further, polysilicon 21 is deposited on the entire surface, and thereafter, a region to be a base and an emitter is opened [FIG.

Next, after doping the polysilicon 21 with boron as a P-type impurity by ion implantation or the like, the surface is oxidized to form an oxide film 22. Further, the Si ₃ N ₄ film 20 and the oxide film 4b are formed.
Is subjected to side etching so that an undercut occurs, and then polysilicon 23 is further deposited on the entire surface including the undercut portion [FIG.

Next, the polysilicon 23 is etched until the N layer 3 of the silicon substrate 100 is exposed [FIG. At this time, as described later in detail, since the polysilicon 23 (21) and the N layer 3 are made of the same material, the etching cannot be stopped at the interface, and a part of the N layer 3 is also etched. .

Next, the surface is oxidized by a thermal oxidation treatment to form an oxide film 22.
Form a. At this time, the polysilicon 21 and the semiconductor substrate 1
In the portion where the N layer 3 contacts the N layer 3, the P
Type impurity is introduced into N layer 3 to form an external base region of P ⁺
An area 26 is formed [FIG.

Then, boron ions are implanted from above the oxide film 22a to form an intrinsic base region 24. Further, after opening the oxide film 22a in a portion where the emitter region is formed, a polysilicon 27 containing an N-type impurity such as arsenic is formed. After that, an emitter region 25 is formed by an N-type impurity diffusion process using the polysilicon 27 as an impurity source [FIG. 3 (e)]. Thereafter, a base electrode and an emitter electrode are taken out in the same manner as in the prior art. An opening is provided and external wiring is performed to complete a bipolar transistor.

According to such a conventional technique, since the external base region 26 is formed in a self-aligned manner, the width of the external base region 26 is determined by the side etching amount of the Si ₃ N ₄ film 20 and the oxide film 4b. It is very easy to reduce the width. Therefore, since the area of the external base region 26 can be reduced, the junction capacitance between the collector and the base is reduced.

Further, according to the manufacturing method, the structure of the bipolar transistor can be obtained by only one lithography step when the polysilicon 21 is opened in the step of FIG. Can be.

On the other hand, FIG. 3 is a cross-sectional view of the bipolar transistor described in the IEICE technical report, and the same reference numerals as those in FIG. 2 represent the same or equivalent parts.

In this prior art, after forming the insulating film 4 in the same manner as in the step (a) of FIG. 2, the insulating film in the active region including the external base region is removed, and then the polysilicon 6 and the silicon oxide film 7 are deposited. Then, an opening is formed in a portion serving as a base region and an emitter region. The structure at this point is almost the same as the above-mentioned step (c).

After that, the polysilicon 6 and the silicon oxide film 7 are
Etching until the N layer 3 of the semiconductor substrate 100 is exposed,
Thereafter, after forming the base region 24 in the same manner as described above, the sidewall 10 is formed.

Next, after the polysilicon 11 is formed on the entire surface, the emitter region 25 is formed by an N-type impurity diffusion process using the polysilicon 11 as an impurity source to complete the bipolar transistor.

(Problems to be Solved by the Invention) In the above-described conventional bipolar transistor, in any case, the polysilicon semiconductor layer 23 or 6 is etched just above the emitter region or the intrinsic base region of the semiconductor substrate 100 made of single crystal silicon. How to do is essential.

According to such an etching method, as described in the step (C) of FIG. 2, when the polysilicon 23 is etched, a part of the semiconductor substrate 100 is simultaneously over-etched. e), the positions of the surfaces of the emitter region 25 and the intrinsic base region 24 are below the interface between the polysilicon 21 and the semiconductor substrate 100, and the external base region 26 and the intrinsic base region twenty four
However, there is a problem in that the connection cross-sectional area with the semiconductor device decreases, causing an increase in base resistance and hindering high speed operation.

There is a solution to this problem by extending the external base region 26 further downward by increasing the heat treatment.However, increasing the depth of the external base region 26 increases the junction capacitance, and further increases the distance between the base and collector. Other problems such as deterioration of the breakdown voltage occur, and the characteristics of the bipolar transistor are remarkably deteriorated.

Here, the silicon shaving amount of the silicon semiconductor substrate in the above-described conventional technology is as follows.

For etching of polysilicon, Cl ₂ gas or CCl
A reactive ion etching method using a _four- system gas is employed, and generally, a condition having an etching rate of about 1000 ° / min under the above conditions is selected.

Further, as described in the step (c) of FIG. 2, when the polysilicon 23 is etched, it is necessary to perform over-etching so that no polysilicon remains on the silicon oxide film 22, The amount of over-etching varies depending on the state on the silicon semiconductor substrate, but a condition of about 10 to 15% of the required amount of etching is selected.

Moreover, although different depending on the mechanism of the dry etching apparatus, the in-plane distribution occurs in the etching amount in the silicon semiconductor substrate, and as a result, in the above-described conventional technology, the silicon shaving amount is forced to occur in the range of about 100 to 500 °, This greatly hinders speeding up.

Moreover, since this etching is reactive ion etching (RIE) or ion milling having anisotropy, a defect (damage) layer due to ion irradiation is generated in the emitter region 25 and the intrinsic base region 24 made of polycrystalline silicon. Let me do it. This defective layer cannot be completely removed later, and causes problems such as an increase in junction leakage current between the emitter and the base.

Hereinafter, the increase in the base resistance caused by over-etching and the hindrance to the increase in the speed due to the over-etching will be specifically described.

FIG. 5 is a diagram showing a general relationship between the amount of silicon shaved by etching and the base resistance of the substrate surface serving as the base region and the emitter region, and the base resistance increases in proportion to the amount of silicon shaved. I can understand.

FIG. 6 is a diagram showing the relationship between the base resistance and the delay time obtained by the basic gate circuit of ECL (Emitter Coupled Logic), and it is understood that the delay time increases as the base resistance increases. it can.

As described above, the silicon collapse leads to an increase in the base resistance, which is a major obstacle to speeding up.

On the other hand, in the conventional example described with reference to FIG. 3, since the oxide film in the active region is completely removed,
The junction 30 between 26 and the N-type layer 3 comes into contact with the field insulating film 4a.

Generally, the field insulating film 4a is formed by local thermal oxidation using the Si ₃ N ₄ film as a mask, so that thermal strain remains in the field insulating film 4a, and the thermal strain causes bonding.
30 deteriorates, the leak current increases, and the problem that the characteristics of the bipolar transistor deteriorate occurs.

Note that a technique for manufacturing a semiconductor device by forming an insulating film on a single crystal semiconductor substrate and epitaxially growing a semiconductor layer on the single crystal semiconductor substrate in an opening provided in the insulating film is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-30144. Publication No.
It is disclosed in Japanese Patent Publication No. 4-33920. However, there is no suggestion as to the problem associated with the above-described over-etching or the necessity of considering this problem.

An object of the present invention is to solve the problems described above and to provide a semiconductor device which can be highly integrated and has excellent characteristics and a method for manufacturing the same.

(Means for Solving the Problems) In order to achieve the above object, the present invention has taken the following measures.

(1) First having an opening on the surface of a single crystal semiconductor substrate
Comprising a semiconductor element formed in a single-crystal semiconductor layer grown on the single-crystal semiconductor substrate in the opening to a position substantially equal to a surface position of the first insulating film. In the device, a semiconductor layer connected to the single crystal semiconductor layer and extending outward is provided at an outer peripheral portion inside the opening, and this is made to function as a lead electrode of the semiconductor element.

Further, the present invention is characterized in that the following manufacturing steps are provided in order to provide the semiconductor device having the above-described configuration.

(3) a step of forming an insulating film on the main surface of the single crystal semiconductor substrate; a step of forming a first opening in the insulating film; and at least a step of forming a first opening on the single crystal semiconductor substrate in the first opening. Forming a single-crystal growth layer by integrating the single-crystal semiconductor until the surface position of the insulating film is substantially the same as the surface position of the insulating film; and integrating the single-crystal semiconductor substrate and the single-crystal growth layer. Forming a bipolar transistor in the integrated single crystal layer.

(4) a step of sequentially forming an insulating film, a second conductive type semiconductor layer, and an insulating layer on the first conductive type single crystal semiconductor region formed on the main surface of the single crystal semiconductor substrate; Forming a first opening reaching the insulating film in the first semiconductor layer; selectively etching the insulating film to form a first opening between the single crystal semiconductor region and the first semiconductor layer; Forming an undercut portion on the side surface facing the opening of the insulating film by side-etching the insulating film; and on a single crystal semiconductor region including the undercut portion,
A step of growing a single crystal semiconductor so as to be integrated at least until it is substantially the same as the surface position of the insulating film to form a single crystal growth layer connected to the first semiconductor layer; Forming a sidewall on a side surface in the opening; integrating the single crystal semiconductor region and the single crystal growth layer; forming a second conductive layer on the integrated single crystal layer exposed at the bottom of the first opening; Introducing an impurity of a mold type; activating the impurity by heat treatment to form an intrinsic base region; introducing an impurity in the first semiconductor layer into the integrated single crystal layer; Forming an external base region connected to the first conductive type, and forming a first conductive type second semiconductor layer on the entire surface including the region in the first opening, and then forming a first conductive type impurity in the semiconductor layer. Into the intrinsic base domain Forming an emitter region.

(5) A step of introducing germanium into a main portion of the intrinsic base region is further provided.

(6) a step of forming an insulating film on the main surface of the single crystal semiconductor substrate; a step of forming a first opening in the insulating film; and at least a step of forming a first opening on the single crystal semiconductor substrate in the first opening. Forming a single-crystal growth layer by integrating the single-crystal semiconductor until the surface position of the insulating film becomes substantially the same as the surface position of the insulating film; and integrating the single-crystal semiconductor substrate and the single-crystal growth layer. A step of oxidizing at least a surface of the integrated single crystal layer to form an oxide insulating film; and a step of forming a MOS transistor having the oxide insulating film as a gate insulating film in the integrated single crystal layer. .

(7) a step of sequentially forming an insulating film, a second conductive type semiconductor layer, and an insulating layer on the main surface of the first conductivity type single crystal semiconductor substrate; and reaching the insulating layer and the semiconductor layer to the insulating film. A groove is formed to form a gap, and the insulating layer and the semiconductor layer are stacked, the first semiconductor layer and the first insulating layer are stacked, and the second semiconductor layer and the second insulating layer are stacked. And selectively etching the insulating film in the gap,
Forming an under-quad portion by side-etching the insulating film on a side surface facing the groove between the single-crystal semiconductor substrate and the first and second semiconductor layers; On a single crystal semiconductor substrate,
Forming a single crystal growth layer connected to the first and second semiconductor layers by growing the single crystal semiconductor so as to be integrated at least until the surface position of the insulating film becomes substantially the same; At least the surface of the integrated single crystal layer formed by integrating the single crystal semiconductor substrate and the single crystal growth layer, which is exposed at the groove, is oxidized to form an oxide insulating film, and the inside of the first and second semiconductor layers is formed. Forming a source / drain region region by introducing an impurity of the formula (1) into the integrated single crystal layer; forming a sidewall on a side surface of the groove; and forming a third semiconductor on the entire surface including a region in the groove. A step of forming a layer; and a step of connecting a gate electrode to the third semiconductor layer.

(2) First having an opening in the surface of the single crystal semiconductor substrate
Obtained by oxidizing a part of the single crystal semiconductor layer which has been grown on the single crystal semiconductor substrate in the opening until it is substantially the same as the surface position of the first insulating film in the opening. A semiconductor device formed with a field-effect semiconductor element using the insulating film as a gate insulating film, wherein a semiconductor layer connected to the single crystal semiconductor layer and extending outward at an outer peripheral portion within the opening is formed. This was made to function as a lead electrode of the field effect type semiconductor element.

(Operation) According to the above configuration (1), since a semiconductor device is formed in a newly grown single crystal semiconductor layer, it is possible to provide a bipolar transistor having excellent characteristics without being adversely affected by etching. Become.

According to the above configuration (2), a MOS transistor can be manufactured by the same manufacturing method as in the above (1). Therefore, when applied to BiCMOS, a bipolar transistor and a MOS transistor can be formed simultaneously. Therefore, the manufacturing process can be simplified.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view of a main part for describing a method of manufacturing a bipolar transistor according to one embodiment of the present invention, and the same reference numerals as those in FIG. 2 or FIG. 4 represent the same or equivalent parts. .

First, a silicon oxide film 4b and a field insulating film 4a are formed on the surface of the semiconductor substrate 100 in the same manner as described with reference to FIG. 2 (FIG. 2A).

Then, for example, the polysilicon film 6 is
Deposit to a thickness of 0 mm. For example, boron ions of about 1 × 10 ²⁰ atoms / cm ² as P-type impurities are introduced into the polysilicon film 6 by ion implantation.

Further, a refractory metal alloy 5 such as tungsten silicide (WSi ₂ ) is deposited to a thickness of 2000 ° by, for example, a CVD method, and a silicon oxide film 8 is deposited to a thickness of 2000 ° by, for example, a CVD method. Fig. (B)].

Next, the silicon oxide film 8, the refractory metal alloy film 5, and the polysilicon film 6 are sequentially etched by, for example, an etching process using a photoetching method and a reactive ion etching method, and processed into a desired shape [FIG. (C)].

At this time, the silicon oxide film 4b is interposed between the silicon semiconductor substrate 100 and the polysilicon film 6, and the silicon semiconductor substrate 100 is not damaged or scraped by the etching process.

The refractory metal alloy film 5 is provided for the purpose of reducing the wiring (external base wiring) resistance, and may not be provided unless it is particularly necessary.

Next, the silicon oxide film 4b is treated with, for example, a hydrofluoric acid aqueous solution and etched so as to generate an undercut [FIG.

Next, the semiconductor substrate 100 including the undercut portion
A silicon single crystal 3a is grown thereon to a thickness of 100 to 1000 mm so as to be integrated with the semiconductor substrate 100 [FIG. This is one of the major features of the present invention.

The growth of the silicon single crystal 3a is performed, for example, by using SiH ₂ Cl ₂ -H ₂
This is carried out in a HCl gas system at a temperature of 900 ° C. and a pressure of 50 Torr or less.

Next, after depositing a silicon oxide film over the entire surface by, for example, a CVD method, the silicon oxide film is etched by a reactive ion etching method to form a sidewall (silicon oxide film) 10 for separating an emitter and a base.

Next, boron ions are introduced into the integrated single crystal layer 200 formed by integrating the semiconductor substrate 100 and the silicon single crystal 3a by ion implantation, and the heat treatment is further performed to form the intrinsic base region 9. At this time, the boron impurity in the polysilicon 6 is simultaneously diffused into the silicon substrate to form the external base region 13, and the base region and the intrinsic base region 9 are connected [FIG.

Next, for example, the polysilicon film 11 is
After being deposited to a thickness of Å, for example, arsenic is implanted into the polysilicon film 11 at a dose of 1 × 10 ¹⁶ atoms / cm ² at an energy of 60 keV, and is activated by a predetermined heat treatment. An emitter region 12 is formed by an N-type impurity diffusion process using 11 as an impurity source.

Further, the polysilicon film 11 is etched using a photoetching method so as to cover at least the opening in the step (f) of FIG.

Thereafter, an opening for taking out a base electrode and an emitter electrode is provided and external wiring is performed in the same manner as in the prior art, thereby completing the bipolar transistor according to the present invention.

FIG. 9 is a plan view of the bipolar transistor formed as described above, and the same reference numerals as those in FIG. 1 indicate the same or equivalent parts. The openings 91 and 92 represent an opening for taking out the base electrode and an opening for taking out the collector electrode, respectively. It should be noted that the polysilicon 11 is omitted in FIG.

According to this embodiment, as shown in FIG. 1 (c), when the silicon oxide film 8, the high melting point metal alloy film 5, and the polysilicon film 6 are etched, the silicon oxide film 4 is formed on the substrate surface. Is formed, there is no damage or scraping of the substrate surface, and the characteristics are not deteriorated.

Further, according to the present embodiment, as described in the steps (e) and (d) in the same figure, single-crystal silicon is grown on the portion where the silicon oxide film 4b is removed, and the region including the single-crystal silicon is formed. Since the intrinsic base region 9 and the embossed region 12 are formed, the cross-sectional area at the connection between the external base region 13 and the intrinsic base region 9 can be made sufficiently large, and the base resistance can be kept low.

In addition, since the polysilicon 6 and the external base region are connected in the undercut portion, the cross-sectional area can be reduced and the degree of integration can be improved.

Furthermore, according to the present embodiment, the silicon oxide film 4b is partially present at the end of the field insulating film 4a, and the diffusion of impurities in the polysilicon 6 is performed through the grown single crystal silicon 3a. In addition, the junction surface between the external base region 13 and the N layer 3 as the collector region does not come into contact with the field insulating film 4a, so that the base-collector junction breakdown voltage does not deteriorate.

FIG. 7 is a sectional view of another embodiment of the present invention, and the same reference numerals as those described above denote the same or equivalent parts.

The method of manufacturing a semiconductor device according to the present embodiment includes a silicon oxide film
The steps from the side etching of 4b to the growth of single-crystal silicon on that portion are the same as those described above, and therefore the description thereof will be omitted.

In this embodiment, when the growth of the single crystal silicon is completed,
Germanium is implanted into a portion serving as a base region by ion implantation or the like to form a germanium region 70. The germanium content is about 10%.

After the ion implantation of germanium is completed, the heat treatment is performed to diffuse the boron impurities in the polysilicon 6 into the silicon substrate, thereby forming the external base region 13. Further, the polysilicon film 11 is reduced to a thickness of 200 mm. After deposition, for example, arsenic is
Implantation of 1 × 10 ¹⁶ atoms / cm ^{2 is performed} at an energy of keV, a predetermined heat treatment is applied, and an N ⁺ emitter region 12 is formed by an N type impurity diffusion process using the polysilicon film 11 as an impurity source.

In the above description, germanium is introduced by ion implantation. However, after the side etching, silicon-germanium-silicon may be continuously grown.

According to this embodiment, the band gap of the emitter becomes relatively wider than that of the base, and the injection efficiency of the emitter is improved, so that the cutoff frequency is improved and the speed is increased.

FIG. 8 is a sectional view of another embodiment of the present invention, and the same reference numerals as those in FIG. 1 indicate the same or equivalent parts. The present embodiment is characterized in that the features of the present invention described above are applied to a MOS transistor.

When manufacturing a MOS transistor, oxide films 4a and 4b, an N-type polysilicon film 6, a refractory metal alloy film 5, and an insulating film 8 are formed on a substrate 100, and then the N-type polysilicon film 6, A groove is formed in the melting point metal alloy film 5 and the insulating film 8 to reach the oxide film 4b to form a gap.

Next, the oxide film 4b is side-etched to form an undercut portion [FIG.
Is epitaxially grown [FIG. (B)].

Incidentally, the refractory metal alloy film 5 is provided for the purpose of reducing the wiring resistance similarly to the above, and the present invention is applied to a MOS LSI.
This is particularly effective when applied to, but need not be provided in other cases.

Next, thermal oxidation is performed to oxidize the single crystal silicon 3b exposed to the outside at the opening to form the gate insulating film 80. At this time, simultaneously, the N-type impurity of the polysilicon layer 6 diffuses into the substrate 100 to form the source / drain regions 82 [FIG.

Next, after the sidewalls 10 are formed in the same manner as described above (FIG. 4D), polysilicon 11 is formed and the MO is removed.
Complete the S transistor.

In this embodiment, the case of an N-type channel MOS transistor has been described. However, if the polysilicon film 6 is of the same P-type as the bipolar, a P-type channel MOS transistor can be formed.

FIG. 10 is a plan view of the MOS transistor formed as described above, and the same reference numerals as those in FIG. 8 denote the same or equivalent parts. Openings 93 and 94 are openings for taking out source / drain electrodes, and opening 95 is an opening for taking out gate electrodes.

According to this embodiment, a MOS transistor can be formed by the same method as the above-described bipolar transistor. In particular, in a so-called BiCMOS transistor or the like in which a bipolar transistor and a MOS transistor are formed on the same substrate, a bipolar transistor is used. Since the transistor and the MOS transistor can be formed at the same time, the manufacturing process can be simplified.

(Effects of the Invention) As is clear from the above description, according to the present invention, the following effects are achieved.

(1) Since the connection cross-sectional area between the external base region and the intrinsic base region can be sufficiently secured, a bipolar transistor having a high operation speed can be realized without increasing the base resistance.

(2) Since the etching of the external base lead-out wiring and the like is performed on the silicon oxide film formed on the surface of the active region, the active region is not damaged and a bipolar transistor having good characteristics can be obtained.

(3) If the manufacturing method of the present invention is applied to a MOS transistor, a bipolar transistor and a MOS transistor can be formed simultaneously, so that the manufacturing process of the BiCMOS can be simplified.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a method of manufacturing a bipolar transistor according to one embodiment of the present invention, FIGS. 2, 3, and 4 are cross-sectional views for explaining a conventional technique, and FIG. FIG. 6 is a diagram showing a general relationship between the amount and the base resistance, FIG. 6 is a diagram showing a relationship between the base resistance and the delay time, FIG.
FIG. 8 is a cross-sectional view of another embodiment of the present invention, FIG. 8 is a cross-sectional view for explaining a method of manufacturing a MOS transistor according to the present invention, FIG. 9 is a plan view of FIG. FIG. 9 is a plan view of FIG. 8 (e). 3a, 3b: silicon single crystal, 4a: field insulating film,
4b ...... SiO ₂ oxide film, 5 ...... refractory metal alloy film, 6, 11 ...
... polysilicon film, 8 ... silicon oxide film, 9 ... intrinsic base region, 10 ... sidewall, 12 ... emitter region, 13 ... external base region, 80 ... gate insulating film, 82 ...
... source / drain regions, 100 ... silicon substrate

Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/78 (72) Inventor Takahiro Nagano 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-63 JP-A-289863 (JP, A) JP-A-64-10667 (JP, A) JP-A-62-66619 (JP, A) JP-A-63-62271 (JP, A) JP-A-2-203534 (JP, A) JP-A-55-33051 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/331 H01L 21/336 H01L 21/8249 H01L 27/06 H01L 29/73 H01L 29 / 78

Claims (4)

(57) [Claims] A first conductivity type single crystal semiconductor region formed on a main surface of a single crystal semiconductor substrate; an insulating film formed on a surface of the single crystal semiconductor region and having a first opening; A single-crystal growth layer in which a single-crystal semiconductor is grown on the single-crystal semiconductor region in the opening of at least until the surface position of the insulating film becomes substantially the same as that of the single-crystal semiconductor; A first monocrystalline layer formed by integrating a growth layer and an insulating film;
A second opening smaller than the opening at the position where the opening is formed, and the integrated single crystal layer is formed between the outer periphery of the first opening and the outer periphery of the second opening. A first semiconductor layer of a second conductivity type connected to the first semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and being the same as the second semiconductor layer;
An insulating layer having an opening, a sidewall formed on a side surface of the second opening, and a second conductivity type impurity from the first semiconductor layer introduced into a surface of the integrated single crystal layer. An intrinsic base region formed by introducing impurities into the surface of the integrated single crystal layer using the sidewalls as a mask, and connected to the external base region; And a second semiconductor layer of the first conductivity type formed in the second opening, and a first conductivity type impurity from the second semiconductor layer is formed on the surface of the intrinsic base region. A semiconductor device comprising: an emitter region. 2. The semiconductor device according to claim 1, further comprising a third semiconductor layer containing germanium in said intrinsic base region. 3. A step of forming an insulating film and a semiconductor layer on the main surface of a single crystal semiconductor substrate in this order, and selectively etching the semiconductor layer into a predetermined shape until the insulating film is exposed. Forming the opening, and selectively etching the insulating film exposed at the first opening to a wider range than the first opening so that an undercut to the semiconductor layer occurs. Forming a second opening wider than the first opening; and forming a single-crystal layer on the single-crystal semiconductor substrate in the second opening until the surface becomes substantially the same as the surface position of the insulating film. A step of growing the semiconductor layer integrally and bonding the semiconductor layer to a substrate surface at the undercut portion; and a side wall in the first opening so as to cover an end surface of the semiconductor layer exposed in the first opening. Insulated side wall Forming a bipolar transistor in an integrated single crystal layer formed by integrating the single crystal semiconductor substrate and a single crystal layer; and depositing a semiconductor film in the first opening. And a method of manufacturing a semiconductor device. 4. A step of forming an insulating film and a semiconductor layer on the main surface of a single-crystal semiconductor substrate in this order, and selectively etching the semiconductor layer into a predetermined shape until the insulating film is exposed. Forming the opening, and selectively etching the insulating film exposed at the first opening to a wider range than the first opening so that an undercut to the semiconductor layer occurs. Forming a second opening wider than the first opening; and forming a single-crystal semiconductor on the single-crystal semiconductor substrate in the second opening until at least the surface position of the insulating film is substantially the same as that of the insulating film. Bonding the semiconductor layer to the substrate surface at the undercut portion, and oxidizing at least the surface of the integrated single crystal layer exposed at the first opening to form an oxide insulating film. Forming a MOS transistor in the integrated single crystal layer, the MOS transistor having the oxide insulating film as a gate insulating film.