JPH11307771A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extremely lower parasitic capacitance and relatively readily manufacture by a method wherein a source region and a drain region are each formed on an element isolation insulation layer. SOLUTION: A source region 14a and a drain region 14a each formed on field oxide films 12, 12, namely an element isolation insulation layer. Thus, a pn junction is not formed under the source region 14a and the drain region 14a, and occurrence of junction capacitance can be eliminated. As the result, it is possible to operate at an extremely higher speed than usual. Further, an oxide film 12 is not provided in a lower layer of a channel region. Accordingly, it is possible to eliminate floating effects which are a problem in a SOI structure. Further, in the operations of an element, a current flows in a channel layer, thereby causing heat, which can be diffused via a silicon substrate 11 having high heat conductivity, and heat radiating characteristic is also excellent.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device optimally used as a transistor element constituting a high-speed LSI and a method of manufacturing the same. More specifically, the present invention provides:
The present invention relates to a semiconductor device including a MOS transistor, a bipolar transistor, or both, which has a low parasitic capacitance and can be manufactured relatively easily and requires a high-speed operation, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, high integration of semiconductor integrated circuits has progressed, and accordingly, further miniaturization and higher speed of semiconductor devices constituting integrated circuits have been demanded. Hereinafter, among such semiconductor devices, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) will be described as an example.

FIG. 11 is a schematic sectional view showing the structure of a conventional MOSFET 100. MOSFET shown in the figure
Is a so-called LDD (Lightly Doped D)
(rain) type structure. In order to suppress the punch-through phenomenon between the source and the drain due to the so-called short channel effect in accordance with the miniaturization of the element size, as shown in FIG. 124 is provided.

A conventional MO will be described below with reference to FIG.
The configuration of the SFET will be described along with its manufacturing process. MO
In manufacturing the SFET, first, the n-type silicon substrate 1
21, an element isolation region 122 of a field oxide film,
A gate oxide film 125 and a gate polysilicon film 126 are respectively formed, and an SiO ₂ film 127 is formed on the gate polysilicon film 126.

[0005] Next, from above the substrate 121, BF ₂ an acceleration voltage 30 keV, ions are implanted at a dose of 2E14 / cm ² about conditions, to form the LDD region 124b of a low concentration is ion-implanted. Next, the SiO ₂ film was about 100nm is deposited on the entire surface of the substrate by the RIE method SiO ₂ film 10
By etching (etch back) about 0 nm, a side wall 123 made of SiO ₂ is formed on the side surface of the gate polysilicon film 126 with a width of about 100 nm. Furthermore, the BF ₂ acceleration voltage 45 keV, a dose of 3E15 /
Ions are implanted under the condition of cm ² to form a region 124a in which ions are implanted at a high concentration.

Next, RTA (Rapid Therma)
1 Annealing) is performed, and a heat treatment is performed at about 1000 ° C. for about 10 seconds to activate the impurities introduced by the ion implantation to form the source and drain diffusion layers. Next, a refractory metal film, for example, a titanium (Ti) film is deposited on the entire surface of the substrate by a sputtering method or the like, and is reacted with silicon (Si) of the substrate by an RTA method to form titanium silicide (TiSix). Further, unreacted titanium is removed by etching with a sulfuric acid-hydrogen peroxide-based etchant. In this way, the metal silicide film 124c can be selectively formed only in the high-concentration ion implantation region 124a where the substrate surface is exposed.

[0007] Finally, an interlayer insulating film 128 is deposited, an opening for contact is formed, and then source and drain electrodes 129 are wired to complete the MOSFET.

In the transistor manufactured by such a method, since the low-concentration ion implantation region 124b is formed in the channel region between the source and the drain by adopting the LDD structure, the drain electric field is reduced and the breakdown voltage is reduced. As a result, the short channel effect can be prevented. Further, a metal silicide film 124c having a low resistance is formed on the surface of the source and drain diffusion layers 124a for reducing the resistance.

However, in the structure shown in FIG. 1, a junction capacitance is generated between the source or the drain and the substrate.
Therefore, there has been a limit in increasing the speed of the apparatus.

Therefore, recently, SOI (Silicon)
A structure called “on insulator” is being adopted. FIG. 12 shows a MOSF having this SOI structure.
It is a schematic sectional drawing showing the structure of ET. This structure is characterized in that a thin silicon layer 133 is formed on an oxide film 132 formed on a silicon substrate 131 as shown in FIG. Since the layers above the thin film silicon layer 133 have the same configuration as that illustrated in FIG. 11, the same reference numerals are given and the description is omitted.

As can be seen from FIG. 1, no junction capacitance is generated because the oxide film 132 is formed below the source and drain regions 124a. As described above, when the SOI structure is used, the parasitic capacitance of the source and the drain can be significantly reduced while making use of the advantage of the LDD structure, so that a high-speed semiconductor device can be expected.

Next, a bipolar transistor will be described as a second example of a conventional semiconductor device. FIG.
FIG. 1 is a schematic sectional view showing a structure of a conventional bipolar transistor. The transistor shown in the figure is a so-called "npn-type" bipolar transistor, and the configuration thereof is schematically described along the manufacturing process as follows. That is, first, the collector epitaxial layer 181 is grown on the silicon substrate 180 including the high-concentration n-type buried layer, and is further separated by the oxide insulating layer 182. Next, polycrystalline silicon 183 is deposited, doped with a p-type impurity by using an ion implantation method, and then processed into the illustrated shape.

Next, an insulating film 184 is deposited, and an opening 185 for forming an internal base and an emitter is opened. Next, an internal base 186 is formed by an ion implantation method, and then an insulating film 187 is formed on a side wall of the opening 185. Next, an n-type emitter region 189 is formed by depositing polycrystalline silicon 188, doping with n-type impurities and applying a thermal process. At this time, the impurity is diffused from the p-type doped polycrystalline silicon 183 to form the external base region 190.

Thereafter, a contact opening is formed in the insulating film 184 to form a metal electrode 191 to complete the bipolar transistor. In the bipolar transistor manufactured in this way, a very thin base layer can be formed, so that a higher cutoff frequency can be obtained as compared with a MOS transistor, and application to a higher-speed circuit is possible.

[0015]

However, the conventional MOS transistors and bipolar transistors described above all have the following problems.

First, a MOS transistor will be described. In the SOI structure as shown in FIG. 12, a silicon substrate 131 and a MOSFET element formed thereon are insulated by an oxide film 132. Therefore, MO
There has been a problem that a floating effect occurs due to the electrical floating of the SFET element.

Further, since the thermal conductivity of the oxide film 132 is low, the heat generated by the device operation is
In addition, there is also a problem that the reliability of the device may be impaired by accumulating in the device 3.

Furthermore, the SOI structure is expensive in cost, and although the effect of reducing the parasitic capacitance can be expected, there is a problem that the cost performance is relatively reduced as a result of a significant increase in the manufacturing cost.

On the other hand, a bipolar transistor as shown in FIG.
In the transistor, there is a problem that a parasitic capacitance is generated between the external base region 190 and the collector region 181 due to a pn junction, which causes deterioration of device characteristics.

The present invention has been made in view of the various problems described above. That is, the objective is to have a very low parasitic capacitance and to be relatively easy to manufacture,
An object of the present invention is to provide a semiconductor device suitable for application to a MOSFET, a bipolar transistor, and the like, and a manufacturing method thereof.

[0021]

That is, a semiconductor device according to the present invention comprises a source region made of a semiconductor of a first conductivity type, a drain region made of a semiconductor of a first conductivity type, the source region and the drain region. The second provided between
A semiconductor device comprising a channel region made of a conductive semiconductor and a gate formed on the channel region with an insulating film interposed therebetween, wherein the source region and the drain region are each formed of an element isolation insulating layer. The structure is characterized in that it is formed on the upper side, and the parasitic capacitance caused by the junction under the source / drain region is greatly reduced, and the floating effect and the heat radiation characteristic, which are disadvantages of the SOI structure, are also eliminated. be able to.

When forming a semiconductor layer on such an insulating layer, so-called lateral epitaxial growth can be used.

Alternatively, a crystal may be grown isotropically from the semiconductor portion exposed on the surface, and then polished to a predetermined layer thickness.

Further, by providing a so-called LDD region, the short channel effect can be suppressed, and the device size can be reduced and the speed can be increased.

Further, if the insulating layer is formed by the STI method, a so-called “bird's beak” can be solved.
Further, since the surface can be maintained smooth, lateral epitaxial growth of silicon crystal on the insulating layer can be easily realized, and its crystallinity can be improved.

On the other hand, a semiconductor device according to the present invention includes a semiconductor substrate, a first conductivity type collector layer formed on the semiconductor substrate, and an insulating layer selectively formed on a surface of the collector layer. An internal base region formed of a semiconductor layer of the second conductivity type formed on a collector region insulated and separated by the insulating layer, and an internal base region formed on the insulating layer on both sides of the insulated collector region; A base having an outer base region formed of a second conductivity type semiconductor layer extending from the inner base region and a first conductivity type emitter region formed on the inner base region; -A high-performance bipolar transistor can be realized by greatly reducing the junction capacitance between the collectors.

On the other hand, if the above-described semiconductor device as a MOS transistor and a semiconductor device as a bipolar transistor are mixedly mounted on a semiconductor substrate, a Bi-CMO having a high-speed and high-performance hybrid analog / digital circuit can be obtained.
The semiconductor device as S can be realized.

[0028]

In the present invention, a silicon crystal layer is epitaxially grown by selective epitaxial growth using a field oxide film, that is, a silicon substrate surrounded by an oxide film for element isolation as a seed. At this time, a silicon crystal layer is grown in the lateral direction and is formed to extend on the field oxide film. Thereafter, a transistor is formed on the silicon crystal layer.

As a result, the junction capacitance between the source and the drain is greatly reduced, and the element can operate at high speed. Further, the same performance can be obtained without using an SOI substrate, which greatly contributes to cost reduction.

Further, a bipolar transistor is formed on the crystalline silicon layer.
If a transistor is formed, the capacitance between the base and the collector can be greatly reduced, and the speed can be further increased.

Further, a similar effect can be obtained by applying the present invention to a BiCMOS in which a MOSFET and a bipolar transistor are mixedly mounted.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view illustrating the structure of a semiconductor device according to the present invention. That is, the semiconductor device illustrated in FIG. 1 is a p-MOSFET, and its configuration is schematically described as follows.

The FET 10 has a source / drain region 1 which is heavily doped on the surface of an n-type silicon substrate 11.
4a, 14a and lightly doped LDD regions 14b, 14b adjacent to the inside thereof. Source·
Metal silicide films 14c, 14c are formed on the drain regions 14a, 14a to reduce device resistance. On the other hand, the active region 1 between the source and the drain
On 1A, a gate oxide film 15, a gate polysilicon film 16, and an oxide film 17 are deposited in this order. Further, on these side surfaces, side walls 2 made of silicon oxide are provided.
0 and 20 are provided. The surface of the device is covered with an insulating film 18, and source / drain electrodes 19, 19 are formed through contact openings.

A feature of the present invention is that the source region 14a and the drain region 14a are respectively formed on the field oxide films 12, 12, that is, on the insulating layer for element isolation. By doing this,
A pn junction is not formed under the source region 14a and the drain region 14a, and the occurrence of junction capacitance can be eliminated. As a result, it becomes possible to operate at a much higher speed than in the past.

According to the present invention, no oxide film 12 is provided below the channel region. Therefore, FIG.
The floating effect which becomes a problem in the SOI structure as shown in FIG. 2 can be eliminated. Further, heat generated by flowing a current through the channel layer during operation of the device can be diffused through the silicon substrate 11 having high thermal conductivity, and has excellent heat dissipation characteristics. As a result, it is possible to solve the problem that the temperature of the element rises and the characteristics are degraded or the reliability is lowered.

Here, as a different point from the structure of the present invention, for example, it is conceivable to form a high-resistance layer under the source / drain region by introducing oxygen or the like by an ion implantation method. However, if an insulating layer is provided on the silicon substrate 11 and the source / drain region 14a having a high carrier concentration is provided thereon, a so-called MIS (Meta
l Insulator Semiconductor
An r) type structure is formed, and a capacitance due to this MIS structure is generated. Here, when a high-resistance layer is formed by introducing oxygen or the like by an ion implantation method, it is difficult to form a sufficiently thick high-resistance layer, and a MIS capacitance that cannot be neglected occurs. A problem arises that the parasitic capacitance increases. For example, in the case where an insulating layer is formed by introducing oxygen by an ion implantation method, the thickness of the formed insulating layer is at most about 400 nm. On the other hand, according to the present invention, the source / drain regions 14a are arranged on the field oxide film 12, and the thickness of the field oxide film 12 can be easily increased. The layer thickness of the field oxide film may be, for example, about 700 nm or more, preferably about 1000 nm. As a result,
The invention also has the advantage that the generated MIS capacity is negligible.

Next, a first method for manufacturing a semiconductor device according to the present invention will be described. 2 and 3 are process cross-sectional views illustrating a main part of a manufacturing process of the MOSFET 10 according to the present invention. In manufacturing the MOSFET 10, first, a field oxide film 12 is formed on an n-type silicon substrate 11 as shown in FIG. As a method of forming this,
For example, LOCOS (Local Oxidation
of Silicon) method, that is, a selective oxidation method using a silicon nitride film as a mask can also be used. However, when the LOCOS method is used, a so-called “bird's beak” may protrude from an oxide layer,
This may be disadvantageous for miniaturization of the element. Therefore, in the same figure, a so-called STI (Shallow Trend
(Ch Isolation) technology is illustrated. Specifically, the surface of the silicon substrate 11 is
Etching is performed by an anisotropic etching method such as an E (Reactive Ion Etching) method to form a trench (groove), silicon oxide is buried in the trench by a CVD method, and the surface of the substrate is smoothed. As shown in FIG. 5A, the field oxide film 12 which is smooth with the substrate surface and has less protrusion of the insulating layer can be formed. In this manner, the p-M insulatingly separated by the field oxide film 12 is provided on the surface of the substrate.
An active region 11A of the OSFET is formed.

Next, as shown in FIG. 2B, a silicon single crystal layer 13 is grown. As this growth method,
For example, a CVD method or MBE (Molecular Be
Am epitaxy) method or the like can be used. Here, during the growth, various conditions such as the growth pressure, the growth temperature, the flow rate of the raw material gas, and the crystal orientation of the substrate are appropriately adjusted so that the epitaxial growth is selectively performed on the active region 11A exposed on the surface of the wafer. The grown silicon single crystal layer can be laterally grown at a higher rate (lateral epitaxial growth). As a result, as shown in FIG.
Can be formed. Furthermore, the silicon single crystal layer 1
3 is ion-implanted with an impurity serving as an n-type dopant.
In addition, instead of this ion implantation, the silicon single crystal layer 1
When epitaxially growing No. ₃ , for example, arsine (AsH ₃ ) may be mixed in and doped into n-type while growing the epitaxial layer. Also, after growth,
The silicon single crystal layer 13 may be patterned into a predetermined shape.

Next, as shown in FIG. 2C, an oxide film 1 serving as a gate insulating film is formed on the surface of the silicon single crystal layer 13.
5. A polycrystalline silicon film 16 and an oxide film 17 are deposited in this order, and a resist pattern 21 for patterning a gate electrode is formed. Thereafter, the oxide film 17, the polycrystalline silicon film 16 and the gate insulating film 15 are processed by RIE and patterned into a shape as shown in FIG.

Next, as shown in FIG.
The region 14b is formed. Specifically, BF2 is applied to the silicon single crystal layer 13 at an acceleration voltage of about 30 keV and a dose of about 2
Ion implantation is performed under the condition of E14 / cm ² to form a low concentration region 14b having an LDD structure. Next, as shown in FIG. 3A, the side wall 20 is formed. Specifically, an SiO ₂ film is deposited on the entire surface of the substrate to a thickness of about 100 nm, and the SiO ₂ film is
Approximately 100 nm etching (etch back) by IE method
By doing so, the side wall 20 made of SiO ₂ having a width of about 100 nm can be formed on the side surface of the gate polysilicon film 16.

Next, as shown in FIG. 3B, source / drain regions 14a are formed. Specifically, BF ₂ is ion-implanted into the silicon single crystal layer 13 at an acceleration voltage of about 45 keV and a dose of about 3E15 / cm ² . Furthermore, RTA (Rapid Thermal Annea)
By performing a heat treatment at a temperature of about 1000 ° C. for about 10 seconds to activate the ion-implanted impurities by the method 1), the source / drain region 14 having a high carrier concentration is activated.
a can be formed.

Next, as shown in FIG. 3C, a metal silicide film 14c is formed. Specifically, first, a thin film of a high melting point metal, for example, titanium (Ti) is deposited on the entire surface of the wafer by a method such as a sputtering method. further,
The metal and silicon of the substrate are reacted by the RTA method to form titanium silicide, and then the unreacted titanium is removed by etching with a sulfuric acid-hydrogen peroxide-based etchant. Thus, the high-concentration ion-implanted region 1 exposed on the surface
The metal silicide film 14c can be selectively formed only on 4a.

Next, as shown in FIG. 3D, an interlayer insulating film 18 and an electrode 19 are formed. Specifically, first,
After an interlayer insulating film 18 is deposited on the entire surface of the wafer and an opening for contact is formed, the source and drain electrodes 19 are formed.
Wiring etc.

By the steps described above, the p-MOSFE
T is completed.

According to the manufacturing method described above, FIG.
As shown in FIG. 2B, the silicon single crystal film 13 serving as a source / drain region can be formed on the field insulating film 12 by positively utilizing the so-called lateral epitaxial growth.

As described with reference to FIG. 2A, when the so-called STI technique is used as the method for forming the field oxide film 12, the surface of the substrate can be maintained smooth, and the silicon single crystal film 13 can be formed. Lateral epitaxial growth can be easily realized,
In addition, the crystallinity of the silicon single crystal 13 grown on the field oxide film 12 can be made high quality. As a result, various characteristics of the semiconductor device are improved, and the reliability is also improved.

Next, a second method of manufacturing a semiconductor device according to the present invention will be described. 4 and 5 are process cross-sectional views illustrating the main parts of the manufacturing process of the present manufacturing method. Also in the present manufacturing method, first, the field oxide film 12 is formed as shown in FIG. As this forming method, for example, STI can be used.

Next, as shown in FIG. 4B, an etching stopper film 24 is selectively formed. Specifically, a film made of, for example, silicon nitride is deposited on the entire surface of the wafer, and an opening centering on the active region 11A is formed as shown.

Next, as shown in FIGS. 4C to 5A, a silicon single crystal layer 13 is grown. Specifically, the active region 11 is formed by a method such as a CVD method or an MBE method.
Epitaxial growth centering on A. At this time,
By appropriately adjusting various conditions such as the growth pressure, the growth temperature, the flow rate of the source gas, and the crystal orientation of the substrate, the crystal growth proceeds isotropically, and the silicon single crystal becomes trapezoidal or pyramidal as shown in the figure. Layer 13 can be grown epitaxially. For example, on a silicon substrate having a (100) plane orientation, the silicon single crystal layer 13 as shown in the figure can be formed by isotropic epitaxial growth in the <111> direction.

Next, as shown in FIG. 5B, the silicon single crystal layer 13 is polished to smooth the surface. Specifically, for example, CMP (Chemical Mechanical)
The surface of the silicon single crystal layer 13 is polished by an electrical polishing method and etched until the surface of the nitride film 14 comes out, so that the surface is processed smoothly without excessively damaging the silicon single crystal layer 13. Can be.

Next, as shown in FIG. 5C, the gate oxide film 15, the gate polysilicon film 16, the oxide film 17,
LDD region 14b, side wall 20, source / drain region 1
The MOSFET 10B is completed by sequentially forming 4a, the interlayer insulating film 18, and the electrode 19. Here, the contents of each step are substantially the same as those described above with reference to FIGS. 2 and 3, and therefore, the same reference numerals are given and the description is omitted.

According to this manufacturing method, the source / drain region 14a is formed on the field oxide film 12 by forming the silicon single crystal layer 13 isotropically on the active region 11A of the silicon substrate and polishing it. Can be formed. Therefore, the semiconductor device of the present invention can be manufactured even in the case where the lateral epitaxial growth is difficult as described above with reference to FIG.
In particular, when the ratio of the length to the layer thickness of the source / drain region 14a to be formed is large, that is,
When the source / drain regions are thin and have a wide range, lateral epitaxial growth may not be easy. Even in such a case, a semiconductor device having a similar structure can be manufactured by growing and polishing the silicon single crystal layer 13 isotropically by this method.

In each of the specific examples described above,
Although a p-MOSFET is illustrated, the present invention is not limited to this. That is, the present invention can be similarly applied to an n-MOSFET in which the conductivity type of each layer is inverted, and the same effect can be obtained. Further, according to the present invention, the p-MOSFET and the n-
-It is also possible to mix and form MOSFETs,
A so-called CM with extremely low parasitic capacitance and capable of high-speed operation
An OS configuration can also be realized.

Next, an example in which the present invention is applied to a bipolar transistor will be described.

FIG. 6 is a schematic sectional view illustrating the structure of a bipolar transistor according to the present invention. That is,
The bipolar transistor illustrated in FIG. 1 is a so-called npn-type bipolar transistor, and its configuration is schematically described as follows.

Bipolar transistor 50 A is formed on n-type buried layer 60 and has n-type collector region 6.
1, a p-type internal base region 66 and an n-type emitter region 69. On the n-type emitter region 69, a polysilicon layer 68 and an emitter electrode 74 are formed. Also,
Sidewall spacers 67 are formed on the side surfaces of the polysilicon layer 68. Further, the surface of the element is covered with an insulating film 64, and the base electrode 72 is formed through the opening.
And a collector electrode 76 are formed. A feature of the present invention is that a main part of the p-type external base region 63 extending from the p-type internal base region 66 is formed on the field oxide film 62, that is, on the inter-element insulating layer. is there. As is clear from comparison with FIG. 13 shown as a conventional example, in the present invention, the external base region 6
3 is formed on field oxide film 62 without contacting collector region 61. With such a configuration, the junction capacitance generated between collector region 61 and external base region 63 can be significantly reduced.
As a result, the parasitic capacitance of the bipolar transistor can be greatly reduced, and the device characteristics can be greatly improved.

The MOSFET described above with reference to FIG.
As in the case of (1), also in the bipolar transistor 50A, the MIS structure is formed below the external base region 63. However, in the present invention, since the field oxide film 62 can be formed to have a large thickness, there is also an advantage that the generated MIS capacitance can be suppressed to a negligible level. As a result, it is possible to obtain a value that is almost twice as large as the conventional one at the maximum oscillation frequency (fmax).

Next, a method of manufacturing bipolar transistor 50A will be described. FIG. 7 is a cross-sectional view of a main part step, illustrating a method for manufacturing a bipolar transistor according to the present invention. In manufacturing the bipolar transistor 50A, first, as shown in FIG. 7A, a base epitaxial layer 63 is formed on the field oxide film 62. Specifically, first, an n-type buried layer 60 having a high carrier concentration is formed on a p-type silicon substrate by using a normal diffusion technique or the like. Further, an n-type collector epitaxial layer 61 is grown. Further, the field oxide film 62
Is used to insulate and isolate the active region of the bipolar transistor. As a method of forming the field oxide film 62,
For example, the STI technology described above can be used.

Next, an internal base region 66 and an external base region 66 are formed by growing silicon. As this growth method, for example, the method described above with reference to FIG. 2 or FIGS. 4 and 5 can be used. That is, both the internal base region 63 and the external base region 66 are formed as silicon single crystal films. Further, at this time, for example, diborane (B ₂ H ₆ ) is mixed at a predetermined growth pressure, a growth temperature, and a source gas flow rate, and the silicon layer is grown to be p-type doped. Further, if a source gas such as monogermane (GeH ₄ ) is added at a predetermined pressure, temperature, and gas flow rate, a silicon-germanium (SiGe) layer can be formed.

The silicon crystal layer formed on the field oxide film 62 may be subjected to patterning in order to form the external base region 63.

Next, as shown in FIG. 7B, an insulating film 64 and a sidewall spacer 67 are formed. Specifically, the insulating film 64 having a predetermined thickness is formed by a CVD method or the like.
Is deposited. Further, an opening 65 is formed in the insulating film 64 through a photolithography process. Next, a sidewall spacer 67 can be formed by depositing an insulator to a predetermined thickness and etching back by RIE.

Next, as shown in FIG. 7C, an emitter region 69 is formed. More specifically, polycrystalline silicon 68 is deposited on the entire surface of the wafer, and arsenic (As) is ion-implanted under the conditions of an acceleration voltage of about 60 keV and a dose of about 1E16 / cm ² , and then a heat treatment is performed to implant arsenic in the opening. By diffusion, an n-type emitter region 69 can be formed.
Instead of arsenic ion implantation here, arsenic may be doped in the polycrystalline silicon 68 in advance and diffused into the opening. Further, single crystal silicon may be epitaxially grown instead of polycrystalline silicon.

Next, as shown in FIG. 7D, electrodes are formed. That is, the emitter electrode 74 is formed on the polycrystalline silicon 68. Further, by forming predetermined openings in the insulating film 64 and the field oxide film 62 and forming the base electrode 72 and the collector electrode 74, respectively, the bipolar transistor 50A is completed.

According to the present invention, it is possible to manufacture a bipolar transistor in which the capacitance between the collector and the base is greatly reduced by forming a single crystal silicon layer extending over field oxide film 62. it can. Further, here, the external base region 63 extending on the field oxide film 62 is formed of high-crystalline silicon single crystal together with the internal base region. The characteristics of the type transistor as a semiconductor device are also improved.

In FIGS. 6 and 7, an npn-type bipolar transistor has been described as an example.
The present invention is not limited to this. Besides this,
The present invention can be similarly applied to, for example, a pnp type bipolar transistor, and the same effect can be obtained.

Next, the present invention is applied to a Bi-CMOS (Bipo CMOS).
lar-CMOS) will be described. FIG. 8 is a schematic sectional view showing the structure of the Bi-CMOS device according to the present invention. That is, the Bi-CMOS device 80 of the present invention includes the MOS transistor portion 10C formed on the silicon substrate 81 and the bipolar transistor portion 50.
B. The detailed configuration of each transistor section can be substantially the same as that shown in FIGS. 1 and 6, and the same reference numerals are given and the description is omitted. The Bi-CMOS device according to the present invention is characterized in that the source / drain region 14a of the MOS transistor portion 10C and the external base region 63 of the bipolar transistor portion 50B.
Are formed on the field oxide film 82, respectively. That is, with such a configuration, as described above, the parasitic capacitance of the source / drain region of the MOS transistor section 10C and the bipolar transistor section 5
The parasitic capacitance between the base and the collector of 0B can be greatly reduced. As a result, it is possible to operate at a higher speed than in the past, and to realize a maximum oscillation frequency (fmax) twice or more as compared with the conventional one, and to realize an analog / digital mixed circuit device excellent in noise and other characteristics. be able to.

Next, the Bi-CMOS device 8 according to the present invention will be described.
0 will be described. 9 and FIG.
FIG. 10 is a schematic process sectional view illustrating the method for manufacturing the i-CMOS element 80. That is, in manufacturing the Bi-CMOS device 80, first, as shown in FIG. 9A, a field oxide film 82 is formed on a silicon substrate 81, and silicon layers 13 and 63 are grown. Specifically, first, as described above, the field oxide film 82 is formed by the STI technique or the like, and the well region of the MOS transistor and the collector region of the bipolar transistor are insulated from each other. Next, as described above for each element, the single crystal silicon layer 13 and the silicon layer 63 are grown, respectively. Thus, the epitaxial layer 13 serving as the source / drain and channel regions of the MOS transistor portion and the base epitaxial layer 63 serving as the base layer of the bipolar transistor portion can be formed.

Next, as shown in FIG.
Doping is performed on a channel portion of the transistor portion. Specifically, for example, after oxidizing the entire surface of the wafer and forming a mask under predetermined conditions, the dopant can be ion-implanted only into the channel portion of the MOS transistor portion.

Next, as shown in FIG.
The gate of the transistor portion is formed. Specifically, after removing the oxide film on the wafer surface, a gate oxide film 15 is formed, and then a polycrystalline silicon film 16 and a nitride film 17 are deposited and patterned to form a gate electrode. Can be formed. Further, the LDD regions 14b, 14b are formed by introducing a dopant at a relatively low concentration by ion implantation. Next, a nitride film is formed on the entire surface of the wafer by the CVD method, and is etched back by the RIE method, whereby the side wall 20 of the nitride film can be formed on the side surface of the gate. Further, a source region 14a and a drain region 14a can be formed by ion-implanting a dopant into the source and drain regions.

Next, as shown in FIG. 10A, an insulating film 90 is deposited on the entire surface of the wafer. Specifically, for example, a silicon oxide film can be deposited to a predetermined thickness by a CVD method.

Next, as shown in FIG. 10B, a main portion of the bipolar transistor portion is formed. Specifically, an opening 91 is formed in the insulating film 90, a second insulating film is further deposited, and the sidewall spacer 67 is formed by etching back by anisotropic etching such as RIE. it can. Thereafter, polycrystalline silicon 68 is deposited, arsenic is ion-implanted under the conditions of an acceleration voltage of about 60 keV and a dose of about 1E16 / cm ² , and a predetermined heat treatment is performed to form an n-type emitter region 69.

Finally, as shown in FIG. 10C, electrodes are formed. Specifically, a contact hole is opened in the insulating film, and a source hole is formed using a material such as aluminum.
By forming the drain electrodes 19, 19, the base electrode 72, the emitter electrode 74, the collector electrode 76, and the like, the Bi-CMOS device is completed.

According to the present invention, in the same step, the source / drain region of the MOS transistor and the external base region of the bipolar transistor can be simultaneously formed on the field oxide film 82. A Bi-CMOS device with significantly reduced parasitic capacitance can be easily manufactured.

In the above example, the p-MOS
The example in which the FET and the npn-type bipolar transistor are combined has been described, but the present invention is not limited to this. In addition, a Bi-CMOS device in which a device whose conductivity type is inverted is combined can be similarly manufactured.

[0075]

The present invention is embodied in the form described above, and has the following effects.

First, according to the present invention,
By forming the source region and the drain region on the field oxide film, that is, on the insulating layer for element isolation, a pn junction is not formed under the source region and the drain region, and the generation of a junction capacitance is eliminated. can do. As a result, it becomes possible to operate at a much higher speed than in the past.

Further, according to the present invention, since no oxide film is provided below the channel region of the MOSFET, the floating effect, which is a problem in the SOI structure, can be eliminated and the operation of the device can be improved. At this time, heat generated by passing a current through the channel layer can be diffused through the silicon substrate having high thermal conductivity, and has excellent heat dissipation characteristics. As a result, it is possible to solve the problem that the temperature of the element rises and the characteristics are degraded or the reliability is lowered.

That is, according to the present invention, the conventional SOI
It is possible to significantly reduce the junction capacitance between the source and the drain and to increase the speed of the element, while preventing deterioration of the element performance due to heat accumulation, which is a problem in MOS transistors using the technology.

Further, according to the present invention, the same performance can be obtained without using an SOI substrate, and the cost can be significantly reduced.

Further, according to the present invention, the thickness of the field oxide film can be easily reduced as compared with the method in which oxygen or the like is introduced below the source / drain regions by ion implantation to form a high resistance layer. M can be formed
Another advantage is that the IS capacity is negligible.

Further, according to the present invention, a predetermined silicon single crystal film can be formed on the field insulating film by positively utilizing the so-called lateral epitaxial growth or isotropic epitaxial growth. .

Here, if the so-called STI technique is used as a method of forming the field oxide film, the surface of the substrate can be kept smooth, and the silicon monocrystalline film can be formed laterally.
Epitaxial growth can be easily realized, and the crystallinity of the silicon single crystal grown on the field oxide film can be high. As a result, there are advantages that the characteristics of the semiconductor device are improved and the reliability is also improved.

On the other hand, according to the present invention, in the bipolar transistor, the main part of the external base region is formed on the field oxide film, that is, on the inter-element insulating layer, so that the parasitic capacitance between the base and the collector is greatly reduced. Thus, the device characteristics can be greatly improved.

Further, also in this case, since the thickness of the field oxide film can be made large, there is an advantage that the MIS capacitance generated can be suppressed to a negligible level.

According to the present invention, the source / drain regions of the MOS transistor and the external base region of the bipolar transistor can be simultaneously formed on the field oxide film in the same step. Is significantly reduced, and a Bi-CMOS device having much higher performance than before can be easily manufactured.

As described above, according to the present invention, it becomes possible to manufacture a semiconductor device having much higher performance than the conventional one by a relatively easy process, and the industrial advantage is great. .

[Brief description of the drawings]

FIG. 1 is a schematic sectional view illustrating the structure of a semiconductor device according to the present invention.

FIG. 2 is a process sectional view illustrating a main part of a manufacturing process of the MOSFET according to the present invention.

FIG. 3 is a process sectional view illustrating a main part of a manufacturing process of the MOSFET according to the present invention.

FIG. 4 is a process cross-sectional view illustrating a main part of a manufacturing process of the second manufacturing method of the MOSFET according to the present invention.

FIG. 5 is a process cross-sectional view illustrating a main part of a manufacturing process of the second manufacturing method of the MOSFET according to the present invention.

FIG. 6 is a schematic cross-sectional view illustrating the structure of a bipolar transistor according to the present invention.

FIG. 7 is a sectional view showing a substantial part of the method for manufacturing the bipolar transistor according to the present invention.

FIG. 8 is a schematic sectional view illustrating a structure of a Bi-CMOS device according to the present invention.

FIG. 9 is a schematic process sectional view illustrating the method for manufacturing the Bi-CMOS device according to the present invention.

FIG. 10 is a schematic process sectional view illustrating the method for manufacturing the Bi-CMOS device according to the present invention.

FIG. 11 is a schematic sectional view illustrating a structure of a conventional MOSFET.

FIG. 12 is a schematic cross-sectional view illustrating a structure of a MOSFET having an SOI structure.

FIG. 13 is a schematic sectional view showing a structure of a conventional bipolar transistor.

[Explanation of symbols]

10, 10B, 10C, 50A, 50B, 80 Semiconductor device 11 Semiconductor substrate 11A Active region 12 Field oxide film 13 Silicon single crystal layer 14a Source / drain region 14b LDD region 14c Silicide layer 15 Gate oxide film 16 Gate electrode 17 Insulating layer 18 Interlayer insulating layer 19 Electrode 21 Resist mask 24 Etching stopper layer 60 Collector layer 61 Collector region 62 Field oxide film 63 External base region 64 Interlayer insulating film 66 Internal base region 67 Sidewall spacer 68 Silicon layer 69 Emitter region 72 Base electrode 74 Emitter electrode 76 Collector electrode 82 Field oxide film

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/73

Claims (10)

[Claims] A source region formed of a semiconductor of a first conductivity type; a drain region formed of a semiconductor of a first conductivity type; and a second region provided between the source region and the drain region.
A semiconductor device comprising a channel region made of a conductive semiconductor and a gate formed on the channel region with an insulating film interposed therebetween, wherein the source region and the drain region are each formed of an element isolation insulating layer. A semiconductor device characterized by being formed thereon. 2. A semiconductor substrate having on its surface an insulating layer selectively provided and a semiconductor region insulated and separated by the insulating layer, a first substrate formed on the semiconductor region and serving as a channel region in a MOSFET. And a second and third semiconductor layers extending from the first semiconductor layer and formed on the insulating layer and serving as a source region and a drain region in a MOSFET, respectively. Characteristic semiconductor device. 3. The semiconductor device according to claim 1, wherein said insulating layer is formed by an STI method. 4. A step of selectively forming a first insulating layer on a surface of a semiconductor substrate to insulate and isolate an active region of a first conductivity type, and a step of selectively epitaxially growing a single-crystal silicon on said active region. A layer is epitaxially grown, and the single crystal silicon layer is grown at a higher speed in a direction substantially parallel to a direction substantially perpendicular to the surface of the semiconductor substrate, and is formed on the first insulating layer, respectively. Extending and forming; processing and forming a gate insulating film and a gate electrode on the single crystal silicon layer on the active region; and extending on the first insulating layer, respectively. Forming a source region and a drain region by introducing a second conductivity type impurity into the formed single crystal silicon layer. 5. A step of selectively forming a first insulating layer on a surface of a semiconductor substrate to insulate and isolate an active region of a first conductivity type; and a second insulating layer on the first insulating layer. Selectively forming a single crystal silicon layer from the surface of the active region by isotropic epitaxial growth by a selective epitaxial growth method, and forming a single crystal silicon layer extending on the first insulating layer, respectively. Etching and polishing the single crystal silicon layer to the surface of the second insulating layer; processing and forming a gate insulating film and a gate electrode on the single crystal silicon layer on the active region; Forming a source region and a drain region by introducing an impurity of a second conductivity type into the single crystal silicon layer extending on the first insulating layer, respectively. Device manufacturing method 6. The method for manufacturing a semiconductor device according to claim 4, wherein said first insulating layer is formed by an STI method. 7. A semiconductor layer of a first conductivity type formed on a semiconductor substrate, an insulating layer selectively formed on a surface of the semiconductor layer, and a collector region insulated and separated by the insulating layer. An inner base region made of a second conductivity type single crystal semiconductor layer, and a second conductivity type formed on the insulating layer around the insulated collector region and extending from the inner base region. A semiconductor device comprising: an external base region made of a single crystal semiconductor layer; and a first conductivity type emitter region formed in the internal base region. 8. A step of forming a first conductivity type collector layer on a semiconductor substrate; a step of selectively forming an insulating layer on a surface of the collector layer to insulate and separate the collector region; Selectively epitaxially growing an internal base layer thereon and extending the internal base layer above the insulating layer to grow an external base layer; and selectively forming a first conductive layer on a surface of the internal base layer. Forming an emitter region by introducing an impurity of a mold type. 9. A step of forming a collector layer of a first conductivity type on a semiconductor substrate; a step of selectively forming a first insulating layer on a surface of the collector layer to insulate and separate a collector region; Selectively epitaxially growing a single crystal silicon layer on the collector region, extending the single crystal silicon layer on the first insulating layer, and forming a second conductivity type base region; Forming a second insulating layer on the single crystal silicon layer; forming a first opening in the second insulating layer; forming a sidewall on a side surface of the first opening. Depositing a silicon layer containing an impurity of a first conductivity type in an opening surrounded by the sidewall, and diffusing the impurity in the single crystal silicon layer to form a silicon layer on a surface portion of the single crystal silicon layer; 1 conductivity The method of manufacturing a semiconductor device which of forming an emitter region, comprising the. 10. The M according to claim 1, wherein
A semiconductor device comprising: a semiconductor device as an OSFET; and a semiconductor device as a bipolar transistor according to claim 7 mounted on a semiconductor substrate.