JP2005072438A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method capable of manufacturing a BJT, an SiGeHBT, and a CMOS on a common semiconductor substrate with simple steps and of enhancing the reliability of any contact. <P>SOLUTION: A first opening W1 is formed in a first insulation film 20 and a polycrystal semiconductor film 21 on the base forming part of the HBT, and thereafter an SiGe layer 31 is formed by non-selective gas phase epitaxial growing method. Then a BJT forming part B and a collector layer surface of the HBT are exposed, a second insulating film 23 covers the base layer 30 of the BJT and an SiGe layer of the base forming part of the HBT, and the second insulation film 23 for the other parts is removed. Then a second opening W2 is formed to the second insulation film 23 on the base layer parts of the BJT and the HBT, and thereafter a second polycrystal semiconductor film 33 containing impurity is formed to form emitter layers 25, 26. Then the second polycrystal semiconductor film 33 is patterned to form a collector leadout electrode 34, an emitter electrode 35, a gate electrode 36, and LDD source / drain regions 37, 38, 40, 41. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device called BiCMOS in which a bipolar transistor and a CMOS transistor are formed on a common semiconductor substrate.

  Conventionally, BiCMOS in which a CMOS and a bipolar transistor are formed on a common silicon substrate is widely used in analog / digital mixed LSIs as a device capable of constructing a multifunctional system on one chip.

  In recent years, with BiCMOS, the demand for low power consumption performance and high functionality has increased with the increase in functionality, and it is necessary to form a high-performance bipolar transistor and a fine CMOS on a common silicon substrate at low cost. .

  In particular, bipolar transistors have a high demand for high-speed and low-current consumption performance, and high-speed and low-current consumption are being achieved by advances in self-alignment technology and microfabrication technology. A heterojunction bipolar transistor (hereinafter referred to as SiGeHBT) using a SiGe layer formed by selective vapor phase epitaxy as a base attracts attention. This SiGeHBT is excellent in high-frequency characteristics due to the formation of a thin base layer, the electric field acceleration effect by the tilted Ge profile, and the narrow band gap effect, and the base resistance can be reduced, and has been widely applied to BiCMOS.

  However, the base formation technique based on the selective vapor phase epitaxial growth method is inferior in the uniformity of characteristics as compared with the base formation technique based on the ion implantation method. That is, compared with SiGeHBT having a base formed by selective vapor phase epitaxy and an ordinary bipolar transistor (hereinafter referred to as BJT) having a base formed by ion implantation, SiGeHBT having a base formed by selective vapor phase epitaxy is In addition, there are large variations in transistor characteristics within the wafer surface and relative variations between wafers, and there is a concern that the manufacturing yield will deteriorate. This variation problem has been highlighted as a prominent problem, particularly with the increase in the diameter of manufactured wafers and the recent high accuracy of systems.

  On the other hand, in order to incorporate BJT having an ion-implanted base into BiCMOS formed from SiGeHBT and CMOS excellent in high-speed and low current consumption performance, the process becomes complicated due to the difference in the base forming method, and the manufacturing cost increases. There's a problem.

  A BiCMOS manufacturing method that solves this problem has been proposed (see, for example, Patent Document 1). In the BiCMOS manufacturing method disclosed in Patent Document 1, a gate electrode is formed through a gate insulating film in each of n-channel and p-channel MOSFETs (hereinafter referred to as MOS) forming portions on the surface of a silicon substrate. Using the electrodes as masks, p-type and n-type source / drain regions are formed, respectively.

  Next, a first insulating film is formed on the entire surface of the silicon substrate, an opening is formed in the first insulating film in the HBT formation portion, and then an HBT base layer is formed on the entire surface of the silicon substrate. A first semiconductor layer formed of a high impurity concentration SiGe film and a second semiconductor layer formed of an n-type low impurity concentration silicon film constituting the emitter layer are sequentially epitaxially grown to form a stacked semiconductor layer.

  Subsequently, by patterning the semiconductor layer of this stacked structure, an operation region by a single crystal portion on the opening of the first insulating film, and a base extraction region of a polycrystalline portion extending over the first insulating film therefrom The other part is removed by etching leaving

  Next, a second insulating film is formed on the entire upper surface of the silicon substrate and patterned to form a pattern on the second semiconductor layer on the emitter forming portion of the HBT operation region and a portion of the BJT link base region. Then, after forming an intrinsic base region of the BJT through the opening on the BJT, a polycrystalline silicon layer containing an n-type impurity is formed on the entire surface of the silicon substrate.

  Next, n-type impurities in the polycrystalline silicon layer are implanted into the second semiconductor layer and the intrinsic base region through the openings to form emitter regions, respectively, and then the polycrystalline silicon layer is patterned to extract the emitters. An electrode is formed.

  Thereafter, anisotropic etching is performed on the second insulating film and the first insulating film using each emitter lead electrode as a mask to form a sidewall on the side surface of each gate electrode, and then the gate electrode and the side Using the wall as a mask, n-type high concentration source / drain regions are formed.

Finally, for example, a reflow film is formed on the entire surface, on the emitter extraction electrode and base extraction electrode of the HBT, on the collector electrode extraction region, on the emitter extraction electrode of the BJT, on the base region, and on the collector electrode extraction region In addition, contact windows are formed on each gate electrode of each pMOS and nMOS and on the high concentration source / drain region, and each part is contacted through these contact windows, and an interlayer insulating layer is formed to form a multilayer wiring layer. BiCMOS is formed by forming a protective insulating film and the like.
Japanese Unexamined Patent Publication No. 2000-340648 (pages 5-7, FIGS. 1-10)

  By the way, the conventional BiCMOS manufacturing method uses a non-selective vapor phase epitaxial growth method to simplify the manufacturing of SiGeHBT and to reduce the number of manufacturing steps and improve the reliability. There is.

  First, the base layer and the emitter layer are stacked by a non-selective epitaxial growth method, the CMOS gate electrode is formed first, and then the BJT and SiGeHBT emitter electrodes are formed. There is a problem that it is complicated.

  Furthermore, since the collector electrode is in direct contact with the silicon substrate, there is a concern that the step in the contact formation process is large and the reliability of the contact is lowered.

  The present invention has been made to solve the above-described problem. A semiconductor device capable of manufacturing BJT, SiGeHBT, and CMOS on a common semiconductor substrate by a simple process and capable of improving contact reliability. It aims at providing the manufacturing method of.

In order to achieve the above object, a method for manufacturing a semiconductor device of one embodiment of the present invention includes a first bipolar transistor of an ion implantation base type and a second bipolar transistor of a SiGe base heterojunction type on a common semiconductor substrate, In a method of manufacturing a semiconductor device having a complementary insulated gate field effect transistor composed of a P channel and an N channel insulated gate field effect transistor, a first insulating film is formed on the entire surface of the semiconductor substrate. A step of forming a first polycrystalline semiconductor film on the entire surface of the first insulating film, a step of forming a base layer by ion implantation in the first bipolar transistor formation portion, A polycrystalline semiconductor film and the first insulating film are patterned to form a first opening in a base forming portion of the second bipolar transistor. Forming a SiGe layer on the entire surface of the first polycrystalline semiconductor film including the surface of the semiconductor substrate exposed through the first opening by non-selective vapor phase epitaxy, and the SiGe layer Patterning the first polycrystalline semiconductor film and the first insulating film to expose the first bipolar transistor forming portion and the collector layer surface portion of the second bipolar transistor; and the semiconductor substrate After the second insulating film is formed on the entire upper surface, the second insulating film is patterned to cover the SiGe layer in the ion-implanted base layer and the base formation planned portion of the second bipolar transistor. A step of removing the second insulating film other than the above, and a base of the ion-implanted base layer and the second bipolar transistor. A step of forming a second opening in the second insulating film on the SiGe layer portion in a portion to be formed, and a second polycrystalline semiconductor containing an impurity on the entire surface of the semiconductor substrate including the second opening A step of forming a film, a step of forming an emitter layer on each of the SiGe layer in an ion-implanted base layer and a base formation scheduled portion of the second bipolar transistor through the second opening, and the second polycrystalline semiconductor. Patterning a film to form a collector extraction electrode on the surface of the collector layer, an emitter electrode on the emitter layer, and a gate electrode portion in a gate electrode formation scheduled portion of the insulated gate field effect transistor; The SiGe film on the complementary insulated gate field effect transistor forming portion, the first polycrystal A step of patterning the semiconductor film and the first insulating film; a step of forming low-concentration source / drain regions in the P-channel and N-channel insulated gate field effect transistor forming portions in a self-aligned manner by the gate electrode Forming a sidewall spacer on the sidewalls of the emitter electrode, the collector extraction electrode and the gate electrode portion after forming a third insulating film on the entire surface of the semiconductor substrate; and having the sidewall spacer Exposing the ion-implanted base layer in the first bipolar transistor and the surface of the SiGe layer in the second bipolar transistor by patterning the second insulating film using the emitter electrode as a mask; and Implanted base layer surface portion, the SiGe layer surface portion and Forming serial source / drain region-based electrode and the source / drain electrodes, respectively, characterized by including the.

  According to the present invention, BJT, SiGeHBT, and CMOS can be manufactured on a common semiconductor substrate by a simple process, and contact reliability can be improved.

  A BiCMOS manufacturing method according to an embodiment of the present invention will be described below with reference to FIGS.

  In this embodiment, a BiCMOS in which BJT having a normal configuration, SiGeHBT made of SiGe, and CMOS made of N channel MOS and P channel MOS are formed as semiconductor elements on a common semiconductor substrate is manufactured. . 1 to 11 are schematic process cross-sectional views showing the manufacturing process of the BiCMOS of the present invention.

As shown in FIG. 1, a silicon substrate 10 having an N ⁻ type epitaxial layer 12 formed on a P type silicon substrate 11 is prepared.

In the silicon substrate 10, a high impurity concentration N ⁺ type buried region 13 is formed across the high breakdown voltage BJT formation portion B and the high speed SiGeHBT formation portion H. These N ⁺ -type buried regions 13 are formed by selectively ion-implanting N-type impurities into the silicon substrate 10 by, for example, a normal PEP technique and an ion implantation technique. Further, before the N ⁻ type epitaxial layer 12 is epitaxially grown on the P type silicon substrate 11, N type impurities are diffused on the surface of the P type silicon substrate 11.

Next, a first oxide film, a silicon nitride film, and a TEOS film (not shown) are sequentially stacked on the entire surface of the silicon substrate 10 and then formed on the silicon substrate 10 using a normal PEP technique and an etching technique. , BJT formation portion B, SiGeHBT formation portion H, and CMOS formation portion C are formed so as to surround deep trench 14a, and an insulating material 14b is embedded in deep trench 14a, thereby forming a deep trench element isolation layer (hereinafter simply referred to as a deep trench isolation layer). 14). The deep isolation layer 14 separates the N ⁺ type buried layer 13 into a BJT N type buried layer 13 a and an HBT N ⁺ type buried layer 13 b.

  Furthermore, a portion necessary for element isolation of an electrode lead-out layer forming portion, which will be described later, in the BJT forming portion B and the SiGeHBT forming portion H on the deep isolation layer 14 by the normal PEP technique and etching technique, and the CMOS forming portion C In order to isolate a P-channel MOSFET (hereinafter simply referred to as pMOS) forming portion P and an N-channel MOSFET (hereinafter simply referred to as nMOS) forming portion N, a shallow trench 15a is formed, and the shallow trench 15a is formed in the shallow trench 15a. A shallow trench isolation layer (hereinafter simply referred to as a shallow isolation layer) 15 is formed by embedding the insulating film material 15b.

  The shallow isolation layer 15 may be formed by using a normal PN junction isolation technique or a LOCOS technique.

Next, the N ⁺ -type collector extraction layers 16a and 16b are formed in the BJT formation portion B and the SiGeHBT formation portion H so as to reach the N ⁺ -type buried layers 13a and 13b, respectively, using a normal ion implantation technique.

  Next, using a normal PEP technique and an ion implantation technique, a P-type impurity is ion-implanted into the nMOS formation region N of the CMOS formation portion C to form a P well layer 17. Further, an N-type impurity is ion-implanted into the pMOS formation region P to form an N well layer 18.

  Next, as shown in FIG. 2, a gate insulating film 20 as a first insulating film is formed to a thickness of 9 nm on the entire surface of the silicon substrate 10 thus formed by, for example, a normal thermal oxidation technique. Then, in order to protect the gate insulating film 20 in the CMOS formation portion C continuously by a normal CVD technique, a first polycrystalline silicon film 21 is formed to a thickness of 100 nm.

Further, the first photoresist 22a is patterned by a normal PEP technique to form an opening in a portion where the base region of the BJT formation portion B is to be formed, and then using the first photoresist 22a as a mask, P-type impurity boron (B) is implanted into the surface of the N ⁻ -type epitaxial layer 12 by an implantation technique, for example, at an acceleration voltage of 30 KeV and an implantation amount of 6 × 10 ¹³ / cm ² , and the B-type P-type base diffusion layer 30 is formed. Form. Thereafter, the first photoresist 22a used in the PEP technique is removed by an ashing process.

  Next, as shown in FIG. 3, a new second photoresist 22b is patterned by a normal PEP technique to form an opening in a portion where the base region of the SiGeHBT formation portion H is formed, and then the second photoresist 22b is formed. Using the photoresist 22b as a mask, the polycrystalline silicon film 20 and the gate oxide film 21 in the base region of the SiGeHBT formation portion H are removed by etching using a normal etching technique to form the first opening W1.

Next, as shown in FIG. 4, after the second photoresist 22b used in the PEP technique is removed by ashing, a boron B concentration of 8 × 10 ¹⁸ / cm ³ is selected non-selectively by a vapor phase epitaxial growth method. The P-type SiGe base epitaxial layer 31 is formed. The base epitaxial layer 31 is also formed on the portion of the polycrystalline silicon film 20 other than the base region in the first opening W1 because the vapor phase epitaxial growth is also performed in the lateral (horizontal) direction.

  Next, as shown in FIG. 5, the third photo resist 22c is used to open only the collector extraction layer 16b of the SiGe HBT formation portion H and the BJT formation portion B, and then the third photo resist 22c is used. Using the resist 22c as a mask, the base epitaxial layer 31 and the polycrystalline silicon film 21 are etched away by a normal etching technique. Subsequently, the gate oxide film 20 is removed by etching by buffered hydrofluoric acid treatment. Thereafter, the third photoresist 22c used in the PEP technique is peeled off.

Next, as shown in FIG. 6, a silicon oxide film 23 as a second insulating film is formed to a thickness of 50 nm on the entire surface of the silicon substrate 10 by the CVD technique. Further, the fourth photoresist 22d is patterned by a normal PEP technique to form second openings W2 in portions where the emitter region of the BJT formation portion B and the emitter region of the SiGeHBT formation portion H are formed. At this time, an SIC (Selective Implanted Collector) 24 for suppressing the base push-out effect (Kirk effect) of the bipolar transistor may be implanted at an ionic species phosphorus P at an acceleration voltage of 150 KeV and an implantation amount of 2 × 10 ¹² / cm ^2. Absent.

  Further, the silicon oxide film 23 in the emitter region of the BJT formation portion B and the emitter region of the SiGeHBT formation portion H is etched away by a reactive anisotropic etching (hereinafter referred to as RIE) technique. At this time, in order to avoid RIE damage to the base region, control is performed so that the remaining film of the silicon oxide film 23 of about 20 nm remains. Thereafter, the fourth photoresist 22d used in the PEP technique is removed.

  Next, as shown in FIG. 7, the fifth photoresist 22e is patterned by a normal PEP technique, so that the base region and the emitter region of the BJT formation portion B and the base region and the emitter region of the SiGeHBT formation portion H are formed in the first region. Then, the other silicon oxide film 23 is removed by etching with a normal etching technique using the fifth photoresist 22e as a mask. Thereafter, the fifth photoresist 22e used in the PEP technique is removed by an ashing process.

  Next, as shown in FIG. 8, buffered hydrofluoric acid treatment is performed on the entire surface of the silicon substrate 10 so as not to damage the base region, and the silicon oxide film 23 in the emitter region of the BJT formation portion B and the SiGeHBT formation portion H is formed. The remaining film is completely removed.

Further, a second polycrystalline silicon film 33 is formed to a thickness of 200 nm on the entire surface of the silicon substrate 10 by an ordinary CVD technique, and arsenic (As) is accelerated by an ordinary ion implantation technique at an acceleration voltage of 40 KeV and an implantation amount 1 × 10 ¹⁶ / Implantation is performed so that the arsenic (As) concentration is about 1 × 10 ²⁰ / cm ³ at cm ² . Further, heat treatment is performed at 990 ° C. for 20 seconds by a normal RTA technique, through the second opening W2 of the silicon oxide film 23 on the BJT formation portion B and the second opening W2 of the silicon oxide film 23 on the SiGeHBT formation portion H. Arsenic (As) is implanted to form the emitter region 25 of the BJT formation portion B and the emitter region 26 of the SiGeHBT formation portion H, and to activate the emitter impurities.

  Next, as shown in FIG. 9, the sixth photoresist 22f is formed into a collector electrode lead portion and an emitter electrode lead portion of the BJT formation portion B, the SiGeHBT formation portion H, and a gate electrode of the CMOS formation portion C by a normal PEP technique. Patterning is performed so as to cover only the region where the portion is to be formed.

  Next, by using the photoresist 22f as a mask, the polycrystalline silicon film 33 is etched by a normal RIE technique to form the collector electrode lead portion 34 and the emitter electrode lead portion 35 in the BJT formation portion B and the SiGeHBT formation portion H, respectively. At the same time, the first polycrystalline silicon film 21 and the SiGe base epitaxial layer 31 in the CMOS formation portion C are further etched to form the gate electrode portion 36 in the CMOS formation portion C. This also leaves the SiGe epitaxial layer 31 only on the SiGe HBT formation portion H, and finally becomes the SiGe base layer of the SiGe HBT. Thereafter, the sixth photoresist 22f used in the PEP technique is removed by an ashing process.

  Next, as shown in FIG. 10, a photoresist (not shown) is patterned so as to cover the BJT formation portion B, the SiGeHBT formation portion H, and the nMOS formation portion N by a normal PEP technique, and the pMOS formation portion P is formed. Boron B is implanted under appropriate conditions by a normal ion implantation method to form a P-type low concentration source / drain region (hereinafter referred to as a P-type LDD portion) 37. Similarly, a photoresist (not shown) is patterned so as to cover the BJT formation portion B, the SiGeHBT formation portion H, and the pMOS formation portion P, and phosphorus (P) is appropriately applied to the nMOS formation portion N by a normal ion implantation method. Implantation is performed under conditions to form an N-type low concentration source / drain region (hereinafter referred to as an N-type LDD portion) 38.

  Needless to say, the N-type LDD portion 38 can be formed first, and the P-type LDD portion 37 can be formed thereafter.

  Next, as shown in FIG. 11, a silicon oxide film (not shown) is formed on the entire surface of the P-type silicon substrate 10, and the collector electrode extraction portion 34, the emitter electrode extraction portion 35, and the gate electrode are formed by a normal RIE technique. Sidewall spacers 39 are formed on the side surfaces of the portion 36. When the side wall spacer 39 is formed, the base layer 30 in the BJT formation portion B and the silicon oxide film 23 in a predetermined portion on the SiGe epitaxial layer (base layer) 31 in the SiGe HBT formation portion H are etched to expose the base lead portion 27. To do. Further, the gate oxide film 20 on the LDD portions 37 and 38 in the CMOS formation portion C is removed.

Further, a photoresist (not shown) is patterned so as to cover the BJT formation part B, the SiGeHBT formation part H, and the nMOS formation part N by a normal PEP technique, and BF2 is formed on the pMOS formation part P by a normal ion implantation technique. Are implanted under the conditions of an acceleration voltage of 40 KeV and an implantation amount of 5 × 10 ¹⁵ / cm ² to form a P-type high concentration source / drain region 40. Similarly, a photoresist (not shown) is patterned so as to cover the BJT formation part B, the SiGeHBT formation part H, and the pMOS formation part P by a normal PEP technique, and the nMOS formation part N is patterned by a normal ion implantation technique. Then, arsenic (As) is implanted under the conditions of an acceleration voltage of 40 KeV and an implantation amount of 5 × 15 ¹⁰ / cm ² to form an N-type high concentration source / drain region 41.

  Needless to say, the N-type source / drain region 41 can be formed first, and the P-type source / drain region 40 can be formed thereafter.

  Next, as shown in FIG. 12, titanium (not shown) is formed to a thickness of 100 nm on the entire surface of the silicon substrate 10 by a normal sputtering technique, and further, under the conditions of 650 ° C. and 30 sec by the RTA technique. The upper surface of the collector electrode lead-out portion 34, the upper surface of the P-type base diffusion layer 30, the upper surface of the emitter electrode lead-out portion 35, the upper surface of the SiGe epitaxial layer 31, the upper surface of the gate electrode 36, the P-type high-concentration source / drain region 40, and the N-type high-concentration source / drain. A silicidation reaction is performed on the surface of the region 41 in a self-aligning manner.

  Next, after removing unreacted titanium (not shown) by ordinary acid etching, the salicide process is completed by reducing the resistance by performing a phase transition reaction again at 800 ° C. for 30 sec by the RTA method. The upper surface of the collector electrode leading portion 34, the upper surface of the emitter electrode leading portion 35, the upper surface of the base leading portion 27, the upper surface of the gate electrode portion 36 of the CMOS forming portion C, and the source / drain regions 40, 41 of the BJT forming portion B and the SiGeHBT forming portion H. A titanium silicide layer 42 is formed on the upper surface in a self-aligning manner.

  Next, although not shown in the drawing, an insulating film for surface protection is formed on the entire surface of the silicon substrate 10 by a well-known method, a contact hole for an electrode is formed, and an aluminum electrode wiring is formed. Complete.

  According to the BiCMOS manufacturing method of this embodiment, as shown in FIG. 8, the emitter of the SiGe HBT forming portion H is implanted with arsenic (As) into the polycrystalline silicon film 33, and heat treatment is performed to remove emitter impurities. Since it is activated and formed, a continuous epitaxial growth process for epitaxial growth for forming an emitter on the P-type SiGe base epitaxial layer is not required as in the prior art, and the process can be simplified.

  Further, as shown in FIG. 10, since the collector electrode lead portion 34, the emitter electrode lead portion 35, and the gate electrode portion 36 of the CMOS formation portion C of the BJT formation portion B and the SiGeHBT formation portion H can be formed at the same time. The process can be simplified.

  Further, the collector electrode is not directly contacted with the silicon substrate 10 as in the prior art, but the collector electrode is contacted via the collector electrode lead-out portion 34 using the polycrystalline polysilicon 33 as shown in FIG. As a result, the level difference in the contact formation process is reduced, and the reliability of the contact can be improved.

  It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the spirit of the invention.

FIG. 4 is a schematic process cross-sectional view showing a manufacturing process of BiCMOS according to the present invention. FIG. 4 is a schematic process cross-sectional view showing a manufacturing process of BiCMOS according to the present invention. FIG. 4 is a schematic process cross-sectional view showing a manufacturing process of BiCMOS according to the present invention. FIG. 4 is a schematic process cross-sectional view showing a manufacturing process of BiCMOS according to the present invention. FIG. 4 is a schematic process cross-sectional view showing a manufacturing process of BiCMOS according to the present invention. FIG. 4 is a schematic process cross-sectional view showing a manufacturing process of BiCMOS according to the present invention. FIG. 4 is a schematic process cross-sectional view showing a manufacturing process of BiCMOS according to the present invention. FIG. 4 is a schematic process cross-sectional view showing a manufacturing process of BiCMOS according to the present invention. FIG. 4 is a schematic process cross-sectional view showing a manufacturing process of BiCMOS according to the present invention. FIG. 4 is a schematic process cross-sectional view showing a manufacturing process of BiCMOS according to the present invention. FIG. 4 is a schematic process cross-sectional view showing a manufacturing process of BiCMOS according to the present invention. FIG. 4 is a schematic process cross-sectional view showing a manufacturing process of BiCMOS according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Silicon substrate 11 P type silicon substrate 12 N ^- epitaxial layer 13 N ⁺ type buried region 14 Deep trench element isolation layer 14a Deep trench 14b, 15b Insulating material 15 Shallow trench element isolation layer 15a Shallow trench 16 N ⁺ type collector extraction layer 17 P well layer 18 N well layer 20 Gate insulating films 21 and 33 Polycrystalline silicon film 22 Photoresist 23 Silicon oxide films 25 and 26 Emitter region 27 Base lead portion 28 Source / drain lead portion 30 P type base diffusion layer 31 P type SiGe Base epitaxial layer 34 Collector electrode lead-out portion 35 Emitter electrode lead-out portion 36 Gate electrode portion 37 P-type low concentration source / drain region 38 N-type low concentration source / drain region 39 Side wall spacer 40 P-type high concentration source / Drain region 41 N-type high concentration source / drain region 42 Silicide layer B BJT formation portion H SiGeHBT formation portion P pMOS formation portion N nMOS formation portion C CMOS formation portion

Claims (5)

Complementary insulated gate type composed of a first bipolar transistor of ion implantation base type, a second bipolar transistor of SiGe base heterojunction type, and P channel and N channel type insulated gate field effect transistors on a common semiconductor substrate In a manufacturing method of a semiconductor device having a field effect transistor,
Forming a first insulating film on the entire surface of the semiconductor substrate;
Forming a first polycrystalline semiconductor film over the entire surface of the first insulating film;
Forming a base layer by ion implantation in the first bipolar transistor forming portion;
Patterning the first polycrystalline semiconductor film and the first insulating film to form a first opening in a base forming portion of the second bipolar transistor;
Forming a SiGe layer on the entire surface of the first polycrystalline semiconductor film including the surface of the semiconductor substrate exposed through the first opening by non-selective vapor phase epitaxy;
Patterning the SiGe layer, the first polycrystalline semiconductor film, and the first insulating film to expose the first bipolar transistor forming portion and the collector layer surface portion of the second bipolar transistor;
After forming a second insulating film on the entire surface of the semiconductor substrate, the second insulating film is patterned to cover the SiGe layer in the ion-implanted base layer and the base formation scheduled portion of the second bipolar transistor. Removing the second insulating film other than that portion;
Forming a second opening in the second insulating film on the SiGe layer portion in the base formation scheduled portion of the ion-implanted base layer and the second bipolar transistor;
Forming an impurity-containing second polycrystalline semiconductor film on the entire surface of the semiconductor substrate including the second opening;
Forming an emitter layer on the SiGe layer in the ion-implanted base layer and the base formation scheduled portion of the second bipolar transistor, respectively, through the second opening;
Patterning the second polycrystalline semiconductor film to form a collector extraction electrode on the surface of the collector layer, an emitter electrode on the emitter layer, and a gate electrode portion on the gate electrode formation planned portion of the insulated gate field effect transistor. And a process of
Patterning the SiGe film, the first polycrystalline semiconductor film, and the first insulating film on the complementary insulated gate field effect transistor forming portion using the gate electrode portion as a mask;
Forming low-concentration source / drain regions in P-channel and N-channel insulated gate field effect transistor formation portions in a self-aligned manner by the gate electrode portion;
Forming a third insulating film on the entire surface of the semiconductor substrate, and then forming sidewall spacers on the side walls of the emitter electrode, the collector extraction electrode, and the gate electrode portion;
The second insulating film portion is patterned using the emitter electrode having the sidewall spacer as a mask to expose the surface of the ion-implanted base layer in the first bipolar transistor and the surface of the SiGe layer in the second bipolar transistor. And a process of
Forming a base electrode and a source / drain electrode on the surface of the ion-implanted base layer, the surface of the SiGe layer, and the source / drain region, respectively.
A method for manufacturing a semiconductor device, comprising: The SiGe layer serving as a base layer is formed on the formation portion of the second bipolar transistor by removing the SiGe layer and the first polycrystalline semiconductor film using the gate electrode portion as a mask. A method for manufacturing a semiconductor device according to claim 1. Impurity implantation for forming the emitter layer for the ion-implanted base layer and the SiGe layer from the second polycrystalline semiconductor film through the second opening and impurity implantation for the collector layer surface portion are simultaneously performed. The method of manufacturing a semiconductor device according to claim 1. 2. The semiconductor device according to claim 1, wherein the emitter layer is formed by ion-implanting an emitter impurity into the second polycrystalline semiconductor film and then activating the emitter impurity by heat treatment. 3. Production method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the emitter electrode, the collector extraction electrode, and the gate electrode portion are simultaneously formed by patterning the second polycrystalline semiconductor film.

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