JP2004253707A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof wherein its operational speed can be improved while suppressing its punch through. <P>SOLUTION: The semiconductor device has a p-type silicon substrate 1, a non-doped silicon layer 7 provided on the silicon substrate 1, a gate insulation film 11 provided on the non-doped silicon layer 7, a metal gate electrode 13 provided on the gate insulation film 11, n<SP>+</SP>S/D diffusion layers 5a, 5b provided in the exposed silicon substrate 1 from under the metal gate electrode 13, and a p<SP>+</SP>diffusion layer 9 provided in the silicon substrate 1 present under a channel region. Further, the impurity concentration of the p<SP>+</SP>diffusion layer 9 is made higher than the one of the silicon substrate 1 present under the n<SP>+</SP>S/D diffusion layers 5a, 5b. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device suitable for being applied to a MIS transistor having a so-called channel epi structure in which a channel region is formed of an epitaxial silicon layer and a method of manufacturing the same. is there.
[0002]
[Prior art]
In recent years, the gate length of the MIS transistor is approaching 0.1 μm, and the threshold voltage of the transistor tends to be further reduced. Along with this, MIS transistors having a so-called channel epi structure, in which a channel region of the transistor is formed of an epitaxial silicon layer, are becoming widespread.
[0003]
FIG. 7 is a cross-sectional view illustrating a configuration example of an n-type MIS transistor 90 according to a conventional example. The MIS transistor 90 has a channel epi structure. In the figure, 91 is a silicon substrate (p-sub), 92 is an element isolation layer, 93 is 94⁺Source / drain diffusion layers (hereinafter, n⁺S / D diffusion layer), 95 is a metal gate electrode, 96 is a sidewall, 97 is a non-doped epitaxial silicon layer (hereinafter, referred to as a non-doped silicon layer), and 98 is a gate insulating film.
[0004]
As shown in FIG. 7, in the MIS transistor 90, n⁺Both the S / D diffusion layer 94 and the channel region 95 have a high concentration of p.⁺Since it is bonded to the well diffusion layer 93, n⁺S / D diffusion layer 94 and p⁺Between the well diffusion layer 93 and between the channel region 95 and p⁺The depletion layer between the well diffusion layers 93 is small, and short channel effects such as punch-through are suppressed.
[0005]
The metal gate electrode 95 shown in FIG. 7 is made of a mid-gap material. Here, the mid-gap material means that the work function of the material is n⁺Polysilicon work function and p⁺A metal that is in the middle of the work function of polysilicon. Examples of the mid-gap material include titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).
[0006]
In the manufacturing process of the MIS transistor 90, non-doped silicon is epitaxially grown at a low temperature on a relatively high-concentration silicon surface, and thereafter, a gate insulating film 98, a metal gate electrode 95, a sidewall 96, and n⁺An S / D diffusion layer 94 is formed. This low temperature process prevents diffusion of impurities (dopants) into the non-doped silicon layer 97.
[0007]
By forming the gate electrode portion of the CMIS including the n-type MIS transistor and the p-type MIS transistor with a mid-gap material and making the epitaxial layer 97 non-doped, the threshold voltage of the n-type MIS transistor and the p-type MIS transistor The absolute values of the threshold voltages can be made uniform, and the absolute values can be reduced.
[0008]
[Patent Document 1]
JP-A-9-45905
[Non-patent document 1]
M. Aoki et al, IEDM Tech. Dig. , P. 939-941, 1990.
[0009]
[Problems to be solved by the invention]
By the way, according to the n-type MIS transistor 90 according to the conventional example, in order to suppress a short channel effect such as punch-through, n⁺The semiconductor substrate 91 under the S / D diffusion layer 94 and the semiconductor substrate 91 under the non-doped silicon layer 97 have a high concentration of p.⁺The well diffusion layer 93 was provided.
[0010]
However, although this structure can suppress the short channel effect, n⁺S / D diffusion layer 94 and p⁺Since the depletion layer between the well diffusion layer 93 and the well becomes small, there is a problem that the junction capacitance (parasitic capacitance) is large. n⁺There is a correlation between the junction capacitance of the S / D diffusion layer 94 and the operation speed of the MIS transistor 90, and n⁺The operating speed of the MIS transistor 90 decreases as the junction capacitance of the S / D diffusion layer 94 increases.
[0011]
SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device capable of improving an operation speed while suppressing punch-through and a method of manufacturing the same.
[0012]
[Means for Solving the Problems]
In order to solve the above-described problem, a first semiconductor device according to the present invention includes a semiconductor substrate, a gate insulating film provided on the semiconductor substrate, and a gate electrode portion provided on the gate insulating film. A source / drain diffusion layer provided on the semiconductor substrate exposed from below the gate electrode portion, and an impurity diffusion layer provided on the semiconductor substrate below the channel region, wherein the impurity diffusion layer is provided below the source / drain diffusion layer. The semiconductor substrate is of the same conductivity type as the semiconductor substrate, and the impurity concentration of the impurity diffusion layer is higher than that of the semiconductor substrate below the source / drain diffusion layers.
[0013]
According to a second semiconductor device of the present invention, in the first semiconductor device described above, the semiconductor substrate includes a silicon substrate and a silicon layer provided on the silicon substrate, and impurity diffusion is performed on a predetermined region of the silicon substrate. A silicon layer on the impurity diffusion layer becomes a channel region.
According to the first and second semiconductor devices according to the present invention, lines of electric force from the drain generated when a voltage is applied between the source and the drain can be terminated at the impurity diffusion layer below the channel region. , Punch-through can be prevented. Further, as compared with the conventional semiconductor device, the depletion layer between the source / drain diffusion layer and the semiconductor substrate (silicon substrate) can be extended toward the substrate, so that the junction capacitance of the source / drain diffusion layer can be reduced. it can. Therefore, the operation speed of the semiconductor device can be improved while suppressing punch-through.
[0014]
A first method for manufacturing a semiconductor device according to the present invention includes a step of forming an impurity diffusion layer of the same conductivity type as a silicon substrate in a predetermined region of a silicon substrate, and a step of forming silicon on the silicon substrate on which the impurity diffusion layer is formed. A step of forming a layer, a step of forming a gate insulating film on the silicon layer, a step of forming a gate electrode portion on the gate insulating film above the impurity diffusion layer, and a step of forming a silicon layer exposed from under the gate electrode portion; Forming a source / drain diffusion layer in the silicon substrate, wherein in the step of forming the impurity diffusion layer, the impurity concentration of the impurity diffusion layer is higher than that of the silicon substrate below the source / drain diffusion layer. It is characterized by the following.
[0015]
According to the first method for manufacturing a semiconductor device of the present invention, the impurity diffusion layer having the same conductivity type as the silicon substrate and having a higher impurity concentration than the silicon substrate below the source / drain diffusion layers is formed below the gate electrode portion. Therefore, a semiconductor device in which punch-through is suppressed and operation speed is high can be provided.
A second method of manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film on the silicon substrate so as to open only a predetermined region of the silicon substrate and cover the other region; Forming an impurity diffusion layer of the same conductivity type as that of the silicon substrate in a region exposed from the substrate, and etching the silicon substrate having an impurity diffusion layer formed in a region exposed from under the insulating film by a predetermined thickness. Forming a groove, forming a silicon layer on a silicon substrate so as to fill the groove, forming a gate insulating film on the silicon layer, and forming a gate electrode on the gate insulating film And forming a source / drain diffusion layer on the silicon layer and the silicon substrate exposed from under the gate electrode portion. In the step of forming the impurity diffusion layer, It is characterized in that a higher concentration than the silicon substrate under the impurity concentration source / drain diffusion layer of the impurity diffusion layer.
[0016]
According to the second method for manufacturing a semiconductor device of the present invention, the same operation and effect as those of the first semiconductor device described above can be obtained. Further, the impurity diffusion layer and the gate electrode portion can be overlapped with each other in a self-aligned manner by the insulating film having the opening. A third method for manufacturing a semiconductor device according to the present invention is the method for manufacturing a semiconductor device according to the above-described second semiconductor device, further comprising: forming an insulating sidewall on a side wall of an opening of the insulating film after forming the gate insulating film. Thereafter, a gate electrode portion is formed so as to cover the sidewall.
[0017]
According to the third method for manufacturing a semiconductor device of the present invention, the junction region between the gate insulating film and the gate electrode portion is narrowed toward the center of the opening of the insulating film by the sidewall. Therefore, it is possible to increase a margin for overlapping the gate electrode portion and the impurity diffusion layer.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention will be described with reference to the drawings.
(1) First embodiment
FIG. 1 is a sectional view showing a configuration example of an n-type MIS transistor 100 according to the first embodiment of the present invention. The MIS transistor 100 has a so-called channel epi structure in which the channel region is formed of an epitaxial silicon layer.
[0019]
In FIG. 1, 1 is a silicon substrate, 3 is an element isolation layer, 5a and 5b are n⁺S / D diffusion layer, 7 is non-doped silicon layer, 9 is p⁺A diffusion layer, 11 is a gate insulating film, 13 is a metal gate electrode, 15 is a sidewall spacer, 16a and 16b are Ni silicide, 17 is an interlayer insulating film, and 19a and 19b are wiring layers. On the silicon substrate 1 shown in FIG. 1, in addition to the n-type MIS transistor 100, a p-type MIS transistor (not shown), a capacitance element (not shown), a resistance element (not shown) and the like are integrally formed. The semiconductor device of the present invention is constituted by the plurality of transistors and elements.
[0020]
In FIG. 1, a silicon substrate 1 is a bulk p-type silicon wafer containing a small amount of a p-type impurity such as boron (B), and has a single crystal structure. The boron concentration of this p-type silicon substrate 1 is, for example, 1E + 15 cm.^-3It is about. The element isolation layer 3 is a silicon oxide film embedded in the silicon substrate 1. The thickness of the element isolation layer 3 is, for example, about 10,000 °.
[0021]
Further, n⁺The S / D diffusion layers 5a and 5b are high-concentration n-type impurity diffusion layers provided on the silicon substrate 1 in a region (hereinafter, also referred to as an element formation region) separated by the element separation layer 3. As shown in FIG.⁺The S / D diffusion layers 5a and 5b have a lightly doped drain (LDD) structure, and suppress generation of hot electrons. This n⁺The n-type impurity contained in the S / D diffusion layer 5 is, for example, phosphorus (P), arsenic (As), or the like.
[0022]
This n⁺In the S / D diffusion layers 5a and 5b, the junction depth (Xj) of the low-concentration region (hereinafter referred to as "extension") which is connected to the channel region of the MIS transistor 100 is, for example, about 200 [deg.] Is 5E + 19cm^-3It is about.
Also, this n⁺Xj of the high-concentration regions (hereinafter referred to as deep source / drain) which are the S / D diffusion layers 5a and 5b and are joined to the extension is, for example, about 600 °, and the impurity concentration thereof is 1E + 20 cm.^-3It is about.
[0023]
The non-doped silicon layer 7 shown in FIG. 1 is a single-crystal silicon layer formed on the surface of the silicon substrate 1 by, for example, epitaxial growth. This non-doped silicon layer 7 hardly contains impurities such as phosphorus, arsenic, and boron.
The non-doped silicon layer 7 is a channel region of the MIS transistor 100, and has a thickness such that when a MIS transistor having the same gate length is formed in FDSOI (Fully Depleted-Silicon On Insulator), the SOI becomes sufficiently small. About the same as the thickness of the layer (top silicon layer). Here, the S-factor is a gate voltage change amount required to change the drain current of the MIS transistor by one digit. For example, when the gate length of the MIS transistor 100 is about 0.1 μm, the thickness of the non-doped silicon layer 7 is about 100 to 200 °.
[0024]
p⁺The diffusion layer 9 is a high-concentration p-type impurity diffusion layer provided on the silicon substrate 1 in a region immediately below the non-doped silicon layer 7. This p⁺The diffusion layer 9 has Xj of, for example, about 10000 ° and an impurity concentration of, for example, 1E + 18 cm.^-3It is about. This p⁺The p-type impurity contained in the diffusion layer 9 is, for example, boron.
As shown in FIG. 1, the gate insulating film 11⁺It is provided on the non-doped silicon layer 7 above the diffusion layer 9. The gate insulating film 11 is, for example, a silicon nitride film and has a thickness of about 35 °. Further, the metal gate electrode 13 is provided on the gate insulating film 11. The metal gate electrode 13 is made of a mid-gap material, like the metal gate electrode 95 of the MIS transistor 90 described above. For example, this metal gate electrode has a three-layer structure of TaN / Ta / TaN.
[0025]
By the way, in the MIS transistor 100, the p concentration which is relatively higher than the substrate concentration of the silicon substrate 1 is⁺A diffusion layer 9 is provided immediately below the non-doped silicon layer 7. Therefore, when a voltage is applied between the source and the drain, the line of electric force from the drain is p⁺The termination can be made at the diffusion layer 9 and punch-through can be prevented.
[0026]
Also, n⁺The semiconductor substrate (p-sub) 1 is located immediately below the deep source / drain of the S / D diffusion layers 5a and 5b.⁺The concentration is lower than that of the diffusion layer 9. Therefore, as compared with the conventional MIS transistor 90, the depletion layer extends below the deep source / drain, so that n⁺The junction capacitance of S / D diffusion layers 5a and 5b can be reduced. Thus, the operation speed of the transistor can be improved.
[0027]
In the first embodiment, the case of the n-type MIS transistor 100 has been described. However, the field effect transistor of one conductivity type of the present invention is not limited to the n-type, but may be a p-type MIS transistor. In this case, in FIG. 1, the conductivity type of the silicon substrate 1 and each impurity diffusion layer is changed from n-type to p-type or from p-type to n-type. Thus, a p-type MIS transistor having a small source-drain junction capacitance and a suppressed short-channel effect such as punch-through can be realized.
[0028]
In the first embodiment, the p-type silicon substrate 1 and the non-doped silicon layer 7 correspond to the semiconductor substrate of the present invention, and the non-doped silicon layer 7 corresponds to the silicon layer (channel region) of the present invention. Further, the metal gate electrode 13 corresponds to the gate electrode portion of the present invention, and n⁺The S / D diffusion layers 5a and 5b correspond to the source / drain diffusion layers of the present invention. Furthermore, p⁺The diffusion layer 9 corresponds to the impurity diffusion layer of the present invention.
[0029]
Next, a method for manufacturing the above-described n-type MIS transistor 100 will be described with reference to FIGS. As shown in FIG. 2A, first, a silicon substrate 1 is prepared. This silicon substrate 1 is a bulk silicon wafer. Next, a trench (groove) is formed on the surface of the silicon substrate 1 other than the element formation region, and a silicon oxide film is buried in the trench to form an element isolation layer 3.
[0030]
Next, as shown in FIG. 2B, a resist pattern 41 is formed on the silicon substrate 1 so as to open a region serving as a channel of the MIS transistor 100. The formation of the resist pattern 41 is performed by, for example, a lithography technique using a stepper. Then, using this resist pattern 41 as a mask, B⁺Or BF₂ ⁺Is ion-implanted.
[0031]
B in this ion implantation⁺Or BF₂ ⁺And the processing conditions such as implantation energy are determined from the viewpoints of suppression of the short-channel effect and source / drain breakdown voltage. Also, the p formed by this ion implantation⁺It is desirable that the diffusion layer 9 has a small dimension width and the dimension depth is as deep as possible. However, if the ion implantation energy is increased to form the diffusion layer 9 deeper, the diffusion layer 9 spreads laterally. In this example, for example, the dose amount is 1E + 13 cm.^-2, The injection energy is
50 to 500 KeV, and the driving angle is 0 to 7 °.
[0032]
Next, B⁺Or BF₂ ⁺After the ion implantation, the silicon substrate 1 is ashed to remove the resist pattern 41. Then, the silicon substrate 1 is annealed at a high temperature of, for example, about 850 ° C. to 950 ° C.⁺The diffusion layer 9 is formed.
Next, as shown in FIG. 2C, a non-doped silicon film 7 'is formed to a thickness of about 10 to 20 nm on the silicon substrate 1 in the element formation region. This non-doped silicon film 7 'is formed by, for example, selective epitaxial growth. Here, the selective epitaxial growth of the non-doped silicon film 7 ′ is performed at a low temperature of, for example, about 600 ° C. This is⁺This is for preventing the diffusion of boron from the diffusion layer 9 to the non-doped silicon film 7 '. In addition, all processes after the formation of the non-doped silicon film 7 'are performed at a low temperature of, for example, 550.degree. This prevents the diffusion of the dopant into the non-doped silicon film 7 '.
[0033]
Next, as shown in FIG. 3A, a gate insulating film 11 made of a silicon nitride film is formed on the non-doped silicon film 7 'to a thickness of about 35 nm. The gate insulating film 11 is formed by, for example, plasma nitridation or sputtering. The film forming temperature of the gate insulating film 11 is, for example, about room temperature to about 400 ° C.
After the gate insulating film 11 is formed, a mid-gap material is formed on the gate insulating film 11. The mid-gap material used here is a film having a three-layer structure of, for example, TaN / Ta / TaN. The film is not limited to such a three-layer film, but may be a single-layer film made of TiN, Ta, TaN, or the like. This kind of mid-gap material is formed, for example, by sputtering.
[0034]
Next, using a lithography technique and a dry etching technique, the mid-gap material is patterned into an electrode shape to form a metal gate electrode 13. Then, using the metal gate electrode 13 as a mask, an n-type impurity such as phosphorus is ion-implanted into the silicon substrate 1 as shown in FIG.
This ion implantation step includes n⁺This is a step for forming an extension of the S / D diffusion layer 5. The processing conditions for this ion implantation step are, for example, a dose amount of 4E + 14 cm.^-2The implantation energy is 5 KeV and the implantation angle is 7 °.
[0035]
Next, a silicon oxide film or a silicon nitride film is deposited on the silicon substrate 1 including the metal gate electrode 13 by CVD. Also here, the film formation temperature is set to a low temperature of, for example, about 400 ° C. so that diffusion of the dopant into the non-doped silicon layer 7 does not occur. Then, the deposited silicon oxide film is etched back to form a sidewall spacer 15 on the side wall of the metal gate electrode 13 as shown in FIG.
[0036]
Next, an n-type impurity such as arsenic is ion-implanted into the silicon substrate 1 using the metal gate electrode 13 on which the sidewall spacers 15 are formed as a mask. This ion implantation step includes n⁺This is a step for forming a deep source / drain of the S / D diffusion layer 5. This ion implantation step includes n⁺This is a step for forming a deep source / drain of the S / D diffusion layer 5. The processing conditions of this ion implantation step are, for example, a dose amount is 2E + 15 cm.^-2The implantation energy is 25 KeV and the implantation angle is 7 °.
[0037]
Next, the silicon substrate 1 is annealed at a low temperature of about 500 ° C.⁺The S / D diffusion layers 5a and 5b are formed. Generally, when annealing after ion implantation is performed at a low temperature of about 500 ° C., it is known that a point defect entangled with a dopant of a semiconductor substrate remains, and a higher dopant concentration increases a leak current. However, in the MIS transistor 100, n⁺The semiconductor substrate 1 is below the S / D diffusion layers 5a and 5b, and has a lower dopant concentration than the conventional MIS transistor 90 (see FIG. 7). Therefore, n⁺The leak current in the S / D diffusion layer 5 can be reduced.
[0038]
Next, about 20 nm of Ni is formed on the silicon substrate 1 by sputtering. Then, heat treatment is performed at about 300 to 500 ° C. to form Ni silicides 16a and 16b (see FIG. 1) on the n + S / D diffusion layers 5a and 5b, respectively. Subsequently, unreacted Ni is selectively removed by etching with an aqueous solution of hydrochloric acid.
Next, an interlayer insulating film 17 (see FIG. 1) is deposited on the silicon substrate 1 by CVD at about 8000 °. Then, the interlayer insulating film 17 is planarized by CMP or the like. Further, a contact hole is formed in the interlayer insulating film 17 by a lithography technique and a dry etching technique. Thereafter, a metal film such as an aluminum alloy film is deposited on the interlayer insulating film 17 in which the contact hole is formed by a sputtering method or the like. Then, the aluminum alloy film is patterned by lithography and dry etching to form wiring layers 19a and 19b. Thus, the n-type MIS transistor shown in FIG. 1 is completed.
[0039]
According to the present invention, since the MIS transistor is formed on the bulk silicon substrate 1 unlike the case where the MIS transistor is formed on the SOI substrate, n⁺Even when the extension thickness of the S / D diffusion layers 5a and 5b is equal to or larger than the thickness of the epitaxial silicon layer 7, the S / D diffusion layers 5a and 5b can be recrystallized by low-temperature solid-layer epitaxial growth. If the impurity is ion-implanted to the depth to reach the depth, the single crystal seed layer necessary for solid-layer epitaxial growth is lost, so that recrystallization is difficult.)
[0040]
Therefore, n⁺The extension of the S / D diffusion layers 5a and 5b and the deep source / drain can be formed thicker, and the source / drain resistance can be reduced. Thus, the problem of junction leakage due to silicide can be avoided without employing an elevated source / drain structure.
Further, as described above, according to the present invention, the p-type impurity having a relatively higher concentration than that of the silicon substrate 1 is provided immediately below the non-doped silicon layer 7 as compared with the MIS transistor 90 of the conventional method.⁺Since the diffusion layer 9 is provided, punch-through can be prevented. Further, n⁺Since the lower side of the S / D diffusion layers 5a and 5b has a relatively low concentration, the depletion layer extends toward the silicon substrate 1, and the junction capacitance can be reduced.
[0041]
As described above, according to the present invention, it is possible to realize a metal gate bulk MISFET in which the source / drain resistance, the junction leak, and the junction capacitance are small and the short channel effect is suppressed.
(2) Second embodiment
In the first embodiment described above, p⁺The case where the alignment between the diffusion layer 9 and the metal gate electrode 13 is performed has been described. However, as is well known, there is a limit in the accuracy of lithography overlay, and as MIS transistors become finer, p⁺There is a possibility that the misalignment of the overlap between the diffusion layer 9 and the metal gate electrode 13 may cause a problem.
[0042]
4A to 6C are process diagrams showing a method for manufacturing the MIS transistor 100 'according to the second embodiment. Here, the above-described metal gate electrode 13 is⁺It is assumed that the MIS transistor 100 'is formed above the diffusion layer 9 in a self-aligned manner. Therefore, in FIGS. 4A to 6C, those having the same functions as those of the MIS transistor 100 shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0043]
As shown in FIG. 4A, first, a silicon substrate 1 having a low dopant concentration is prepared. Next, an element isolation layer 3 is formed on the silicon substrate 1, and a silicon oxide film (SiO₂) 53 and a silicon nitride film (SiN) 55 are formed. The silicon oxide film 53 is formed to a thickness of about 10 nm by thermal oxidation. The silicon nitride film 55 is formed to a thickness of about 10 nm by CVD. In FIG. 4A, SiN / SiO₂The two-layer structure is used to stop the etch-back on the silicon nitride film 55 when forming the sidewall made of the silicon oxide film in FIG. 5B. Therefore, in FIG. 4A, amorphous silicon may be used instead of the silicon nitride film 55.
[0044]
Next, as shown in FIG. 4B, a resist pattern 57 is formed on the silicon nitride film 55 by lithography so as to open only the region where the non-doped silicon layer 7 is to be formed. Then, using this resist pattern 57 as a mask, SiN / SiO₂Is dry-etched to form an opening through which the silicon substrate 1 is exposed.
[0045]
Further, the SiN / SiO₂The silicon substrate 1 exposed from the opening is dry-etched to form a groove 59 having a depth of about 10 nm. In FIG. 4B, the dimensional width of the groove 59 is, for example, about 0.1 μm.
Next, a region of higher density for the punch-through stopper, here p⁺In order to form the diffusion layer 9, an impurity such as boron is ion-implanted using the resist pattern 57 as a mask. In this ion implantation step, when a SOI layer thick wafer for PDSOI (Partially Depleted-SOI) is used as the silicon substrate 1, the impurity ions reach the insulating layer (BOX layer). Also, this p⁺As in the first embodiment, the concentration of the diffusion layer 9, that is, the dose in this ion implantation step, the implantation energy, and the like are determined from the viewpoints of the short channel effect suppression and the source / drain breakdown voltage. After the ion implantation, the resist pattern 57 is removed by ashing. Then, the dopant implanted into the trench 59 is activated by low-temperature annealing or RTA (rapid thermal anneal), and as shown in FIG.⁺The diffusion layer 9 is formed.
[0046]
Next, as shown in FIG. 5A, a non-doped silicon film 7 'is selectively epitaxially grown on the surface of the silicon substrate 1 so as to fill the groove 59 formed in the silicon substrate 1. The thickness of the non-doped silicon film 7 'may be any thickness as long as it is equal to or larger than the inversion layer.
Next, a silicon oxide film is deposited on the silicon substrate 1 and etched back to form a SiN / SiO 2 film.₂A sidewall 61 is formed on the side wall of the opening provided in the substrate. Due to the sidewall 61, the junction region between the gate insulating film 11 and the metal gate electrode 13 is p⁺It is narrowed with respect to the diffusion layer 9. By increasing the lateral dimension width of the side wall 61, the junction region between the gate insulating film 11 and the metal gate electrode can be changed to SiN / SiO.₂Can be narrowed toward the center of the opening provided in the metal gate electrode and p.⁺It is possible to increase a margin for superimposition with the diffusion layer 9.
[0047]
Then, the gate insulating film 11 is formed at a low temperature by plasma nitridation or the like. After the gate insulating film 11 is formed, a mid-gap material such as TaN / Ta / TaN is formed and patterned by lithography and dry etching to form a metal gate electrode 13 as shown in FIG. I do.
In the step of patterning the mid-gap material, SiN / SiO 2 is used as an exposure mask (reticle).₂The exposure mask used when dry-etching, ie, the exposure mask for forming the resist pattern 57 shown in FIG. 4B can be used as it is. As a result, manufacturing costs can be reduced.
[0048]
Also, SiN / SiO on the silicon substrate 1₂And this SiN / SiO₂Of the metal gate electrode 13 and p⁺Since the alignment with the diffusion layer 9 is performed in a self-aligned manner, the metal gate electrode 13 remains at p⁺It can be formed with high reproducibility above the diffusion layer 9.
[0049]
After forming the metal gate electrode 13, the silicon nitride film 55 is removed. The removal of the silicon nitride film 55 is performed using, for example, hot phosphoric acid. Subsequently, the silicon oxide film 53 and the side wall 61 are removed. These removals are performed using, for example, DHF (dilute hydrofluoric acid aqueous solution). This exposes the surfaces of the silicon substrate 1 and the element isolation layer 3 as shown in FIG.
[0050]
Next, as shown in FIG. 6B, using the metal gate electrode 13 as a mask, an n-type impurity such as phosphorus is ion-implanted into the silicon substrate 1 by TILT (tilt). This ion implantation step includes n⁺This is a step for forming an extension of the S / D diffusion layer 5. In this step, p serving as a punch-through stopper⁺Since the diffusion layer 9 is formed in the silicon substrate 1, n-type impurities such as phosphorus can be implanted deeply. This gives p⁺The source / drain resistance can be reduced as compared with the case where the diffusion layer 9 is not provided.
[0051]
Subsequent steps are the same as in the first embodiment. That is, a silicon oxide film or a silicon nitride film is deposited on the silicon substrate 1 including the metal gate electrode 13 by CVD. Then, the deposited silicon oxide film is etched back to form a sidewall spacer 15 on the side wall of the metal gate electrode 13 as shown in FIG.
[0052]
Further, an n-type impurity such as arsenic is ion-implanted into the silicon substrate 1 using the sidewall spacer 15 and the metal gate electrode 13 as a mask. Then, the silicon substrate 1 is annealed at a low temperature of about 500 ° C.⁺The S / D diffusion layers 5a and 5b are formed. By this low-temperature annealing, the lateral interface of the non-doped silicon film 7 'embedded in the trench becomes n⁺It is taken into the S / D diffusion layers 5a and 5b. Therefore, even if the crystallinity at the interface of the non-doped silicon film 7 'is poor, the problem of junction leakage does not occur.
[0053]
Next, Ni silicide (not shown) is formed on n + S / D diffusion layers 5a and 5b. Then, an interlayer insulating film (not shown) is deposited on the silicon substrate 1 by CVD, and a flattening process is performed. Further, a contact hole is formed in the interlayer insulating film by a lithography technique and a dry etching technique. Thereafter, an aluminum alloy film or the like is deposited and patterned on the interlayer insulating film in which the contact hole has been formed to form a wiring layer (not shown). Thus, the MIS transistor 100 'is completed.
[0054]
According to the method for manufacturing the MIS transistor 100 ′ according to the second embodiment of the present invention, the same operation and effect as those of the MIS transistor 100 and the method for manufacturing the MIS transistor described in the first embodiment can be obtained. Further, according to the method of manufacturing MIS transistor 100 ′, metal gate electrode 13 is formed using silicon oxide film 53, silicon nitride film 55, and sidewall 61.⁺Since it is formed in a self-aligned manner above the diffusion layer 9, the metal gate electrode 13 and p⁺It is possible to increase a margin for superimposition with the diffusion layer 9. In the second embodiment, the silicon oxide film 53 and the silicon nitride film 55 (SiN / SiO₂) Corresponds to the insulating film of the present invention, and the sidewall 61 corresponds to the sidewall of the present invention.
[0055]
In the first and second embodiments described above, the case where the gate insulating films of the MIS transistors 100 and 100 ′ are formed of a silicon nitride film is described, but the constituent material of the gate insulating film is not limited to this. . For example, the gate insulating film may be a silicon oxide film. In this case, it is possible to provide a MOS transistor in which the source / drain resistance, the junction capacitance and the junction leak are small and the short channel effect is suppressed.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a configuration example of a MIS transistor 100.
FIG. 2 is a process chart showing a method (part 1) of manufacturing the MIS transistor 100.
FIG. 3 is a process chart showing a method (part 2) of manufacturing MIS transistor 100.
FIG. 4 is a process chart showing a method (part 1) of manufacturing the MIS transistor 100 ′.
FIG. 5 is a process chart showing a method (part 2) of manufacturing MIS transistor 100 ′.
FIG. 6 is a process chart showing a method (part 3) of manufacturing MIS transistor 100 ′.
FIG. 7 is a cross-sectional view illustrating a configuration example of a MIS transistor 90 according to a conventional example.
[Explanation of symbols]
1 silicon substrate, 3 element isolation layers, 5a, 5bn⁺S / D diffusion layer, 7 non-doped silicon layer, 7 'non-doped silicon film, 9 p⁺Diffusion layer, 11 gate insulating film, 13 metal gate electrode, 15 sidewall spacer, 16a, 16b Ni silicide, 17 interlayer insulating film, 19a, 19b wiring layer, 41, 57 resist pattern, 53 silicon oxide film, 55 silicon nitride film , 59 groove, 61 sidewall, 100, 100 'MIS transistor

Claims (5)

A semiconductor substrate;
A gate insulating film provided on the semiconductor substrate,
A gate electrode portion provided on the gate insulating film;
Source / drain diffusion layers provided on the semiconductor substrate exposed from under the gate electrode portion;
An impurity diffusion layer provided on the semiconductor substrate below the channel region,
The impurity diffusion layer is of the same conductivity type as the semiconductor substrate under the source / drain diffusion layer, and the impurity concentration of the impurity diffusion layer is higher than that of the semiconductor substrate under the source / drain diffusion layer. Characteristic semiconductor device. The semiconductor substrate includes a silicon substrate and a silicon layer provided on the silicon substrate,
2. The semiconductor device according to claim 1, wherein the impurity diffusion layer is provided in a predetermined region of the silicon substrate, and a silicon layer on the impurity diffusion layer serves as the channel region. Forming an impurity diffusion layer of the same conductivity type as the silicon substrate in a predetermined region of the silicon substrate;
Forming a silicon layer on the silicon substrate on which the impurity diffusion layer is formed,
Forming a gate insulating film on the silicon layer;
Forming a gate electrode portion on a gate insulating film above the impurity diffusion layer;
Forming a source / drain diffusion layer on the silicon layer and the silicon substrate exposed from under the gate electrode portion,
In the step of forming the impurity diffusion layer,
A method of manufacturing a semiconductor device, wherein the impurity concentration of the impurity diffusion layer is higher than that of a silicon substrate below the source / drain diffusion layers. Forming an insulating film on the silicon substrate so as to open only a predetermined region of the silicon substrate and cover other regions;
Forming an impurity diffusion layer of the same conductivity type as the silicon substrate in a region exposed from under the insulating film of the silicon substrate;
Forming a groove by etching a silicon substrate in a region exposed from under the insulating film and having the impurity diffusion layer formed thereon by a predetermined thickness;
Forming a silicon layer on the silicon substrate so as to fill the groove,
Forming a gate insulating film on the silicon layer;
Forming a gate electrode portion on the gate insulating film;
Forming a source / drain diffusion layer on the silicon layer and the silicon substrate exposed from under the gate electrode portion,
In the step of forming the impurity diffusion layer,
A method of manufacturing a semiconductor device, wherein the impurity concentration of the impurity diffusion layer is higher than that of a silicon substrate below the source / drain diffusion layers. After the gate insulating film is formed, an insulating sidewall is formed on a side wall of the opening of the insulating film, and thereafter, the gate electrode portion is formed so as to cover the sidewall. Item 5. The method for manufacturing a semiconductor device according to Item 4.

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